Initial commit of files

SoftwareDefined/HackRF/gsg-sdr/README

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+materials for Great Scott Gadgets Software Defined Radio course

SoftwareDefined/HackRF/hackrf-2015.07.2/COPYING

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+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+     51 Franklin Street, Boston, MA  02110-1301  USA
+ Everyone is permitted to copy and distribute verbatim copies
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+
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+	    How to Apply These Terms to Your New Programs
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+    This is free software, and you are welcome to redistribute it
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+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, the commands you use may
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+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  <signature of Ty Coon>, 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs.  If your program is a subroutine library, you may
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+library.  If this is what you want to do, use the GNU Library General
+Public License instead of this License.

SoftwareDefined/HackRF/hackrf-2015.07.2/RELEASENOTES

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+HackRF 2015.07.2 Release Notes
+
+Bonus release!  This release contains fixes for CMake configuration bugs that
+affected installation of 2015.07.1 on some platforms.
+
+
+==============================
+HackRF 2015.07.1 Release Notes
+
+To upgrade to this release, you must update libhackrf and hackrf-tools on your
+host computer.  You must also update firmware on your HackRF.  It is important
+to update both the host code and firmware for this release to work properly.
+If you only update one or the other, you may experience unpredictable
+behaviour.
+
+Major changes in this release include:
+
+- Multiple HackRF support.  Users with more than one HackRF can target a
+  specific device from software using the device serial number.  The serial
+  number is easy to find with hackrf_info.  Thanks, Hessu!
+
+- Linux kernel module detaching.  A work-around to avoid the unofficial HackRF
+  kernel module in recent kernel versions that has been causing problems for
+  many users.
+
+- Updating the CPLD is now possible from Windows.  There is no CPLD update with
+  this release, but Windows users should now be able to update.
+
+- Support for rad1o hardware, the badge of CCCamp 2015 based on HackRF One.
+  This package contains host software supporting rad1o; for firmware and other
+  resources, refer to: https://rad1o.badge.events.ccc.de/
+
+There have been many more enhancements and bug fixes, for a full list of
+changes, see the git log.
+
+
+==============================
+HackRF 2014.08.1 Release Notes
+
+To upgrade to this release, you must update libhackrf and hackrf-tools on your
+host computer.  You must also update firmware and the CPLD.  It is important to
+update both the firmware and the CPLD for this release to work properly.  If
+you only update one or the other, you may experience an inverted baseband
+spectrum.
+
+For a complete list of changes, see the git log.  Highlights include:
+
+- HackRF now uses high side injection when tuning to frequencies below 2150
+  MHz.  This significantly reduces images on both RX and TX that resulted from
+  harmonics of the front-end local oscillator.  If you ever wondered why you
+  were picking up broadcast FM stations at frequencies well outside the FM
+  broadcast band, they were probably such images.
+
+- A CLKIN firmware bug was fixed.  The bug prevented switching to the external
+  clock source.  Switching now works automatically at the start of every TX or
+  RX operation.  If a clock signal is detected on CLKIN, that external source
+  is used.  If a clock signal is not detected on CLKIN, the internal crystal is
+  used.
+
+- hackrf_transfer now has a signal source mode that transmits a CW signal.
+  Thanks, dovecho!
+
+- The optional udev rules file was moved from hackrf-tools to libhackrf.
+
+
+==============================
+HackRF 2014.04.1 Release Notes
+
+To upgrade to this release, you must install updates to the software on your
+host computer including libhackrf, hackrf-tools, and any other software (e.g.
+gr-osmosdr) that uses libhackrf.  You must also update firmware and the CPLD
+(which should be updated after firmware and host software is updated).
+
+For a complete list of changes, see the git log.  Highlights include:
+
+- The sample format has changed from unsigned 8 bit integers to signed 8 bit
+  integers.  This affects all HackRF software and changes the file format used
+  by hackrf_transfer.  If you need to convert a file from unsigned bytes to
+  signed bytes, I recommend sox:
+
+  $ sox old.ub new.sb
+
+- HackRF One is now supported and is the default target platform when compiling
+  firmware.  To compile firmware for Jawbreaker, set the BOARD variable:
+
+  $ make -e BOARD=JAWBREAKER
+
+- HackRF One hardware design and documentation are complete.  It is now the
+  preferred platform.
+
+- Automatic clock synchronization is enabled in the firmware.  To activate
+  clock synchronization, simply connect an SMA cable from CLKOUT on one HackRF
+  One to CLKIN on another HackRF One.  The clock signal is a 10 MHz square wave
+  at 3.3 V DC.  This also works on Jawbreaker but requires the installation of
+  SMA connectors and a few other components noted in the schematic diagram.
+
+- The automatic tuning algorithm is improved for frequencies above 2150 MHz.
+  The algorithm (in firmware) automatically avoids spurs caused by harmonic
+  relationships between oscillator frequencies in the analog RF section.
+  Similar improvements below 2150 MHz will require further effort.
+
+- An explicit tuning option is now available to select tuning parameters
+  different from those chosen by the automatic tuning algorithm.  Automatic
+  tuning should be preferred for most use cases, but advanced users can use
+  explicit tuning when there is a need, for example, to avoid a particular
+  local oscillator frequency for a specific application.  Explicit tuning is
+  implemented only in hackrf_transfer so far.
+
+- Antenna port power on HackRF One can be enabled or disabled during RX or TX.
+  This is implemented in hackrf_transfer.  When activated, 3.0 to 3.3 V DC is
+  supplied to the antenna port.  This can safely supply up to 50 mA, enabling
+  equipment including some active antennas.
+
+- The firmware compilation and installation instructions have changed.  See
+  firmware/README and firmware/cpld/README for details.
+
+Known bug: CPLD update does not work on Windows.  See:
+https://github.com/mossmann/hackrf/issues/113
+
+Many thanks to Ben Gamari and Jared Boone for their considerable efforts to
+improve the firmware in this release!
+
+
+==============================
+HackRF 2013.07.1 Release Notes
+
+A firmware update is required to take advantage of features of this release and
+for compatibility with future software based on this release.
+
+For a complete list of changes, see the git log.  Highlights include:
+
+- DC offset correction (greatly reducing the spike seen in the center of an FFT
+  display)
+- Intermediate Frequency (IF) selection
+
+
+==============================
+HackRF 2013.06.1 Release Notes
+
+This is the first release of the HackRF project.
+
+This release package is simply a copy of the git repository with the addition
+of a binary firmware image (in the firmware-bin directory) that may be used
+to upgrade the firmware on a HackRF Jawbreaker.  For instructions, see:
+
+https://github.com/mossmann/hackrf/wiki/Updating-Firmware
+
+The git repository is located at:
+
+https://github.com/mossmann/hackrf

SoftwareDefined/HackRF/hackrf-2015.07.2/Readme.md

@@ -0,0 +1,10 @@
+This repository contains hardware designs and software for HackRF, a project to
+produce a low cost, open source software radio platform.
+
+![Jawbreaker](https://raw.github.com/mossmann/hackrf/master/doc/jawbreaker-fd0-145436.jpeg)
+
+(photo by fd0 from https://github.com/fd0/jawbreaker-pictures)
+
+principal author: Michael Ossmann <mike@ossmann.com>
+
+http://greatscottgadgets.com/hackrf/

SoftwareDefined/HackRF/hackrf-2015.07.2/TRADEMARK

@@ -0,0 +1,3 @@
+"HackRF" is a trademark of Michael Ossmann.  Permission to use the trademark
+with attribution to Michael Ossmann is granted to all licensees of HackRF for
+the purpose of naming or describing copies or derived works.  (See COPYING.)

SoftwareDefined/HackRF/hackrf-2015.07.2/doc/Readme.md

@@ -0,0 +1,7 @@
+The primary source of documentation is the wiki on github:
+
+https://github.com/mossmann/hackrf/wiki
+
+This directory contains supplemental documentation.
+
+(photo jawbreaker-fd0-145436.jpeg by fd0 from https://github.com/fd0/jawbreaker-pictures)

SoftwareDefined/HackRF/hackrf-2015.07.2/doc/SPIFI_Quad_Tests_OLS/SPIFI_QUAD_100MHZ_OLS_0_9_6b3_JellyBean_Startup_Dual4_M4_SPIFI_0_Analyze.txt

@@ -0,0 +1,127 @@
+
+OLS version used from: git://github.com/jawi/ols.git
+Warning sometimes there's a bug between Mode3 & Mode0 in OLS 0.9.6b3 
+Expected is when /CS = 0 at first SCK Rising Edge data shall be read.
+
+1) Read JDEC ID:
+----------------
+SPI Standard, Mode3, 8bits, MSB first, Show /CS & Honour /CS, SCK=About 32MHz:
+Send(MOSI)=0x9F(Read JDEC ID)
+Receive(MISO)=0xEF => Manufacturer ID(Winbond) and 0x40, 0x14 => Device ID
+
+2) Read Status Register-2:
+--------------------------
+SPI Standard, Mode3, 8bits, MSB first, Show /CS & Honour /CS, SCK=About 32MHz:
+Send(MOSI)=0x35(Read Status Register-2)
+Receive(MISO)=0x02 (Status Register-2 => S15-S8)
+
+3) Read Unknown Command 0xA3 (maybe for other SPIFI memory ??):
+---------------------------------------------------------------
+SPI Standard, Mode3, 8bits, MSB first, Show /CS & Honour /CS, SCK=About 32MHz:
+Send(MOSI)=0xA3
+Receive(MISO)=0x00 0x00 0x00
+
+4) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
+--------------------------------------------------------
+SPI Standard, Mode3, 8bits, MSB first, Show /CS & Honour /CS, SCK=About 32MHz:
+Send(MOSI)=0xEB(Fast Read Quad I/O)
+SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS:
+Send(IO0 to IO3) hexa:
+00 00 00 (A23-16) (A15-8) (A7-0)
+A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
+A5 A5 (Dummy 2 bytes)
+Receive(IO0 to IO3) hexa:
+00 00 02 10 B1 01 00 14 (Data) => Vect Table = 0x10020000(Stack Pointer), 0x140001B1(Thumb) Real Addr=0x140001B0 (Reset_Handler/ResetISR)
+79 01 00 14 7B 01 00 14 (Data)
+7D 01 00 14 7F 01 00 14 (Data)
+Dump from Debug (Big Endian to swap 32bits):
+0x80000000  00000210 B1010014 79010014 7B010014  ....<2E>...y...{...
+0x80000010  7D010014 7F010014                    }.......
+
+5) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
+--------------------------------------------------------
+SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS, SCK=About 32MHz:
+Send(IO0 to IO3) hexa:
+00 01 B0 (A23-16) (A15-8) (A7-0) (Corresponds to Real Addr=0x140001B0 (Reset_Handler/ResetISR))
+A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
+A5 A5 (Dummy 2 bytes)
+Receive(IO0 to IO3) hexa:
+10 B5 72 B6 19 4B 1A 4A (Data)
+1A 60 1A 4A 5A 60 1A 4A (Data)
+4F F0 FF 33 13 60 53 60 (Data)
+Dump from Debug (Big Endian to swap 32bits):
+0x800001B0  10B572B6 194B1A4A 1A601A4A 5A601A4A  .<2E>r<EFBFBD>.K.J.`.JZ`.J
+0x800001C0  4FF0FF33 13605360                    O<><4F>3.`S`
+
+6) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
+--------------------------------------------------------
+SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS:
+Send(IO0 to IO3) hexa:
+00 02 18 (A23-16) (A15-8) (A7-0)
+A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
+A5 A5 (Dummy 2 bytes)
+Receive(IO0 to IO3) hexa:
+FE E7 00 BF 00 31 05 40 (Data)
+00 00 DF 10 FF F7 DF 01 (Data)
+80 E2 00 E0 14 01 00 14 (Data)
+Dump from Debug (Big Endian to swap 32bits):
+0x80000218  FEE700BF 00310540 0000DF10 FFF7DF01  <20><>.<2E>.1.@..<2E>.<2E><><EFBFBD>.
+0x80000228  80E200E0 14010014                    .<2E>.<2E>....
+
+7) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
+--------------------------------------------------------
+SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS:
+Send(IO0 to IO3) hexa:
+00 01 C8 (A23-16) (A15-8) (A7-0)
+A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
+A5 A5 (Dummy 2 bytes)
+Receive(IO0 to IO3) hexa:
+93 60 D3 60 13 61 53 61 (Data)
+93 61 D3 61 62 B6 15 4C (Data)
+Dump from Debug (Big Endian to swap 32bits):
+0x800001C8  9360D360 13615361 9361D361 62B6154C  .`<60>`.aSa.a<>ab<61>.L
+
+8) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
+--------------------------------------------------------
+SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS:
+Send(IO0 to IO3) hexa:
+00 02 30 (A23-16) (A15-8) (A7-0)
+A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
+A5 A5 (Dummy 2 bytes)
+Receive(IO0 to IO3) hexa:
+50 01 00 14 78 01 00 14 (Data)
+Dump from Debug (Big Endian to swap 32bits):
+0x80000230  50010014 78010014                    P...x...
+
+9) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
+--------------------------------------------------------
+SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS:
+Send(IO0 to IO3) hexa:
+00 01 D8 (A23-16) (A15-8) (A7-0)
+A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
+A5 A5 (Dummy 2 bytes)
+Receive(IO0 to IO3) hexa:
+05 E0 20 68 61 68 A2 68 (Data)
+0C 34 FF F7 D2 FF 12 4B (Data
+9C 42 F6 D3 04 E0 20 68 (Data)
+61 68 08 34 FF F7 D2 FF (Data)
+0E 4B 9C 42 F7 D3 DF F8 (Data)
+Dump from Debug (Big Endian to swap 32bits):
+0x800001D8  05E02068 6168A268 0C34FFF7 D2FF124B  .<2E> hah<61>h.4<EFBFBD><EFBFBD><EFBFBD><EFBFBD>.K
+0x800001E8  9C42F6D3 04E02068 61680834 FFF7D2FF  .B<><42>.<2E> hah.4<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
+0x800001F8  0E4B9C42 F7D3DFF8                    .K.B<><42><EFBFBD><EFBFBD>
+
+Nota: 
+Tested on JellyBean.
+SCK is about 32MHz After about 620us from startup.
+SCK change to about 660KHz/700KHz during about 400us. (During Read from 00 0C 78 => During CGU SetPLL1 code).
+SCK change from 4MHz to about 8MHz during about 15us. (Read from 00 0D 98 => During CGU SetPLL1 code).
+SCK stabilize to 8MHz during 122us (no data anymore OLS memory is full) (Read from 00 05 B0).
+
+...
+During Code running the SCK run at 8MHz MCU is configured at 72MHz => 12MHz(IRC)*6.
+SPIFI CLK(0x40050070) = 0xD000800 0x0D=IDIVB & 0x800=AUTOBLOCK_CLOCK_BIT Enabled
+IDIVB_CTRL(0x4005004C) = 0x9000820 => IDIB=1000(8+1)=9 => for 72MHz Core => 72/9=8MHz
+IDIVB_CTRL(0x4005004C) = 0x9000800 => IDIB=0000(0+1)=1 => for 72MHz Core => 72/1=72MHz => This configuration just crash.
+IDIVB_CTRL(0x4005004C) = 0x9000800 => IDIB=0000(0+1)=1 => for 72MHz Core => 72/2=36MHz => This configuration works fine.
+

SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/README

@@ -0,0 +1,2 @@
+These files are generated from KiCad source.  They are provided for
+convenience but may not be as up to date as the KiCad source files.

SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/hackrf-one-bom.csv

@@ -0,0 +1,415 @@
+ref;value;Field1;Field2;Field3;Field4;Field5;Field6;Field7;Field8
+C1;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C2;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
+C3;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C4;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
+C5;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C6;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
+C7;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C8;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
+C9;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C10;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C11;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C12;330pF;Murata;GRM155R71H331KA01D;CAP CER 330PF 50V 10% X7R 0402;;;;;
+C13;330pF;Murata;GRM155R71H331KA01D;CAP CER 330PF 50V 10% X7R 0402;;;;;
+C14;8p2;Taiyo Yuden;UMK105CG8R2DV-F;CAP CER 8.2PF 50V NP0 0402;;;;;
+C15;180pF;Murata;GRM1555C1H181JA01D;CAP CER 180PF 50V 5% NP0 0402;;;;;
+C16;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C17;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C18;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C19;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C20;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C21;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
+C22;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C23;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C24;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C25;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C26;47pF;Murata;GRM1555C1H470JA01D;CAP CER 47PF 50V 5% NP0 0402;;;;;
+C27;47pF;Murata;GRM1555C1H470JA01D;CAP CER 47PF 50V 5% NP0 0402;;;;;
+C28;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C29;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C30;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C31;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C32;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
+C33;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C34;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C35;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C36;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C37;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C38;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C39;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C40;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C41;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;;;;;
+C42;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;;;;;
+C43;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
+C44;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C45;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C46;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C47;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C48;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
+C49;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C50;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C51;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
+C52;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;;;;;
+C53;1uF;Taiyo Yuden;LMK105BJ105KV-F;CAP CER 1UF 10V 10% X5R 0402;;;;;
+C54;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C55;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C56;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C57;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C58;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C59;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C60;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C61;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C62;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C63;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C64;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C65;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C66;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C67;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C68;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;DNP;;;;
+C69;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;DNP;;;;
+C70;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;;;;;
+C71;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C72;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402;;;;;
+C73;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C74;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402;;;;;
+C75;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C76;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402;;;;;
+C77;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C78;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402;;;;;
+C79;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C80;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402;;;;;
+C81;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C82;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402;;;;;
+C83;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C84;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
+C85;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
+C86;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
+C87;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
+C88;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
+C89;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
+C90;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;;;;;
+C91;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C92;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
+C93;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
+C94;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
+C95;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
+C96;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
+C97;330nF;Murata;GRM155R61A334KE15D;CAP CER 0.33UF 10V 10% X5R 0402;;;;;
+C98;330nF;Murata;GRM155R61A334KE15D;CAP CER 0.33UF 10V 10% X5R 0402;;;;;
+C99;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
+C100;330nF;Murata;GRM155R61A334KE15D;CAP CER 0.33UF 10V 10% X5R 0402;;;;;
+C101;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
+C102;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
+C103;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
+C104;3pF;Murata;GRM1555C1H3R0CA01D;CAP CER 3PF 50V NP0 0402;;;;;
+C105;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805;;;;;
+C106;1uF;Taiyo Yuden;LMK105BJ105KV-F;CAP CER 1UF 10V 10% X5R 0402;;;;;
+C107;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
+C108;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
+C109;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
+C110;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
+C111;3pF;Murata;GRM1555C1H3R0CA01D;CAP CER 3PF 50V NP0 0402;;;;;
+C112;180pF;Murata;GRM1555C1H181JA01D;CAP CER 180PF 50V 5% NP0 0402;;;;;
+C113;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C114;3.3nF;Murata;GRM155R71H332KA01D;CAP CER 3300PF 50V 10% X7R 0402;;;;;
+C115;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C116;47pF;Murata;GRM1555C1H470JA01D;CAP CER 47PF 50V 5% NP0 0402;;;;;
+C118;18pF;Murata;GRM1555C1H180JA01D;CAP CER 18PF 50V 5% NP0 0402;;;;;
+C119;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C120;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C121;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C122;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C123;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C124;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402;;;;;
+C125;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
+C126;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805;;;;;
+C127;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805;;;;;
+C128;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C129;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C130;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C131;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C132;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C133;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C134;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C135;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C136;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C137;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C138;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C139;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C140;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C141;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C142;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C143;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805;;;;;
+C144;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C145;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805;;;;;
+C146;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805;;;;;
+C147;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C148;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C149;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C150;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C151;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C152;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C153;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C154;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C155;DNP;DNP;;;;;;;
+C156;47pF;Murata;GRM1555C1H470JA01D;CAP CER 47PF 50V 5% NP0 0402;DNP;;;;
+C157;18pF;Murata;GRM1555C1H180JA01D;CAP CER 18PF 50V 5% NP0 0402;;;;;
+C158;18pF;Murata;GRM1555C1H180JA01D;CAP CER 18PF 50V 5% NP0 0402;;;;;
+C159;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;DNP;;;;
+C160;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;;;;;
+C161;1uF;Taiyo Yuden;LMK105BJ105KV-F;CAP CER 1UF 10V 10% X5R 0402;;;;;
+C162;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
+C163;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
+C164;18pF;Murata;GRM1555C1H180JA01D;CAP CER 18PF 50V 5% NP0 0402;;;;;
+C165;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;DNP;;;;
+C166;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C167;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
+C168;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;DNP;;;;
+C169;DNP;DNP;;;;;;;
+C170;DNP;DNP;;;;;;;
+C171;1uF;Taiyo Yuden;LMK105BJ105KV-F;CAP CER 1UF 10V 10% X5R 0402;;;;;
+D1;GSG-DIODE-TVS-BI;Murata;LXES15AAA1-100;TVS DIODE ESD .05PF 15KV 0402;;;;;
+D2;VAALED;Lite-On;LTST-S220KRKT;LED SUPR RED CLR RT ANG 0805;;;;;
+D3;GSG-DIODE-TVS-BI;Murata;LXES15AAA1-100;TVS DIODE ESD .05PF 15KV 0402;;;;;
+D4;USBLED;Lite-On;LTST-S220KGKT;LED GREEN CLEAR RT ANG 0805;;;;;
+D5;RXLED;Lite-On;LTST-S220KSKT;LED YELLOW CLEAR RT ANG 0805;;;;;
+D6;TXLED;Lite-On;LTST-S220KRKT;LED SUPR RED CLR RT ANG 0805;;;;;
+D7;VCCLED;Lite-On;LTST-S220KGKT;LED GREEN CLEAR RT ANG 0805;;;;;
+D8;1V8LED;Lite-On;LTST-S220KSKT;LED YELLOW CLEAR RT ANG 0805;;;;;
+D9;GSG-DIODE-TVS-BI;Murata;LXES15AAA1-100;TVS DIODE ESD .05PF 15KV 0402;;;;;
+FB1;FILTER;Murata;BLM21PG221SN1D;FERRITE CHIP 220 OHM 2000MA 0805;;;;;
+FB2;FILTER;Murata;BLM21PG221SN1D;FERRITE CHIP 220 OHM 2000MA 0805;;;;;
+FB3;FILTER;Murata;BLM21PG221SN1D;FERRITE CHIP 220 OHM 2000MA 0805;;;;;
+J1;USB-MICRO-B;FCI;10103592-0001LF;CONN RCPT REV MICRO USB TYPE B;;;;;
+J2;RF-SHIELD-FRAME;Laird;BMI-S-230-F-R;BOARD SHIELD 2INX1.5IN FRAME;DNP;;;;
+J3;RF-SHIELD-COVER;Laird;BMI-S-230-C;BOARD SHIELD 2INX1.5IN COVER;DNP;;;;
+J4;MOUNTING_HOLE;DNP;;;;;;;
+J5;MOUNTING_HOLE;DNP;;;;;;;
+J6;MOUNTING_HOLE;DNP;;;;;;;
+J7;MOUNTING_HOLE;DNP;;;;;;;
+J8;MOUNTING_HOLE;DNP;;;;;;;
+J9;MOUNTING_HOLE;DNP;;;;;;;
+J10;GND_CLIP;Harwin;S1751-46R;PC TEST POINT TIN SMD;DNP;;;;
+L1;DNP;DNP;;;;;;;
+L2;10uH;Taiyo Yuden;BRL1608T100M;INDUCTR 10UH 220MA 20% 0603 SMD;;;;;
+L3;10uH;Taiyo Yuden;BRL1608T100M;INDUCTR 10UH 220MA 20% 0603 SMD;;;;;
+L4;DNP;DNP;;;;;;;
+L5;10uH;Taiyo Yuden;BRL1608T100M;INDUCTR 10UH 220MA 20% 0603 SMD;;;;;
+L6;DNP;DNP;;;;;;;
+L7;6.2nH;Taiyo Yuden;HK10056N2S-T;INDUCTOR HIFREQ 6.2+/-0.3NH 0402;;;;;
+L8;DNP;DNP;;;;;;;
+L9;DNP;DNP;;;;;;;
+L10;4u7;Taiyo Yuden;NRG4026T4R7M;INDUCTOR 4.7UH 1.6A 20% SMD;;;;;
+L11;4u7;Taiyo Yuden;NRG4026T4R7M;INDUCTOR 4.7UH 1.6A 20% SMD;;;;;
+L12;10uH;Taiyo Yuden;BRL1608T100M;INDUCTR 10UH 220MA 20% 0603 SMD;;;;;
+L13;10uH;Taiyo Yuden;BRL1608T100M;INDUCTR 10UH 220MA 20% 0603 SMD;;;;;
+P1;1V8;DNP;;;;;;;
+P2;CLKOUT;Molex;73251-2121;CONN SMA JACK 50 OHM EDGE MNT W/JAM NUT & LOCK WASHER;;;;;
+P3;GND;DNP;;;;;;;
+P4;ANTENNA;Molex;73251-2121;CONN SMA JACK 50 OHM EDGE MNT W/JAM NUT & LOCK WASHER;;;;;
+P5;LEDS;DNP;;;;;;;
+P6;GPO4;DNP;;;;;;;
+P7;GPO2;DNP;;;;;;;
+P8;VCC;DNP;;;;;;;
+P9;BASEBAND;Sullins;PPPC082LFBN-RC;CONN HEADER FMAL 16PS.1" DL GOLD;;;;;
+P13;GPO1;DNP;;;;;;;
+P14;XCVR_CLKOUT;DNP;;;;;;;
+P15;INTR;DNP;;;;;;;
+P16;CLKIN;Molex;73251-2121;CONN SMA JACK 50 OHM EDGE MNT W/JAM NUT & LOCK WASHER;;;;;
+P17;GPO6;DNP;;;;;;;
+P18;OEB;DNP;;;;;;;
+P19;GPO3;DNP;;;;;;;
+P20;GPIO;Sullins;PPPC112LFBN-RC;CONN HEADER FMAL 22PS.1" DL GOLD;;;;;
+P21;REF_IN;DNP;;;;;;;
+P22;I2S;Sullins;PPPC132LFBN-RC;CONN HEADER FMAL 26PS.1" DL GOLD;;;;;
+P23;DBGEN;DNP;;;;;;;
+P24;TRST;DNP;;;;;;;
+P25;LPC_ISP;DNP;;;;;;;
+P26;LPC_JTAG;Sullins;GRPB052VWVN-RC;CONN HEADER .050" 10PS DL PCB AU;DNP;;;;
+P27;MIXER_SDATA;DNP;;;;;;;
+P28;SD;Sullins;PPPC112LFBN-RC;CONN HEADER FMAL 22PS.1" DL GOLD;;;;;
+P29;CPLD_JTAG;DNP;;;;;;;
+P30;BANK2_AUX;DNP;;;;;;;
+P31;MIXER_SCLK;DNP;;;;;;;
+P32;MIXER_ENX;DNP;;;;;;;
+P33;MIXER_RESETX;DNP;;;;;;;
+P34;MIX_BYPASS;DNP;;;;;;;
+P35;!MIX_BYPASS;DNP;;;;;;;
+P36;VAA;DNP;;;;;;;
+P37;SCL;DNP;;;;;;;
+P38;SDA;DNP;;;;;;;
+P39;SSP1_SCK;DNP;;;;;;;
+P40;SSP1_MOSI;DNP;;;;;;;
+P41;SSP1_MISO;DNP;;;;;;;
+P42;TX;DNP;;;;;;;
+P43;RX;DNP;;;;;;;
+P44;HP;DNP;;;;;;;
+P45;LP;DNP;;;;;;;
+P46;TX_MIX_BP;DNP;;;;;;;
+P47;RX_MIX_BP;DNP;;;;;;;
+P48;TX_AMP;DNP;;;;;;;
+P49;RX_AMP;DNP;;;;;;;
+P50;AMP_BYPASS;DNP;;;;;;;
+P51;!TX_AMP_PWR;DNP;;;;;;;
+P52;!RX_AMP_PWR;DNP;;;;;;;
+P53;CS_XCVR;DNP;;;;;;;
+P54;CS_AD;DNP;;;;;;;
+P55;TXENABLE;DNP;;;;;;;
+P56;RXENABLE;DNP;;;;;;;
+P57;XTAL2;DNP;;;;;;;
+P58;GCK1;DNP;;;;;;;
+P59;GCK2;DNP;;;;;;;
+P60;SGPIO_CLK;DNP;;;;;;;
+P61;DA0;DNP;;;;;;;
+P62;DA7;DNP;;;;;;;
+P63;DD0;DNP;;;;;;;
+P64;DD9;DNP;;;;;;;
+P65;DA4;DNP;;;;;;;
+P66;DD5;DNP;;;;;;;
+P67;RSSI;DNP;;;;;;;
+P68;SPIFI_CS;DNP;;;;;;;
+P69;VREGMODE;DNP;;;;;;;
+P70;EN_1V8;DNP;;;;;;;
+P71;ID;DNP;;;;;;;
+P72;GP_CLKIN;DNP;;;;;;;
+P73;P1_2;DNP;;;;;;;
+P74;P1_1;DNP;;;;;;;
+P75;GP_CLKIN;DNP;;;;;;;
+P76;GP_CLKIN;DNP;;;;;;;
+P77;GP_CLKIN;DNP;;;;;;;
+P78;GP_CLKIN;DNP;;;;;;;
+P79;GP_CLKIN;DNP;;;;;;;
+P80;SHIELD;DNP;;;;;;;
+P81;SPIFI_SIO2;DNP;;;;;;;
+P82;SPIFI_SIO3;DNP;;;;;;;
+P83;GND;DNP;;;;;;;
+P84;GND;DNP;;;;;;;
+P85;GND;DNP;;;;;;;
+P86;GND;DNP;;;;;;;
+P87;GND;DNP;;;;;;;
+P88;GND;DNP;;;;;;;
+P89;GND;DNP;;;;;;;
+P90;GND;DNP;;;;;;;
+P91;GND;DNP;;;;;;;
+P92;GND;DNP;;;;;;;
+Q1;MOSFET_P;Fairchild;BSS84;MOSFET P-CH 50V 130MA SOT-23;;;;;
+Q2;MOSFET_P;Fairchild;BSS84;MOSFET P-CH 50V 130MA SOT-23;;;;;
+Q3;MOSFET_P;Diodes Inc.;DMP2305U-7;MOSFET P-CH 20V 4.2A SOT-23;;;;;
+Q4;MOSFET_P;Fairchild;BSS84;MOSFET P-CH 50V 130MA SOT-23;;;;;
+Q5;MOSFET_P;Alpha and Omega;AO3407A;MOSFET P-CH -30V -4.3A SOT23;;;;;
+R1;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402;;;;;
+R2;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402;;;;;
+R3;22k;Panasonic;ERJ-2GEJ223X;RES 22K OHM 1/10W 5% 0402 SMD;;;;;
+R4;51k;Stackpole;RMCF0402FT51K0;RES TF 51K OHM 1% 0.0625W 0402;;;;;
+R5;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R6;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R7;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R8;1k;Stackpole;RMCF0402FT1K00;RES 1K OHM 1/16W 1% 0402;;;;;
+R9;1k;Stackpole;RMCF0402FT1K00;RES 1K OHM 1/16W 1% 0402;;;;;
+R10;1k;Stackpole;RMCF0402FT1K00;RES 1K OHM 1/16W 1% 0402;;;;;
+R11;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R12;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R13;1k;Stackpole;RMCF0402FT1K00;RES 1K OHM 1/16W 1% 0402;;;;;
+R14;4k7;Stackpole;RMCF0402FT4K70;RES 4.7K OHM 1/16W 1% 0402;;;;;
+R15;4k7;Stackpole;RMCF0402FT4K70;RES 4.7K OHM 1/16W 1% 0402;;;;;
+R16;4k7;Stackpole;RMCF0402FT4K70;RES 4.7K OHM 1/16W 1% 0402;;;;;
+R17;4k7;Stackpole;RMCF0402FT4K70;RES 4.7K OHM 1/16W 1% 0402;;;;;
+R18;1k8;Stackpole;RMCF0402JT1K80;RES TF 1.8K OHM 5% 1/16W 0402;;;;;
+R19;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R20;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD;;;;;
+R21;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD;;;;;
+R22;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD;;;;;
+R23;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD;;;;;
+R24;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R25;475;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402;;;;;
+R26;475;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402;;;;;
+R27;1k8;Stackpole;RMCF0402JT1K80;RES TF 1.8K OHM 5% 1/16W 0402;;;;;
+R28;1k8;Stackpole;RMCF0402JT1K80;RES TF 1.8K OHM 5% 1/16W 0402;;;;;
+R29;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R30;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R31;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R32;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R33;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R34;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R35;DNP;DNP;;;;;;;
+R36;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R37;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R41;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R46;162k;Stackpole;RMCF0402FT162K;RES TF 1/16W 162K OHM 1% 0402;;;;;
+R47;330k;Stackpole;RMCF0402FT330K;RES TF 1/16W 330K OHM 1% 0402;;;;;
+R48;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R49;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R51;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R52;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R54;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R55;162k;Stackpole;RMCF0402FT162K;RES TF 1/16W 162K OHM 1% 0402;;;;;
+R56;715k;Stackpole;RMCF0402FT715K;RES TF 1/16W 715K OHM 1% 0402;;;;;
+R57;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD;;;;;
+R58;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD;;;;;
+R59;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R62;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD;;;;;
+R63;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R64;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R65;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R66;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R67;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R68;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R69;12k;Rohm;MCR01MRTF1202;RES 12.0K OHM 1/16W 1% 0402 SMD;;;;;
+R72;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402;;;;;
+R73;1k;Stackpole;RMCF0402FT1K00;RES 1K OHM 1/16W 1% 0402;;;;;
+R74;1k8;Stackpole;RMCF0402JT1K80;RES TF 1.8K OHM 5% 1/16W 0402;;;;;
+R75;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402;;;;;
+R76;1k;Stackpole;RMCF0402FT1K00;RES 1K OHM 1/16W 1% 0402;;;;;
+R77;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R78;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R79;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R80;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R81;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R85;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R86;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R87;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R88;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R89;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R90;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R91;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R93;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R94;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R96;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R98;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R99;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R100;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
+R104;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+R105;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
+SW1;DFU;TE Connectivity;FSMRA3JH;SWITCH TACTILE SPST-NO 0.05A 12V;;;;;
+SW2;RESET;TE Connectivity;FSMRA3JH;SWITCH TACTILE SPST-NO 0.05A 12V;;;;;
+T1;MIX_IN_BALUN;Anaren;B0310J50100AHF;Ultra Low Profile 0805 Balun 50 to 100 ohm Balanced;;;;;
+T2;MIX_OUT_BALUN;Anaren;B0310J50100AHF;Ultra Low Profile 0805 Balun 50 to 100 ohm Balanced;;;;;
+T3;RX_BALUN;Johanson Technology;2500BL14M100T;BALUN CERAMIC CHIP WIMAX 2.5GHZ;;;;;
+T4;TX_BALUN;Johanson Technology;2500BL14M100T;BALUN CERAMIC CHIP WIMAX 2.5GHZ;;;;;
+U1;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch;;;;;
+U2;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch;;;;;
+U3;RX_LOWPASS_FILTER;AVX;LP0603A1880ANTR;FILTER LOW PASS 1880MHZ 0603 SMD;;;;;
+U4;RFFC5072;RFMD;RFFC5072TR7;WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6GHz MIXER;;;;;
+U5;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch;;;;;
+U6;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch;;;;;
+U7;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch;;;;;
+U8;RX_HIGHPASS_FILTER;TDK;DEA162400HT-8004B1;FILTER HIGHPASS WLAN&BLUETOOTH;;;;;
+U9;SKY13317;Skyworks;SKY13317-373LF;20 MHz-6.0 GHz pHEMT GaAs SP3T Switch;;;;;
+U10;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch;;;;;
+U11;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch;;;;;
+U12;SKY13317;Skyworks;SKY13317-373LF;20 MHz-6.0 GHz pHEMT GaAs SP3T Switch;;;;;
+U13;MGA-81563;Avago;MGA-81563-TR1G;0.1-6 GHz 3 V, 14 dBm Amplifier;;;;;
+U14;SKY13317;Skyworks;SKY13317-373LF;20 MHz-6.0 GHz pHEMT GaAs SP3T Switch;;;;;
+U15;LXES1TBCC2-004;Murata;LXES1TBCC2-004;ESD Suppressors 0.55pF 6V 2ch;;;;;
+U17;MAX2837;Maxim;MAX2837ETM+;IC TXRX 2.3GHZ-2.7GHZ 48TQFN;;;;;
+U18;MAX5864;Maxim;MAX5864ETM+;IC ANLG FRONT END 22MSPS 48-TQFN;;;;;
+U19;SI5351C;Silicon Laboratories Inc;SI5351C-B-GM;IC CLK GENERATOR 160MHZ 20QFN;;;;;
+U20;W25Q80BV;Winbond;W25Q80BVSSIG;IC FLASH 8MBIT 8SOIC;;;;;
+U21;TPS62410;Texas Instruments;TPS62410DRCR;IC BUCK SYNC DUAL ADJ 0.8A 10SON;;;;;
+U23;LPC4320FBD144;NXP;LPC4320FBD144,551;IC MCU 32BIT 144LQFP;;;;;
+U24;GSG-XC2C64A-7VQG100C;Xilinx;XC2C64A-7VQG100C;IC CR-II CPLD 64MCELL 100-VQFP;;;;;
+U25;MGA-81563;Avago;MGA-81563-TR1G;0.1-6 GHz 3 V, 14 dBm Amplifier;;;;;
+X1;GSG-XTAL4PIN;AVX;CX3225GB25000D0HEQZ1;CRYSTAL 25.000MHZ 8PF SMD;;;;;
+X2;MCU_XTAL;TXC;7V-12.000MAAE-T;CRYSTAL 12.000 MHZ 12PF SMD;;;;;
+X3;RTC_XTAL;Abracon;AB26TRQ-32.768KHZ-T;CRYSTAL 32.768KHZ 12.5PF SMD;;;;;

SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/hackrf-one-gerbers/README

@@ -0,0 +1,47 @@
+Copyright 2012, 2013, 2014 Michael Ossmann
+
+These files are part of HackRF.
+
+This is a free hardware design; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This design is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this design; see the file COPYING.  If not, write to
+the Free Software Foundation, Inc., 51 Franklin Street,
+Boston, MA 02110-1301, USA.
+
+
+HackRF One is a wideband software radio transceiver with a USB interface.
+
+hardware notes:
+
+Schematic and layout files were designed in KiCad, an open source electronic
+design automation package.
+
+order of copper layers:
+    Copper 1:  C1F (front)
+    Copper 2:  C2
+    Copper 3:  C3
+    Copper 4:  C1B (back)
+
+PCB description: 4 layer PCB 0.062 in
+    Copper        1   0.5 oz foil plated to approximately 0.0017 in
+    Dielectric  1-2   0.0119 in
+    Copper        2   1 oz foil (0.0014 in)
+    Dielectric  2-3   0.0280 in
+    Copper        3   1 oz foil (0.0014 in)
+    Dielectric  3-4   0.0119 in
+    Copper        4   0.5 oz foil plated to approximately 0.0017 in
+
+FR4 or similar substrate with Er=4.5 (+/- 0.1)
+double side solder mask green
+single side silkscreen white
+6 mil min trace width and
+6 mil min isolation

SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/hackrf-one-gerbers/hackrf-one-B_Mask.gbs

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SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/hackrf-one-gerbers/hackrf-one-Edge_Cuts.gbr

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SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/hackrf-one-gerbers/hackrf-one.drl

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SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/jawbreaker-bom.csv

@@ -0,0 +1,368 @@
+ref;value;Field1;Field2;Field3;Field4;Field5;Field6;Field7;Field8
+C1;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C2;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C3;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C4;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C5;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C6;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C7;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C8;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
+C9;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
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+C11;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
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+C13;330pF;Murata;GRM155R71H331KA01D;CAP CER 330PF 50V 10% X7R 0402
+C14;8p2;Taiyo Yuden;UMK105CG8R2DV-F;CAP CER 8.2PF 50V NP0 0402
+C15;180pF;Murata;GRM1555C1H181JA01D;CAP CER 180PF 50V 5% NP0 0402
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+C33;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C34;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C35;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C36;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C37;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C38;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C39;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C40;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C41;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
+C42;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
+C43;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
+C44;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C45;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C46;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C47;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C48;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
+C49;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C50;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
+C51;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
+C52;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
+C53;1uF;Taiyo Yuden;LMK105BJ105KV-F;CAP CER 1UF 10V 10% X5R 0402
+C54;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C55;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C56;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C57;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C58;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
+C59;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
+C60;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C61;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C62;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
+C63;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C64;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C65;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C66;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C67;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
+C68;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C69;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C70;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
+C71;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C72;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402
+C73;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C74;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402
+C75;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C76;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402
+C77;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C78;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402
+C79;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C80;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402
+C81;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C82;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402
+C83;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C84;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402
+C85;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402
+C86;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402
+C87;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C88;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C89;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C90;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
+C91;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C92;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C93;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C94;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402
+C95;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
+C96;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
+C97;330nF;Murata;GRM155R61A334KE15D;CAP CER 0.33UF 10V 10% X5R 0402
+C98;330nF;Murata;GRM155R61A334KE15D;CAP CER 0.33UF 10V 10% X5R 0402
+C99;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402
+C100;330nF;Murata;GRM155R61A334KE15D;CAP CER 0.33UF 10V 10% X5R 0402
+C101;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
+C102;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402
+C103;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
+C104;3pF;Murata;GRM1555C1H3R0CA01D;CAP CER 3PF 50V NP0 0402
+C105;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805
+C106;1uF;Taiyo Yuden;LMK105BJ105KV-F;CAP CER 1UF 10V 10% X5R 0402
+C107;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
+C108;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
+C109;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
+C110;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
+C111;3pF;Murata;GRM1555C1H3R0CA01D;CAP CER 3PF 50V NP0 0402
+C112;180pF;Murata;GRM1555C1H181JA01D;CAP CER 180PF 50V 5% NP0 0402
+C113;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C114;3.3nF;Murata;GRM155R71H332KA01D;CAP CER 3300PF 50V 10% X7R 0402
+C115;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C116;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
+C117;DNP;DNP
+C118;DNP;DNP
+C119;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C120;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C121;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C122;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C123;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C124;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402
+C125;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
+C126;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805
+C127;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805
+C128;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C129;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C130;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C131;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C132;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C133;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C134;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C135;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C136;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C137;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C138;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C139;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C140;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C141;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C142;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C143;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805
+C144;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C145;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805
+C146;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805
+C147;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C148;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C149;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C150;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C151;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C152;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C153;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C154;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
+C155;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
+C156;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
+C157;18pF;Murata;GRM1555C1H180JZ01D;CAP CER 18PF 50V 5% NP0 0402
+C158;18pF;Murata;GRM1555C1H180JZ01D;CAP CER 18PF 50V 5% NP0 0402
+C159;1uF;Murata;GRM155R61A105ME15D;CAP CER 1UF 10V 20% X5R 0402;DNP
+C160;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
+C161;1uF;Taiyo Yuden;LMK105BJ105KV-F;CAP CER 1UF 10V 10% X5R 0402
+C162;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C163;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
+C164;DNP;DNP
+C165;DNP;DNP
+D1;GSG-DIODE-TVS-BI;Murata;LXES15AAA1-100;TVS DIODE ESD .05PF 15KV 0402
+D2;USBLED1;Everlight;QTLP601C4TR;LED GREEN STD BRIGHT 0603 SMD
+D3;USBLED0;Everlight;QTLP600CYTR;LED YLW SUPER BRIGHT 0606 SMD
+D4;LED1;Everlight;QTLP601C4TR;LED GREEN STD BRIGHT 0603 SMD
+D5;LED2;Everlight;QTLP600CYTR;LED YLW SUPER BRIGHT 0606 SMD
+D6;LED3;Everlight;QTLP601CRTR;LED RED STD BRIGHT 0603 SMD
+D7;VCCLED;Everlight;QTLP601C4TR;LED GREEN STD BRIGHT 0603 SMD
+D8;1V8LED;Everlight;QTLP600CYTR;LED YLW SUPER BRIGHT 0606 SMD
+FB1;FILTER;Murata;BLM21PG221SN1D;FERRITE CHIP 220 OHM 2000MA 0805
+FB2;FILTER;Murata;BLM21PG221SN1D;FERRITE CHIP 220 OHM 2000MA 0805
+J1;GSG-USB-MICRO-B;FCI;10103594-0001LF;CONN RCPT STD MICRO USB TYPE B
+J2;900MHZ-F-ANTENNA;DNP
+L1;DNP;DNP
+L2;1uH;Taiyo Yuden;BRL1608T1R0M;INDUCTR 1.0UH 650MA 20% 0603 SMD
+L3;1uH;Taiyo Yuden;BRL1608T1R0M;INDUCTR 1.0UH 650MA 20% 0603 SMD
+L4;DNP;DNP
+L5;1uH;Taiyo Yuden;BRL1608T1R0M;INDUCTR 1.0UH 650MA 20% 0603 SMD
+L6;DNP;DNP
+L7;6.2nH;Taiyo Yuden;HK10056N2S-T;INDUCTOR HIFREQ 6.2+/-0.3NH 0402
+L8;DNP;DNP
+L9;DNP;DNP
+L10;4u7;Taiyo Yuden;NRG4026T4R7M;INDUCTOR 4.7UH 1.6A 20% SMD
+L11;4u7;Taiyo Yuden;NRG4026T4R7M;INDUCTOR 4.7UH 1.6A 20% SMD
+L12;1uH;Taiyo Yuden;BRL1608T1R0M;INDUCTR 1.0UH 650MA 20% 0603 SMD
+L13;INDUCTOR;DNP
+L14;INDUCTOR;DNP
+P1;1V8;DNP
+P2;CLKOUT;TE Connectivity;2081233-1;CONN JACK SMA PCB VERT;DNP
+P3;GND;DNP
+P4;ANTENNA;TE Connectivity;2081233-1;CONN JACK SMA PCB VERT
+P5;WAKEUP;DNP
+P6;TRACECLK;DNP
+P7;CTIN_4;DNP
+P8;VCC;DNP
+P9;CTOUT_4;DNP
+P10;CTOUT_2;DNP
+P11;CTIN_2;DNP
+P12;U3_RXD;DNP
+P13;U3_TXD;DNP
+P14;XCVR_CLKOUT;DNP
+P15;INTR;DNP
+P16;CLKIN;TE Connectivity;2081233-1;CONN JACK SMA PCB VERT;DNP
+P17;CLKIN_JMP;DNP
+P18;OEB;DNP
+P19;SPIFI;DNP
+P20;GPIO;DNP
+P21;ANALOG;DNP
+P22;I2S;DNP
+P23;DBGEN;DNP
+P24;TRST;DNP
+P25;LPC_ISP;DNP
+P26;LPC_JTAG;DNP
+P27;CONN_3;DNP
+P28;SD;DNP
+P29;CPLD_JTAG;DNP
+P30;BANK2_AUX;DNP
+P31;BANK1_AUX;DNP
+P32;CONN_3;DNP
+P33;CONN_3;DNP
+P34;CONN_3;DNP
+P35;GCK0;DNP
+P36;VAA;DNP
+P37;SCL;DNP
+P38;SDA;DNP
+P39;SSP1_SCK;DNP
+P40;SSP1_MOSI;DNP
+P41;SSP1_MISO;DNP
+Q1;MOSFET_P;Fairchild;BSS84;MOSFET P-CH 50V 130MA SOT-23
+Q2;MOSFET_P;Fairchild;BSS84;MOSFET P-CH 50V 130MA SOT-23
+R1;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
+R2;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
+R3;22k;Panasonic;ERJ-2GEJ223X;RES 22K OHM 1/10W 5% 0402 SMD
+R4;51k;Stackpole;RMCF0402FT51K0;RES TF 51K OHM 1% 0.0625W 0402
+R5;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
+R6;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
+R7;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
+R8;1k;Stackpole;RMCF0402JT1K00;RES 1K OHM 1/16W 5% 0402 SMD
+R9;1k;Stackpole;RMCF0402JT1K00;RES 1K OHM 1/16W 5% 0402 SMD
+R10;1k;Stackpole;RMCF0402JT1K00;RES 1K OHM 1/16W 5% 0402 SMD
+R11;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R12;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R13;1k;Stackpole;RMCF0402JT1K00;RES 1K OHM 1/16W 5% 0402 SMD
+R14;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
+R15;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
+R16;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
+R17;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
+R18;47;DNP
+R19;47;DNP
+R20;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD
+R21;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD
+R22;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD
+R23;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD
+R24;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
+R25;475;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
+R26;475;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
+R27;1k8;Stackpole;RMCF0402JT1K80;RES TF 1.8K OHM 5% 1/16W 0402
+R28;1k8;Stackpole;RMCF0402JT1K80;RES TF 1.8K OHM 5% 1/16W 0402
+R29;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
+R30;0;DNP
+R31;0;DNP
+R32;0;DNP
+R33;0;DNP
+R34;0;DNP
+R35;0;DNP
+R36;0;DNP
+R37;0;DNP
+R38;0;DNP
+R39;0;DNP
+R40;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;DNP
+R41;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
+R42;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;DNP
+R43;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;DNP
+R44;0;DNP
+R45;DNP;DNP
+R46;162k;Stackpole;RMCF0402FT162K;RES TF 1/16W 162K OHM 1% 0402
+R47;330k;Stackpole;RMCF0402FT330K;RES TF 1/16W 330K OHM 1% 0402
+R48;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
+R49;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
+R50;DNP;DNP
+R51;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
+R52;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
+R53;DNP;DNP
+R54;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
+R55;162k;Stackpole;RMCF0402FT162K;RES TF 1/16W 162K OHM 1% 0402
+R56;715k;Stackpole;RMCF0402FT715K;RES TF 1/16W 715K OHM 1% 0402
+R57;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD
+R58;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD
+R59;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
+R60;0;DNP
+R61;0;DNP
+R62;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD
+R63;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
+R64;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
+R65;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;DNP
+R66;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
+R67;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
+R68;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
+R69;12k;Rohm;MCR01MRTF1202;RES 12.0K OHM 1/16W 1% 0402 SMD
+R70;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
+R71;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
+R72;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
+R73;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
+R74;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
+R75;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
+R76;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
+R77;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R78;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R79;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R80;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R81;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R82;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;DNP
+R83;0;DNP
+R84;50;DNP
+R85;DNP;DNP
+R86;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R87;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R88;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R89;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R90;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R91;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R92;50;DNP
+R93;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
+R94;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R96;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R97;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;DNP
+R98;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R99;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R100;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
+R104;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
+R105;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
+T1;MIX_IN_BALUN;Anaren;B0310J50100AHF;Ultra Low Profile 0805 Balun 50 to 100 ohm Balanced
+T2;MIX_OUT_BALUN;Anaren;B0310J50100AHF;Ultra Low Profile 0805 Balun 50 to 100 ohm Balanced
+T3;RX_BALUN;Johanson Technology;2500BL14M100T;BALUN CERAMIC CHIP WIMAX 2.5GHZ
+T4;TX_BALUN;Johanson Technology;2500BL14M100T;BALUN CERAMIC CHIP WIMAX 2.5GHZ
+U1;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch
+U2;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch
+U3;RX_LOWPASS_FILTER;AVX;LP0603A1880ANTR;FILTER LOW PASS 1880MHZ 0603 SMD
+U4;RFFC5072;RFMD;RFFC5072TR7;WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6GHz MIXER
+U5;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch
+U6;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch
+U7;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch
+U8;RX_HIGHPASS_FILTER;TDK;DEA162400HT-8004B1;FILTER HIGHPASS WLAN&BLUETOOTH
+U9;SKY13317;Skyworks;SKY13317-373LF;20 MHz-6.0 GHz pHEMT GaAs SP3T Switch
+U10;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch
+U11;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch
+U12;SKY13317;Skyworks;SKY13317-373LF;20 MHz-6.0 GHz pHEMT GaAs SP3T Switch
+U13;MGA-81563;Avago;MGA-81563-TR1G;0.1-6 GHz 3 V, 14 dBm Amplifier
+U14;SKY13317;Skyworks;SKY13317-373LF;20 MHz-6.0 GHz pHEMT GaAs SP3T Switch
+U15;GSG-74HC04;Texas Instruments;SN74AHC04RGYR;IC HEX INVERTERS 14-QFN
+U16;GSG-74HC08;Texas Instruments;SN74AHC08RGYR;IC QUAD 2IN POS-AND GATE 14-QFN
+U17;MAX2837;Maxim;MAX2837ETM+;IC TXRX 2.3GHZ-2.7GHZ 48TQFN
+U18;MAX5864;Maxim;MAX5864ETM+;IC ANLG FRONT END 22MSPS 48-TQFN
+U19;SI5351C;Silicon Laboratories Inc;SI5351C-B-GM;IC CLK GENERATOR 160MHZ 20QFN
+U20;W25Q80BV;Winbond;W25Q80BVSSIG;IC FLASH 8MBIT 8SOIC
+U21;TPS62410;Texas Instruments;TPS62410DRCR;IC BUCK SYNC DUAL ADJ 0.8A 10SON
+U22;GSG-IP4220CZ6;NXP;IP4220CZ6,125;IC USB DUAL ESD PROTECT 6TSOP
+U23;LPC43XXFBD144;NXP;LPC4330FBD144,551;IC MCU 32BIT 144LQFP
+U24;GSG-XC2C64A-7VQG100C;Xilinx;XC2C64A-7VQG100C;IC CR-II CPLD 64MCELL 100-VQFP
+U25;MGA-81563;Avago;MGA-81563-TR1G;0.1-6 GHz 3 V, 14 dBm Amplifier
+U26;RF LDO;DNP
+X1;GSG-XTAL4PIN;AVX;CX3225GB25000D0HEQZ1;CRYSTAL 25.000MHZ 8PF SMD
+X2;MCU_XTAL;TXC;7V-12.000MAAE-T;CRYSTAL 12.000 MHZ 12PF SMD

SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/jawbreaker-gerbers/README

@@ -0,0 +1,19 @@
+order of copper layers:
+    Copper 1: Front
+    Copper 2: Inner3
+    Copper 3: Inner2
+    Copper 4: Back
+
+PCB description: 4 layer PCB 0.062 in
+    Copper        1   0.5 oz foil plated to approximately 0.0017 in
+    Dielectric  1-2   0.0119 in
+    Copper        2   1 oz foil (0.0014 in)
+    Dielectric  2-3   0.0280 in
+    Copper        3   1 oz foil (0.0014 in)
+    Dielectric  3-4   0.0119 in
+    Copper        4   0.5 oz foil plated to approximately 0.0017 in
+FR4 or similar substrate with Er=4.5 (+/- 0.1)
+double side solder mask black
+single side silkscreen white
+6 mil min trace width and
+6 mil min isolation

SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/jawbreaker-gerbers/jawbreaker-B_Mask.gbs

@@ -0,0 +1,257 @@
+G04 (created by PCBNEW (2013-01-23 BZR 3920)-stable) date Mon Jun 10 00:49:26 2013*
+%MOIN*%
+G04 Gerber Fmt 3.4, Leading zero omitted, Abs format*
+%FSLAX34Y34*%
+G01*
+G70*
+G90*
+G04 APERTURE LIST*
+%ADD10C,2.3622e-06*%
+%ADD11C,0.075*%
+%ADD12C,0.0691*%
+%ADD13C,0.0292*%
+%ADD14C,0.029*%
+%ADD15R,0.072X0.072*%
+%ADD16C,0.072*%
+%ADD17C,0.112*%
+%ADD18C,0.138*%
+%ADD19C,0.0306*%
+%ADD20R,0.054X0.054*%
+%ADD21C,0.054*%
+%ADD22C,0.035*%
+G04 APERTURE END LIST*
+G54D10*
+G54D11*
+X70583Y-22169D03*
+X68417Y-22169D03*
+G54D12*
+X70479Y-23339D03*
+X68521Y-23339D03*
+G54D13*
+X44202Y-47702D03*
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+X43798Y-47298D03*
+X44202Y-47298D03*
+X40202Y-47702D03*
+X39798Y-47702D03*
+X39798Y-47298D03*
+X40202Y-47298D03*
+G54D14*
+X51225Y-27025D03*
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+X51819Y-26431D03*
+X51819Y-27025D03*
+X51819Y-27619D03*
+X51225Y-27619D03*
+X50631Y-27619D03*
+X50631Y-27025D03*
+X50631Y-26431D03*
+G54D13*
+X38150Y-27200D03*
+X37717Y-27200D03*
+X37717Y-26767D03*
+X38150Y-26767D03*
+X38583Y-26767D03*
+X38583Y-27200D03*
+X38583Y-27633D03*
+X38150Y-27633D03*
+X37717Y-27633D03*
+X46300Y-31600D03*
+X46039Y-31339D03*
+X46561Y-31339D03*
+X46561Y-31861D03*
+X46039Y-31861D03*
+G54D15*
+X59500Y-29000D03*
+G54D16*
+X60500Y-29000D03*
+X59500Y-30000D03*
+X60500Y-30000D03*
+X59500Y-31000D03*
+X60500Y-31000D03*
+X59500Y-32000D03*
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+X59500Y-33000D03*
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+X59500Y-34000D03*
+X60500Y-34000D03*
+X59500Y-35000D03*
+X60500Y-35000D03*
+X59500Y-36000D03*
+X60500Y-36000D03*
+G54D15*
+X66500Y-48500D03*
+G54D16*
+X66500Y-49500D03*
+X65500Y-48500D03*
+X65500Y-49500D03*
+X64500Y-48500D03*
+X64500Y-49500D03*
+X63500Y-48500D03*
+X63500Y-49500D03*
+X62500Y-48500D03*
+X62500Y-49500D03*
+X61500Y-48500D03*
+X61500Y-49500D03*
+G54D15*
+X78500Y-43500D03*
+G54D16*
+X77500Y-43500D03*
+X78500Y-42500D03*
+X77500Y-42500D03*
+X78500Y-41500D03*
+X77500Y-41500D03*
+X78500Y-40500D03*
+X77500Y-40500D03*
+X78500Y-39500D03*
+X77500Y-39500D03*
+X78500Y-38500D03*
+X77500Y-38500D03*
+G54D15*
+X78500Y-35500D03*
+G54D16*
+X77500Y-35500D03*
+X78500Y-34500D03*
+X77500Y-34500D03*
+X78500Y-33500D03*
+X77500Y-33500D03*
+X78500Y-32500D03*
+X77500Y-32500D03*
+X78500Y-31500D03*
+X77500Y-31500D03*
+G54D15*
+X50500Y-49500D03*
+G54D16*
+X50500Y-48500D03*
+X51500Y-49500D03*
+X51500Y-48500D03*
+X52500Y-49500D03*
+X52500Y-48500D03*
+X53500Y-49500D03*
+X53500Y-48500D03*
+X54500Y-49500D03*
+X54500Y-48500D03*
+G54D15*
+X76500Y-29000D03*
+G54D16*
+X76500Y-30000D03*
+X75500Y-29000D03*
+X75500Y-30000D03*
+X74500Y-29000D03*
+X74500Y-30000D03*
+X73500Y-29000D03*
+X73500Y-30000D03*
+G54D15*
+X78510Y-46500D03*
+G54D16*
+X78510Y-47500D03*
+X77510Y-46500D03*
+X77510Y-47500D03*
+X76510Y-46500D03*
+X76510Y-47500D03*
+G54D15*
+X69500Y-49500D03*
+G54D16*
+X70500Y-49500D03*
+X71500Y-49500D03*
+X72500Y-49500D03*
+X73500Y-49500D03*
+X74500Y-49500D03*
+G54D15*
+X47500Y-44500D03*
+G54D16*
+X47500Y-45500D03*
+X47500Y-46500D03*
+X47500Y-47500D03*
+X47500Y-48500D03*
+X47500Y-49500D03*
+G54D15*
+X63500Y-24000D03*
+G54D16*
+X64500Y-24000D03*
+X65500Y-24000D03*
+G54D15*
+X63500Y-23000D03*
+G54D16*
+X64500Y-23000D03*
+X65500Y-23000D03*
+G54D15*
+X63500Y-25000D03*
+G54D16*
+X64500Y-25000D03*
+X65500Y-25000D03*
+G54D15*
+X63500Y-26000D03*
+G54D16*
+X64500Y-26000D03*
+X65500Y-26000D03*
+G54D15*
+X67500Y-26000D03*
+G54D16*
+X67500Y-25000D03*
+G54D17*
+X43500Y-36500D03*
+X42500Y-37500D03*
+X44500Y-37500D03*
+X44500Y-35500D03*
+X42500Y-35500D03*
+X35000Y-44500D03*
+X36000Y-43500D03*
+X34000Y-43500D03*
+X34000Y-45500D03*
+X36000Y-45500D03*
+X43500Y-42500D03*
+X42500Y-43500D03*
+X44500Y-43500D03*
+X44500Y-41500D03*
+X42500Y-41500D03*
+G54D15*
+X54500Y-24000D03*
+G54D16*
+X54500Y-23000D03*
+G54D15*
+X77500Y-24000D03*
+G54D16*
+X77500Y-23000D03*
+G54D15*
+X77500Y-27000D03*
+G54D16*
+X77500Y-26000D03*
+G54D15*
+X42500Y-33500D03*
+G54D16*
+X43500Y-33500D03*
+G54D18*
+X26075Y-23075D03*
+X80925Y-23075D03*
+X80925Y-48925D03*
+X26075Y-48925D03*
+G54D19*
+X52575Y-34275D03*
+X52575Y-33625D03*
+X53225Y-33625D03*
+X53225Y-34275D03*
+X53225Y-34925D03*
+X52575Y-34925D03*
+X51925Y-34925D03*
+X51925Y-34275D03*
+X51925Y-33625D03*
+G54D20*
+X63000Y-29900D03*
+G54D21*
+X63000Y-29400D03*
+X63500Y-29900D03*
+X63500Y-29400D03*
+X64000Y-29900D03*
+X64000Y-29400D03*
+X64500Y-29900D03*
+X64500Y-29400D03*
+X65000Y-29900D03*
+X65000Y-29400D03*
+G54D22*
+X73750Y-25000D03*
+X73947Y-24705D03*
+X73553Y-24705D03*
+X73553Y-25295D03*
+X73947Y-25295D03*
+M02*

SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/jawbreaker-gerbers/jawbreaker-Edge_Cuts.gbr

@@ -0,0 +1,42 @@
+G04 (created by PCBNEW (2013-01-23 BZR 3920)-stable) date Mon Jun 10 00:49:26 2013*
+%MOIN*%
+G04 Gerber Fmt 3.4, Leading zero omitted, Abs format*
+%FSLAX34Y34*%
+G01*
+G70*
+G90*
+G04 APERTURE LIST*
+%ADD10C,2.3622e-06*%
+%ADD11C,0.015*%
+G04 APERTURE END LIST*
+G54D10*
+G54D11*
+X26075Y-21500D02*
+X80975Y-21500D01*
+X26075Y-50500D02*
+X80925Y-50500D01*
+X24500Y-23075D02*
+X24500Y-48925D01*
+X82500Y-23075D02*
+X82500Y-48925D01*
+X82500Y-23075D02*
+G75*
+G03X80925Y-21500I-1575J0D01*
+G74*
+G01*
+X80925Y-50500D02*
+G75*
+G03X82500Y-48925I0J1575D01*
+G74*
+G01*
+X24500Y-48925D02*
+G75*
+G03X26075Y-50500I1575J0D01*
+G74*
+G01*
+X26075Y-21500D02*
+G75*
+G03X24500Y-23075I0J-1575D01*
+G74*
+G01*
+M02*

SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/jawbreaker-gerbers/jawbreaker.drl

@@ -0,0 +1,715 @@
+M48
+INCH,TZ
+T1C0.013
+T2C0.014
+T3C0.015
+T4C0.016
+T5C0.020
+T6C0.025
+T7C0.028
+T8C0.040
+T9C0.041
+T10C0.047
+T11C0.060
+T12C0.067
+T13C0.126
+%
+G90
+G05
+T1
+X033650Y-039550
+X033650Y-040400
+X034350Y-022550
+X034550Y-039500
+X034740Y-041100
+X034750Y-030250
+X034780Y-035640
+X034850Y-026330
+X034900Y-034400
+X034900Y-034750
+X035010Y-039720
+X035150Y-033100
+X035420Y-022550
+X035600Y-033100
+X035660Y-037040
+X036000Y-025950
+X036000Y-031500
+X036050Y-033100
+X036050Y-034550
+X036090Y-024630
+X036100Y-025500
+X036280Y-035280
+X036370Y-039100
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+X038550Y-047360
+X038560Y-048220
+X038600Y-028630
+X038850Y-047960
+X038930Y-047230
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+X039000Y-046870
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+X039020Y-022820
+X039220Y-045050
+X039240Y-036530
+X039260Y-025930
+X039270Y-023190
+X039400Y-035520
+X039590Y-023020
+X039670Y-045890
+X039880Y-029130
+X040160Y-045620
+X040230Y-023850
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+X040410Y-042350
+X040570Y-035690
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+X040600Y-044770
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+X041450Y-031410
+X041600Y-047570
+X041710Y-031150
+X042000Y-047190
+X042200Y-023670
+X042340Y-023280
+X042370Y-047570
+X042870Y-047040
+X043098Y-025298
+X043100Y-024150
+X043130Y-026360
+X043390Y-046520
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+X044780Y-026900
+X044950Y-047000
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+X045330Y-047030
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+X050200Y-040360
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+X051620Y-029390
+X051670Y-028620
+X051670Y-029010
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+X052025Y-030975
+X052525Y-030975
+X052750Y-032450
+X052825Y-027335
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+               id="tspan3374">MAX5864</tspan></text>
+</g><g
+           id="g3376"><text
+             transform="matrix(1,0,0,-1,92.7,340.9)"
+             id="text3378"><tspan
+               style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-family:Arial;font-variant:normal;font-weight:900;font-size:44;writing-mode:lr;-inkscape-font-specification:Arial-Black"
+               x="0 34.276 68.376 102.652 114.84 147.136 180.444"
+               y="0"
+               sodipodi:role="line"
+               id="tspan3380">ADC/DAC</tspan></text>
+</g><g
+           id="g3382"><text
+             transform="matrix(1,0,0,-1,47.1,278.8)"
+             id="text3384"><tspan
+               style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-family:Arial;font-variant:normal;font-weight:900;font-size:44;writing-mode:lr;-inkscape-font-specification:Arial-Black"
+               x="0 36.652 66.088 80.696 100.232 129.58 144.188 173.536 202.884 244.376 281.028"
+               y="0"
+               sodipodi:role="line"
+               id="tspan3386">Up to 22MHz</tspan></text>
+</g><path
+           d="m 457.6,443.7 c 0,12.7 16.9,25.4 33.8,25.4 l 220.5,0 c 16.9,0 33.9,-12.7 33.9,-25.4 l 0,-165.2 c 0,-12.7 -17,-25.4 -33.9,-25.4 l -220.5,0 c -16.9,0 -33.8,12.7 -33.8,25.4 l 0,165.2 z"
+           style="fill:#99ccff;fill-opacity:1;fill-rule:evenodd;stroke:none"
+           id="path3388" /><g
+           id="g3390"><path
+             d="m 457.6,443.7 c 0,12.7 16.9,25.4 33.8,25.4 l 220.5,0 c 16.9,0 33.9,-12.7 33.9,-25.4 l 0,-165.2 c 0,-12.7 -17,-25.4 -33.9,-25.4 l -220.5,0 c -16.9,0 -33.8,12.7 -33.8,25.4 l 0,165.2 z"
+             style="fill:none;stroke:none"
+             id="path3392" /></g><g
+           id="g3394"><path
+             d="m 457.6,469.1 0,0 z"
+             style="fill:none;stroke:none"
+             id="path3396" /></g><g
+           id="g3398"><path
+             d="m 745.8,253.1 0,0 z"
+             style="fill:none;stroke:none"
+             id="path3400" /></g><g
+           id="g3402"><text
+             transform="matrix(1,0,0,-1,545.7,376)"
+             id="text3404"><tspan
+               style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-family:Arial;font-variant:normal;font-weight:900;font-size:48;writing-mode:lr;-inkscape-font-specification:Arial-Black"
+               x="0 39.888 77.184"
+               y="0"
+               sodipodi:role="line"
+               id="tspan3406">NXP</tspan></text>
+</g><g
+           id="g3408"><text
+             transform="matrix(1,0,0,-1,485.5,308.3)"
+             id="text3410"><tspan
+               style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-family:Arial;font-variant:normal;font-weight:900;font-size:48;writing-mode:lr;-inkscape-font-specification:Arial-Black"
+               x="0 32.064 66.72 104.016 135.984 168.048 200.016"
+               y="0"
+               sodipodi:role="line"
+               id="tspan3412">LPC43xx</tspan></text>
+</g><g
+           id="g3414"><path
+             d="m 429.9,361.1 -39.4,0"
+             style="fill:none;stroke:#000000;stroke-opacity:1;stroke-width:7.07499;stroke-linecap:butt;stroke-linejoin:round;stroke-miterlimit:10;stroke-dasharray:none"
+             id="path3416" /></g><path
+           d="m 457.6,361.1 -28.9,9.6 0,-19.3 28.9,9.7 z"
+           style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:none"
+           id="path3418" /><path
+           d="m 362.8,361.1 28.9,-9.7 0,19.3 -28.9,-9.6 z"
+           style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:none"
+           id="path3420" /><text
+           transform="matrix(1,0,0,-1,49,181.9)"
+           id="text3422"><tspan
+             style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-family:Arial;font-variant:normal;font-weight:900;font-size:48;writing-mode:lr;-inkscape-font-specification:Arial-Black"
+             x="0 45.264 77.328 109.296 125.28 173.28 205.248 253.248 269.232 301.2 333.264 378.528 418.512 445.104 461.088 498.384 535.68 572.976 586.32 621.504 657.984 695.28"
+             y="0"
+             sodipodi:role="line"
+             id="tspan3424">Maximum 20MHz ADC/DAC </tspan></text>
+<text
+           transform="matrix(1,0,0,-1,142.3,114.2)"
+           id="text3426"><tspan
+             style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-family:Arial;font-variant:normal;font-weight:900;font-size:48;writing-mode:lr;-inkscape-font-specification:Arial-Black"
+             x="0 15.888 31.872 79.872 95.76 117.12 149.088 181.152 197.136 229.104 258.384 274.272 314.256 348.912 386.208 418.176 434.16 474.144"
+             y="0"
+             sodipodi:role="line"
+             id="tspan3428">limited by USB2 HS</tspan></text>
+<text
+           transform="matrix(1,0,0,-1,192.5,46.5)"
+           id="text3430"><tspan
+             style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-family:Arial;font-variant:normal;font-weight:900;font-size:48;writing-mode:lr;-inkscape-font-specification:Arial-Black"
+             x="0 18.672 51.216 83.184 115.152 147.216 168.48 184.464 216.432 248.496 293.76 309.744 347.04 360.336 389.616"
+             y="0"
+             sodipodi:role="line"
+             id="tspan3432">(about 40MiB/s)</tspan></text>
+</g></g><g
+       id="g3434"><g
+         id="g3436" /><g
+         id="g3442"><g
+           clip-path="url(#clipPath3438)"
+           opacity="0.5"
+           id="g3444" /></g></g></g></svg>

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/.gitignore

@@ -0,0 +1,9 @@
+*.bin
+*.d
+*.elf
+*.hex
+*.list
+*.map
+*.o
+*.srec
+*.dfu

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/CMakeLists.txt

@@ -0,0 +1,36 @@
+# Copyright 2012 Jared Boone <jared@sharebrained.com>
+#
+# This file is part of HackRF.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+# Top directory CMake project for HackRF firmware
+
+cmake_minimum_required(VERSION 2.8.9)
+set(CMAKE_TOOLCHAIN_FILE toolchain-arm-cortex-m.cmake)
+
+project (hackrf_firmware_all)
+
+add_subdirectory(blinky)
+add_subdirectory(mixertx)
+add_subdirectory(sgpio)
+add_subdirectory(sgpio-rx)
+add_subdirectory(simpletx)
+add_subdirectory(startup)
+add_subdirectory(startup_systick)
+add_subdirectory(startup_systick_perfo)
+add_subdirectory(hackrf_usb)

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/README

@@ -0,0 +1,56 @@
+The primary firmware source code for USB HackRF devices is hackrf_usb.  Most of
+the other directories contain firmware source code for test and development.
+The common directory contains source code shared by multiple HackRF firmware
+projects.  The cpld directory contains HDL source for the CPLD.
+
+
+The firmware is set up for compilation with the GCC toolchain available here:
+
+https://code.launchpad.net/gcc-arm-embedded
+
+Required dependency:
+
+https://github.com/mossmann/libopencm3
+
+If you are using git, the preferred way to install libopencm3 is to use the
+submodule:
+
+$ cd ..
+$ git submodule init
+$ git submodule update
+$ cd firmware/libopencm3
+$ make
+
+
+To build and install a standard firmware image for HackRF One:
+
+$ cd hackrf_usb
+$ mkdir build
+$ cd build
+$ cmake .. -DBOARD=HACKRF_ONE
+$ make
+$ hackrf_spiflash -w hackrf_usb.bin
+
+If you have a Jawbreaker, use -DBOARD=JAWBREAKER instead.
+
+
+For loading firmware into RAM with DFU you will also need:
+
+http://dfu-util.gnumonks.org/
+
+To start up HackRF One in DFU mode, hold down the DFU button while powering it
+on or while pressing and releasing the RESET button.  Release the DFU button
+after the 3V3 LED illuminates.
+
+With dfu-util and dfu-suffix (from the dfu-util package) installed and with the
+HackRF operating in DFU mode, you can build firmware for RAM and load it with:
+
+$ cd hackrf_usb
+$ mkdir build
+$ cd build
+$ cmake .. -DRUN_FROM=RAM
+$ make hackrf_usb-program
+
+Alternatively you can load a .dfu file from a release package with:
+
+$ dfu-util --device 1fc9:000c --alt 0 --download hackrf_usb_ram.dfu

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/blinky/CMakeLists.txt

@@ -0,0 +1,33 @@
+# Copyright 2012 Michael Ossmann <mike@ossmann.com>
+# Copyright 2012 Jared Boone <jared@sharebrained.com>
+#
+# This file is part of HackRF.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+cmake_minimum_required(VERSION 2.8.9)
+set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
+
+project(blinky)
+
+include(../hackrf-common.cmake)
+
+set(SRC_M4
+	blinky.c
+)
+
+DeclareTargets()

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/blinky/README

@@ -0,0 +1 @@
+This is the simplest example firmware for HackRF.  It flashes three LEDs.

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/blinky/blinky.c

@@ -0,0 +1,54 @@
+/*
+ * Copyright 2010 - 2012 Michael Ossmann
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#include <libopencm3/lpc43xx/gpio.h>
+#include <libopencm3/lpc43xx/scu.h>
+
+#include "hackrf_core.h"
+
+uint32_t boot0, boot1, boot2, boot3;
+
+int main(void)
+{
+	int i;
+	pin_setup();
+
+	/* enable all power supplies */
+	enable_1v8_power();
+
+	/* Blink LED1/2/3 on the board and Read BOOT0/1/2/3 pins. */
+	while (1) 
+	{
+		boot0 = BOOT0_STATE;
+		boot1 = BOOT1_STATE;
+		boot2 = BOOT2_STATE;
+		boot3 = BOOT3_STATE;
+
+		gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */
+		for (i = 0; i < 2000000; i++)	/* Wait a bit. */
+			__asm__("nop");
+		gpio_clear(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LED off */
+		for (i = 0; i < 2000000; i++)	/* Wait a bit. */
+			__asm__("nop");
+	}
+
+	return 0;
+}

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/LPC4320_M4_memory.ld

@@ -0,0 +1,34 @@
+/*
+ * Copyright 2012 Michael Ossmann <mike@ossmann.com>
+ * Copyright 2012 Jared Boone <jared@sharebrained.com>
+ *
+ * This file is part of HackRF
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+/* Linker script for HackRF One (LPC4320, 1M SPI flash, 200K SRAM). */
+
+MEMORY
+{
+	/* rom is really the shadow region that points to SPI flash or elsewhere */
+	rom (rx)  : ORIGIN = 0x00000000, LENGTH =  96K
+	ram_local1 (rwx) : ORIGIN = 0x10000000, LENGTH =  96K
+	ram_local2 (rwx) : ORIGIN = 0x10080000, LENGTH =  32K
+	ram_sleep (rwx) : ORIGIN = 0x10088000, LENGTH = 8K
+}
+
+INCLUDE LPC43xx_M4_memory.ld

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/LPC4330_M4_memory.ld

@@ -0,0 +1,34 @@
+/*
+ * Copyright 2012 Michael Ossmann <mike@ossmann.com>
+ * Copyright 2012 Jared Boone <jared@sharebrained.com>
+ *
+ * This file is part of HackRF
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+/* Linker script for HackRF Jellybean/Jawbreaker (LPC4330, 1M SPI flash, 264K SRAM). */
+
+MEMORY
+{
+	/* rom is really the shadow region that points to SPI flash or elsewhere */
+	rom (rx)  : ORIGIN = 0x00000000, LENGTH =  128K
+	ram_local1 (rwx) : ORIGIN = 0x10000000, LENGTH =  128K
+	ram_local2 (rwx) : ORIGIN = 0x10080000, LENGTH =  64K
+	ram_sleep (rwx) : ORIGIN = 0x10090000, LENGTH = 8K
+}
+
+INCLUDE LPC43xx_M4_memory.ld

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/LPC43xx_M0_memory.ld

@@ -0,0 +1,26 @@
+/*
+ * Copyright 2012 Michael Ossmann <mike@ossmann.com>
+ * Copyright 2012 Jared Boone <jared@sharebrained.com>
+ *
+ * This file is part of HackRF
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+MEMORY
+{
+	ram (rwx) : ORIGIN = 0x00000000, LENGTH = 28K
+}

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/LPC43xx_M4_M0_image_from_text.ld

@@ -0,0 +1,31 @@
+/*
+ * Copyright 2012 Michael Ossmann <mike@ossmann.com>
+ * Copyright 2012 Jared Boone <jared@sharebrained.com>
+ *
+ * This file is part of HackRF
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+SECTIONS
+{
+	.text : {
+		PROVIDE(__m0_start__ = .);
+		KEEP(*(.m0_bin*));
+		. = ALIGN(4);
+		PROVIDE(__m0_end__ = .);
+	} >rom
+}

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/LPC43xx_M4_memory.ld

@@ -0,0 +1,36 @@
+/*
+ * Copyright 2012 Michael Ossmann <mike@ossmann.com>
+ * Copyright 2012 Jared Boone <jared@sharebrained.com>
+ *
+ * This file is part of HackRF
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+MEMORY
+{
+	/* Physical address in Flash used to copy Code from Flash to RAM */
+	rom_flash (rx)  : ORIGIN = 0x80000000, LENGTH =  1M
+	ram_m0 (rwx) : ORIGIN = 0x20000000, LENGTH = 28K
+	ram_shared (rwx) : ORIGIN = 0x20007000, LENGTH =  4K
+	ram_usb (rwx) : ORIGIN = 0x20008000, LENGTH = 32K
+	/* ram_usb: USB buffer. Straddles two blocks of RAM
+	 * to get performance benefit of having two USB buffers addressable
+	 * simultaneously (on two different buses of the AHB multilayer matrix)
+	 */
+}
+
+usb_bulk_buffer = ORIGIN(ram_usb);

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/README

@@ -0,0 +1,2 @@
+This directory contains things shared by multiple HackRF firmware
+implementations.

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/bitband.c

@@ -0,0 +1,45 @@
+/*
+ * Copyright 2012 Jared Boone <jared@sharebrained.com>
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#include "bitband.h"
+
+volatile uint32_t* peripheral_bitband_address(volatile void* const address, const uint_fast8_t bit_number) {
+    const uint32_t bit_band_base = 0x42000000;
+    const uint32_t byte_offset = (uint32_t)address - 0x40000000;
+    const uint32_t bit_word_offset = (byte_offset * 32) + (bit_number * 4);
+    const uint32_t bit_word_address = bit_band_base + bit_word_offset;
+    return (volatile uint32_t*)bit_word_address;
+}
+
+void peripheral_bitband_set(volatile void* const peripheral_address, const uint_fast8_t bit_number) {
+    volatile uint32_t* const bitband_address = peripheral_bitband_address(peripheral_address, bit_number);
+    *bitband_address = 1;
+}
+
+void peripheral_bitband_clear(volatile void* const peripheral_address, const uint_fast8_t bit_number) {
+    volatile uint32_t* const bitband_address = peripheral_bitband_address(peripheral_address, bit_number);
+    *bitband_address = 0;
+}
+
+uint32_t peripheral_bitband_get(volatile void* const peripheral_address, const uint_fast8_t bit_number) {
+    volatile uint32_t* const bitband_address = peripheral_bitband_address(peripheral_address, bit_number);
+    return *bitband_address;
+}

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/bitband.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright 2012 Jared Boone <jared@sharebrained.com>
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#ifndef __BITBAND_H__
+#define __BITBAND_H__
+
+#include <stdint.h>
+
+volatile uint32_t* peripheral_bitband_address(volatile void* const address, const uint_fast8_t bit_number);
+void peripheral_bitband_set(volatile void* const peripheral_address, const uint_fast8_t bit_number);
+void peripheral_bitband_clear(volatile void* const peripheral_address, const uint_fast8_t bit_number);
+uint32_t peripheral_bitband_get(volatile void* const peripheral_address, const uint_fast8_t bit_number);
+
+#endif//__BITBAND_H__

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/cpld_jtag.c

@@ -0,0 +1,88 @@
+/*
+ * Copyright 2013 Michael Ossmann <mike@ossmann.com>
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#include "cpld_jtag.h"
+#include "hackrf_core.h"
+#include "xapp058/micro.h"
+#include <libopencm3/lpc43xx/gpio.h>
+#include <libopencm3/lpc43xx/scu.h>
+#include <stdint.h>
+
+static refill_buffer_cb refill_buffer;
+static uint32_t xsvf_buffer_len, xsvf_pos;
+static unsigned char* xsvf_buffer;
+
+void cpld_jtag_setup(void) {
+	scu_pinmux(SCU_PINMUX_CPLD_TDO, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION4);
+	scu_pinmux(SCU_PINMUX_CPLD_TCK, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_PINMUX_CPLD_TMS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_PINMUX_CPLD_TDI, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
+	
+	/* TDO is an input */
+	GPIO_DIR(PORT_CPLD_TDO) &= ~PIN_CPLD_TDO;
+
+	/* the rest are outputs */
+	GPIO_DIR(PORT_CPLD_TCK) |= PIN_CPLD_TCK;
+	GPIO_DIR(PORT_CPLD_TMS) |= PIN_CPLD_TMS;
+	GPIO_DIR(PORT_CPLD_TDI) |= PIN_CPLD_TDI;
+}
+
+/* set pins as inputs so we don't interfere with an external JTAG device */
+void cpld_jtag_release(void) {
+	scu_pinmux(SCU_PINMUX_CPLD_TDO, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION4);
+	scu_pinmux(SCU_PINMUX_CPLD_TCK, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_PINMUX_CPLD_TMS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_PINMUX_CPLD_TDI, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
+	
+	GPIO_DIR(PORT_CPLD_TDO) &= ~PIN_CPLD_TDO;
+	GPIO_DIR(PORT_CPLD_TCK) &= ~PIN_CPLD_TCK;
+	GPIO_DIR(PORT_CPLD_TMS) &= ~PIN_CPLD_TMS;
+	GPIO_DIR(PORT_CPLD_TDI) &= ~PIN_CPLD_TDI;
+}
+
+/* return 0 if success else return error code see xsvfExecute() */
+int cpld_jtag_program(
+        const uint32_t buffer_length,
+        unsigned char* const buffer,
+        refill_buffer_cb refill
+) {
+	int error;
+	cpld_jtag_setup();
+	xsvf_buffer = buffer;
+	xsvf_buffer_len = buffer_length;
+        refill_buffer = refill;
+	error = xsvfExecute();
+	cpld_jtag_release();
+	
+	return error;
+}
+
+/* this gets called by the XAPP058 code */
+unsigned char cpld_jtag_get_next_byte(void) {
+        if (xsvf_pos == xsvf_buffer_len) {
+                refill_buffer();
+                xsvf_pos = 0;
+        }
+
+	unsigned char byte = xsvf_buffer[xsvf_pos];
+        xsvf_pos++;
+	return byte;
+}

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/cpld_jtag.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright 2013 Michael Ossmann <mike@ossmann.com>
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#ifndef __CPLD_JTAG_H__
+#define __CPLD_JTAG_H__
+
+#include <stdint.h>
+
+typedef void (*refill_buffer_cb)(void);
+
+void cpld_jtag_release(void);
+
+/* Return 0 if success else return error code see xsvfExecute() see micro.h.
+ *
+ * We expect the buffer to be initially full of data. After the entire
+ * contents of the buffer has been streamed to the CPLD the given
+ * refill_buffer callback will be called. */
+int cpld_jtag_program(
+        const uint32_t buffer_length,
+        unsigned char* const buffer,
+        refill_buffer_cb refill
+);
+unsigned char cpld_jtag_get_next_byte(void);
+
+#endif//__CPLD_JTAG_H__

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/fault_handler.c

@@ -0,0 +1,86 @@
+/*
+ * Copyright 2012 Jared Boone <jared@sharebrained.com>
+ * Copyright 2013 Benjamin Vernoux <titanmkd@gmail.com>
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#include <stdint.h>
+
+#include "fault_handler.h"
+
+typedef struct
+{
+	uint32_t r0;
+	uint32_t r1;
+	uint32_t r2;
+	uint32_t r3;
+	uint32_t r12;
+	uint32_t lr; /* Link Register. */
+	uint32_t pc; /* Program Counter. */
+	uint32_t psr;/* Program Status Register. */
+} hard_fault_stack_t;
+
+__attribute__((naked))
+void hard_fault_handler(void) {
+	__asm__("TST LR, #4");
+	__asm__("ITE EQ");
+	__asm__("MRSEQ R0, MSP");
+	__asm__("MRSNE R0, PSP");
+	__asm__("B hard_fault_handler_c");
+}
+
+volatile hard_fault_stack_t* hard_fault_stack_pt;
+
+__attribute__((used)) void hard_fault_handler_c(uint32_t* args) 
+{
+	/* hard_fault_stack_pt contains registers saved before the hard fault */
+	hard_fault_stack_pt = (hard_fault_stack_t*)args;
+	
+	// args[0-7]: r0, r1, r2, r3, r12, lr, pc, psr
+	// Other interesting registers to examine:
+	//	CFSR: Configurable Fault Status Register
+	//	HFSR: Hard Fault Status Register
+	//	DFSR: Debug Fault Status Register
+	//	AFSR: Auxiliary Fault Status Register
+	//	MMAR: MemManage Fault Address Register
+	//	BFAR: Bus Fault Address Register
+	
+	/*
+	if( SCB->HFSR & SCB_HFSR_FORCED ) {	
+		if( SCB->CFSR & SCB_CFSR_BFSR_BFARVALID ) {
+			SCB->BFAR;
+			if( SCB->CFSR & CSCB_CFSR_BFSR_PRECISERR ) {
+			}
+		}
+	}
+	*/
+	while(1);
+}
+
+void mem_manage_handler() {
+	while(1);
+}
+
+void bus_fault_handler() {
+	while(1);
+}
+
+void usage_fault_handler() {
+	while(1);
+}

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/fault_handler.h

@@ -0,0 +1,73 @@
+/*
+ * Copyright 2012 Jared Boone <jared@sharebrained.com>
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#ifndef __FAULT_HANDLER__
+#define __FAULT_HANDLER__
+
+#include <stdint.h>
+
+#include <libopencm3/cm3/memorymap.h>
+
+// TODO: Move all this to a Cortex-M(?) include file, since these
+// structures are supposedly the same between processors (to an
+// undetermined extent).
+typedef struct armv7m_scb_t armv7m_scb_t;
+struct armv7m_scb_t {
+	volatile const uint32_t CPUID;
+	volatile uint32_t ICSR;
+	volatile uint32_t VTOR;
+	volatile uint32_t AIRCR;
+	volatile uint32_t SCR;
+	volatile uint32_t CCR;
+	volatile uint32_t SHPR1;
+	volatile uint32_t SHPR2;
+	volatile uint32_t SHPR3;
+	volatile uint32_t SHCSR;
+	volatile uint32_t CFSR;
+	volatile uint32_t HFSR;
+	volatile uint32_t DFSR;
+	volatile uint32_t MMFAR;
+	volatile uint32_t BFAR;
+	volatile uint32_t AFSR;
+	volatile const uint32_t ID_PFR0;
+	volatile const uint32_t ID_PFR1;
+	volatile const uint32_t ID_DFR0;
+	volatile const uint32_t ID_AFR0;
+	volatile const uint32_t ID_MMFR0;
+	volatile const uint32_t ID_MMFR1;
+	volatile const uint32_t ID_MMFR2;
+	volatile const uint32_t ID_MMFR3;
+	volatile const uint32_t ID_ISAR0;
+	volatile const uint32_t ID_ISAR1;
+	volatile const uint32_t ID_ISAR2;
+	volatile const uint32_t ID_ISAR3;
+	volatile const uint32_t ID_ISAR4;
+	volatile const uint32_t __reserved_0x74_0x87[5];
+	volatile uint32_t CPACR;
+} __attribute__((packed));
+
+static armv7m_scb_t* const SCB = (armv7m_scb_t*)SCB_BASE;
+
+#define SCB_HFSR_DEBUGEVT (1 << 31)
+#define SCB_HFSR_FORCED (1 << 30)
+#define SCB_HFSR_VECTTBL (1 << 1)
+
+#endif//__FAULT_HANDLER__

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/gpdma.c

@@ -0,0 +1,62 @@
+/*
+ * Copyright 2013 Jared Boone <jared@sharebrained.com>
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#include <gpdma.h>
+
+#include <libopencm3/lpc43xx/gpdma.h>
+
+void gpdma_controller_enable() {
+	GPDMA_CONFIG |= GPDMA_CONFIG_E(1);
+	while( (GPDMA_CONFIG & GPDMA_CONFIG_E_MASK) == 0 );
+}
+
+void gpdma_channel_enable(const uint_fast8_t channel) {
+	GPDMA_CCONFIG(channel) |= GPDMA_CCONFIG_E(1);
+}
+
+void gpdma_channel_disable(const uint_fast8_t channel) {
+	GPDMA_CCONFIG(channel) &= ~GPDMA_CCONFIG_E_MASK;
+	while( (GPDMA_ENBLDCHNS & GPDMA_ENBLDCHNS_ENABLEDCHANNELS(1 << channel)) );
+}
+
+void gpdma_channel_interrupt_tc_clear(const uint_fast8_t channel) {
+	GPDMA_INTTCCLEAR = GPDMA_INTTCCLEAR_INTTCCLEAR(1 << channel);
+}
+
+void gpdma_channel_interrupt_error_clear(const uint_fast8_t channel) {
+	GPDMA_INTERRCLR = GPDMA_INTERRCLR_INTERRCLR(1 << channel);
+}
+
+void gpdma_lli_enable_interrupt(gpdma_lli_t* const lli) {
+	lli->ccontrol |= GPDMA_CCONTROL_I(1);
+}
+
+void gpdma_lli_create_loop(gpdma_lli_t* const lli, const size_t lli_count) {
+	for(size_t i=0; i<lli_count; i++) {
+		gpdma_lli_t* const next_lli = &lli[(i + 1) % lli_count];
+		lli[i].clli = (lli[i].clli & ~GPDMA_CLLI_LLI_MASK) | GPDMA_CLLI_LLI((uint32_t)next_lli >> 2);
+	}
+}
+
+void gpdma_lli_create_oneshot(gpdma_lli_t* const lli, const size_t lli_count) {
+	gpdma_lli_create_loop(lli, lli_count);
+	lli[lli_count - 1].clli &= ~GPDMA_CLLI_LLI_MASK;
+}

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/gpdma.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright 2013 Jared Boone <jared@sharebrained.com>
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#ifndef __GPDMA_H__
+#define __GPDMA_H__
+
+#include <stddef.h>
+#include <stdint.h>
+
+#include <libopencm3/lpc43xx/gpdma.h>
+
+void gpdma_controller_enable();
+
+void gpdma_channel_enable(const uint_fast8_t channel);
+void gpdma_channel_disable(const uint_fast8_t channel);
+
+void gpdma_channel_interrupt_tc_clear(const uint_fast8_t channel);
+void gpdma_channel_interrupt_error_clear(const uint_fast8_t channel);
+
+void gpdma_lli_enable_interrupt(gpdma_lli_t* const lli);
+
+void gpdma_lli_create_loop(gpdma_lli_t* const lli, const size_t lli_count);
+void gpdma_lli_create_oneshot(gpdma_lli_t* const lli, const size_t lli_count);
+
+#endif/*__GPDMA_H__*/

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/hackrf_core.c

@@ -0,0 +1,644 @@
+/*
+ * Copyright 2012 Michael Ossmann <mike@ossmann.com>
+ * Copyright 2012 Jared Boone <jared@sharebrained.com>
+ * Copyright 2013 Benjamin Vernoux <titanmkd@gmail.com>
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#include "hackrf_core.h"
+#include "si5351c.h"
+#include "max2837.h"
+#include "rffc5071.h"
+#include "sgpio.h"
+#include "rf_path.h"
+#include <libopencm3/lpc43xx/i2c.h>
+#include <libopencm3/lpc43xx/cgu.h>
+#include <libopencm3/lpc43xx/gpio.h>
+#include <libopencm3/lpc43xx/scu.h>
+#include <libopencm3/lpc43xx/ssp.h>
+
+#define WAIT_CPU_CLOCK_INIT_DELAY   (10000)
+
+void delay(uint32_t duration)
+{
+	uint32_t i;
+
+	for (i = 0; i < duration; i++)
+		__asm__("nop");
+}
+
+/* GCD algo from wikipedia */
+/* http://en.wikipedia.org/wiki/Greatest_common_divisor */
+static uint32_t
+gcd(uint32_t u, uint32_t v)
+{
+	int s;
+
+	if (!u || !v)
+		return u | v;
+
+	for (s=0; !((u|v)&1); s++) {
+		u >>= 1;
+		v >>= 1;
+	}
+
+	while (!(u&1))
+		u >>= 1;
+
+	do {
+		while (!(v&1))
+			v >>= 1;
+
+		if (u>v) {
+			uint32_t t;
+			t = v;
+			v = u;
+			u = t;
+		}
+
+		v = v - u;
+	}
+	while (v);
+
+	return u << s;
+}
+
+bool sample_rate_frac_set(uint32_t rate_num, uint32_t rate_denom)
+{
+	const uint64_t VCO_FREQ = 800 * 1000 * 1000; /* 800 MHz */
+	uint32_t MSx_P1,MSx_P2,MSx_P3;
+	uint32_t a, b, c;
+	uint32_t rem;
+
+	/* Find best config */
+	a = (VCO_FREQ * rate_denom) / rate_num;
+
+	rem = (VCO_FREQ * rate_denom) - (a * rate_num);
+
+	if (!rem) {
+		/* Integer mode */
+		b = 0;
+		c = 1;
+	} else {
+		/* Fractional */
+		uint32_t g = gcd(rem, rate_num);
+		rem /= g;
+		rate_num /= g;
+
+		if (rate_num < (1<<20)) {
+			/* Perfect match */
+			b = rem;
+			c = rate_num;
+		} else {
+			/* Approximate */
+			c = (1<<20) - 1;
+			b = ((uint64_t)c * (uint64_t)rem) / rate_num;
+
+			g = gcd(b, c);
+			b /= g;
+			c /= g;
+		}
+	}
+
+	/* Can we enable integer mode ? */
+	if (a & 0x1 || b)
+		si5351c_set_int_mode(0, 0);
+	else
+		si5351c_set_int_mode(0, 1);
+
+	/* Final MS values */
+	MSx_P1 = 128*a + (128 * b/c) - 512;
+	MSx_P2 = (128*b) % c;
+	MSx_P3 = c;
+
+	/* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */
+	si5351c_configure_multisynth(0, MSx_P1, MSx_P2, MSx_P3, 1);
+
+	/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
+	si5351c_configure_multisynth(1, 0, 0, 0, 0);//p1 doesn't matter
+
+	/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
+	si5351c_configure_multisynth(2, 0, 0, 0, 0);//p1 doesn't matter
+
+	return true;
+}
+
+bool sample_rate_set(const uint32_t sample_rate_hz) {
+#ifdef JELLYBEAN
+	/* Due to design issues, Jellybean/Lemondrop frequency plan is limited.
+	 * Long version of the story: The MAX2837 reference frequency
+	 * originates from the same PLL as the sample clocks, and in order to
+	 * keep the sample clocks in phase and keep jitter noise down, the MAX2837
+	 * and sample clocks must be integer-related.
+	 */
+	uint32_t r_div_sample = 2;
+	uint32_t r_div_sgpio = 1;
+	
+	switch( sample_rate_hz ) {
+	case 5000000:
+		r_div_sample = 3;	/* 800 MHz / 20 / 8 =  5 MHz */
+		r_div_sgpio = 2;	/* 800 MHz / 20 / 4 = 10 MHz */
+		break;
+		
+	case 10000000:
+		r_div_sample = 2;	/* 800 MHz / 20 / 4 = 10 MHz */
+		r_div_sgpio = 1;	/* 800 MHz / 20 / 2 = 20 MHz */
+		break;
+		
+	case 20000000:
+		r_div_sample = 1;	/* 800 MHz / 20 / 2 = 20 MHz */
+		r_div_sgpio = 0;	/* 800 MHz / 20 / 1 = 40 MHz */
+		break;
+		
+	default:
+		return false;
+	}
+	
+	/* NOTE: Because MS1, 2, 3 outputs are slaved to PLLA, the p1, p2, p3
+	 * values are irrelevant. */
+	
+	/* MS0/CLK1 is the source for the MAX5864 codec. */
+	si5351c_configure_multisynth(1, 4608, 0, 1, r_div_sample);
+
+	/* MS0/CLK2 is the source for the CPLD codec clock (same as CLK1). */
+	si5351c_configure_multisynth(2, 4608, 0, 1, r_div_sample);
+
+	/* MS0/CLK3 is the source for the SGPIO clock. */
+	si5351c_configure_multisynth(3, 4608, 0, 1, r_div_sgpio);
+	
+	return true;
+#endif
+
+#if (defined JAWBREAKER || defined HACKRF_ONE)
+	uint32_t p1 = 4608;
+	uint32_t p2 = 0;
+	uint32_t p3 = 0;
+	
+ 	switch(sample_rate_hz) {
+	case 8000000:
+		p1 = SI_INTDIV(50);	// 800MHz / 50 = 16 MHz (SGPIO), 8 MHz (codec)
+		break;
+		
+ 	case 9216000:
+ 		// 43.40277777777778: a = 43; b = 29; c = 72
+ 		p1 = 5043;
+ 		p2 = 40;
+ 		p3 = 72;
+ 		break;
+
+ 	case 10000000:
+		p1 = SI_INTDIV(40);	// 800MHz / 40 = 20 MHz (SGPIO), 10 MHz (codec)
+ 		break;
+ 
+ 	case 12288000:
+ 		// 32.552083333333336: a = 32; b = 159; c = 288
+ 		p1 = 3654;
+ 		p2 = 192;
+ 		p3 = 288;
+ 		break;
+
+ 	case 12500000:
+		p1 = SI_INTDIV(32);	// 800MHz / 32 = 25 MHz (SGPIO), 12.5 MHz (codec)
+ 		break;
+ 
+ 	case 16000000:
+		p1 = SI_INTDIV(25);	// 800MHz / 25 = 32 MHz (SGPIO), 16 MHz (codec)
+ 		break;
+ 	
+ 	case 18432000:
+ 		// 21.70138888889: a = 21; b = 101; c = 144
+ 		p1 = 2265;
+ 		p2 = 112;
+ 		p3 = 144;
+ 		break;
+
+ 	case 20000000:
+		p1 = SI_INTDIV(20);	// 800MHz / 20 = 40 MHz (SGPIO), 20 MHz (codec)
+ 		break;
+	
+	default:
+		return false;
+	}
+	
+	/* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */
+	si5351c_configure_multisynth(0, p1, p2, p3, 1);
+
+	/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
+	si5351c_configure_multisynth(1, p1, 0, 1, 0);//p1 doesn't matter
+
+	/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
+	si5351c_configure_multisynth(2, p1, 0, 1, 0);//p1 doesn't matter
+
+	return true;
+#endif
+}
+
+bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz) {
+	return max2837_set_lpf_bandwidth(bandwidth_hz);
+}
+
+/* clock startup for Jellybean with Lemondrop attached
+Configure PLL1 to max speed (204MHz).
+Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */ 
+void cpu_clock_init(void)
+{
+	/* use IRC as clock source for APB1 (including I2C0) */
+	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);
+
+	/* use IRC as clock source for APB3 */
+	CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC);
+
+	i2c0_init(15);
+
+	si5351c_disable_all_outputs();
+	si5351c_disable_oeb_pin_control();
+	si5351c_power_down_all_clocks();
+	si5351c_set_crystal_configuration();
+	si5351c_enable_xo_and_ms_fanout();
+	si5351c_configure_pll_sources();
+	si5351c_configure_pll_multisynth();
+
+#ifdef JELLYBEAN
+	/*
+	 * Jellybean/Lemondrop clocks:
+	 *   CLK0 -> MAX2837
+	 *   CLK1 -> MAX5864/CPLD.GCLK0
+	 *   CLK2 -> CPLD.GCLK1
+	 *   CLK3 -> CPLD.GCLK2
+	 *   CLK4 -> LPC4330
+	 *   CLK5 -> RFFC5072
+	 *   CLK6 -> extra
+	 *   CLK7 -> extra
+	 */
+
+	/* MS0/CLK0 is the source for the MAX2837 clock input. */
+	si5351c_configure_multisynth(0, 2048, 0, 1, 0); /* 40MHz */
+
+	/* MS4/CLK4 is the source for the LPC43xx microcontroller. */
+	si5351c_configure_multisynth(4, 8021, 0, 3, 0); /* 12MHz */
+
+	/* MS5/CLK5 is the source for the RFFC5071 mixer. */
+	si5351c_configure_multisynth(5, 1536, 0, 1, 0); /* 50MHz */
+#endif
+
+#if (defined JAWBREAKER || defined HACKRF_ONE)
+	/*
+	 * Jawbreaker clocks:
+	 *   CLK0 -> MAX5864/CPLD
+	 *   CLK1 -> CPLD
+	 *   CLK2 -> SGPIO
+	 *   CLK3 -> external clock output
+	 *   CLK4 -> RFFC5072
+	 *   CLK5 -> MAX2837
+	 *   CLK6 -> none
+	 *   CLK7 -> LPC4330 (but LPC4330 starts up on its own crystal)
+	 */
+
+	/* MS3/CLK3 is the source for the external clock output. */
+	si5351c_configure_multisynth(3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */
+
+	/* MS4/CLK4 is the source for the RFFC5071 mixer. */
+	si5351c_configure_multisynth(4, 16*128-512, 0, 1, 0); /* 800/16 = 50MHz */
+ 
+ 	/* MS5/CLK5 is the source for the MAX2837 clock input. */
+	si5351c_configure_multisynth(5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
+
+	/* MS6/CLK6 is unused. */
+	/* MS7/CLK7 is the source for the LPC43xx microcontroller. */
+	uint8_t ms7data[] = { 90, 255, 20, 0 };
+	si5351c_write(ms7data, sizeof(ms7data));
+#endif
+
+	/* Set to 10 MHz, the common rate between Jellybean and Jawbreaker. */
+	sample_rate_set(10000000);
+
+	si5351c_set_clock_source(PLL_SOURCE_XTAL);
+	// soft reset
+	uint8_t resetdata[] = { 177, 0xac };
+	si5351c_write(resetdata, sizeof(resetdata));
+	si5351c_enable_clock_outputs();
+
+	//FIXME disable I2C
+	/* Kick I2C0 down to 400kHz when we switch over to APB1 clock = 204MHz */
+	i2c0_init(255);
+
+	/*
+	 * 12MHz clock is entering LPC XTAL1/OSC input now.  On
+	 * Jellybean/Lemondrop, this is a signal from the clock generator.  On
+	 * Jawbreaker, there is a 12 MHz crystal at the LPC.
+	 * Set up PLL1 to run from XTAL1 input.
+	 */
+
+	//FIXME a lot of the details here should be in a CGU driver
+
+#ifdef JELLYBEAN
+	/* configure xtal oscillator for external clock input signal */
+	CGU_XTAL_OSC_CTRL |= CGU_XTAL_OSC_CTRL_BYPASS;
+#endif
+
+	/* set xtal oscillator to low frequency mode */
+	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF_MASK;
+
+	/* power on the oscillator and wait until stable */
+	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE_MASK;
+
+	/* Wait about 100us after Crystal Power ON */
+	delay(WAIT_CPU_CLOCK_INIT_DELAY);
+
+	/* use XTAL_OSC as clock source for BASE_M4_CLK (CPU) */
+	CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
+
+	/* use XTAL_OSC as clock source for APB1 */
+	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
+			| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
+
+	/* use XTAL_OSC as clock source for APB3 */
+	CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
+			| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);
+
+	cpu_clock_pll1_low_speed();
+
+	/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
+	CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
+
+	/* use XTAL_OSC as clock source for PLL0USB */
+	CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1)
+			| CGU_PLL0USB_CTRL_AUTOBLOCK(1)
+			| CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL);
+	while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK);
+
+	/* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */
+	/* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */
+	CGU_PLL0USB_MDIV = 0x06167FFA;
+	CGU_PLL0USB_NP_DIV = 0x00302062;
+	CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD(1)
+			| CGU_PLL0USB_CTRL_DIRECTI(1)
+			| CGU_PLL0USB_CTRL_DIRECTO(1)
+			| CGU_PLL0USB_CTRL_CLKEN(1));
+
+	/* power on PLL0USB and wait until stable */
+	CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD_MASK;
+	while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK));
+
+	/* use PLL0USB as clock source for USB0 */
+	CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK(1)
+			| CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);
+
+	/* Switch peripheral clock over to use PLL1 (204MHz) */
+	CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK(1)
+			| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
+
+	/* Switch APB1 clock over to use PLL1 (204MHz) */
+	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
+			| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
+
+	/* Switch APB3 clock over to use PLL1 (204MHz) */
+	CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
+			| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1);
+}
+
+
+/* 
+Configure PLL1 to low speed (48MHz).
+Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1.
+This function shall be called after cpu_clock_init().
+This function is mainly used to lower power consumption.
+*/
+void cpu_clock_pll1_low_speed(void)
+{
+	uint32_t pll_reg;
+
+	/* Configure PLL1 Clock (48MHz) */
+	/* Integer mode:
+		FCLKOUT = M*(FCLKIN/N) 
+		FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N) 
+	*/
+	pll_reg = CGU_PLL1_CTRL;
+	/* Clear PLL1 bits */
+	pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK |  /* CLK SEL, PowerDown , FBSEL */
+				  CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
+				  CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
+				  CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
+	/* Set PLL1 up to 12MHz * 4 = 48MHz. */
+	pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
+				| CGU_PLL1_CTRL_PSEL(0)
+				| CGU_PLL1_CTRL_NSEL(0)
+				| CGU_PLL1_CTRL_MSEL(3)
+				| CGU_PLL1_CTRL_FBSEL(1)
+				| CGU_PLL1_CTRL_DIRECT(1);
+	CGU_PLL1_CTRL = pll_reg;
+	/* wait until stable */
+	while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
+
+	/* Wait a delay after switch to new frequency with Direct mode */
+	delay(WAIT_CPU_CLOCK_INIT_DELAY);
+}
+
+/* 
+Configure PLL1 (Main MCU Clock) to max speed (204MHz).
+Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1.
+This function shall be called after cpu_clock_init().
+*/
+void cpu_clock_pll1_max_speed(void)
+{
+	uint32_t pll_reg;
+
+	/* Configure PLL1 to Intermediate Clock (between 90 MHz and 110 MHz) */
+	/* Integer mode:
+		FCLKOUT = M*(FCLKIN/N) 
+		FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N) 
+	*/
+	pll_reg = CGU_PLL1_CTRL;
+	/* Clear PLL1 bits */
+	pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK |  /* CLK SEL, PowerDown , FBSEL */
+				  CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
+				  CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
+				  CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
+	/* Set PLL1 up to 12MHz * 8 = 96MHz. */
+	pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
+				| CGU_PLL1_CTRL_PSEL(0)
+				| CGU_PLL1_CTRL_NSEL(0)
+				| CGU_PLL1_CTRL_MSEL(7)
+				| CGU_PLL1_CTRL_FBSEL(1);
+	CGU_PLL1_CTRL = pll_reg;
+	/* wait until stable */
+	while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
+
+	/* Wait before to switch to max speed */
+	delay(WAIT_CPU_CLOCK_INIT_DELAY);
+
+	/* Configure PLL1 Max Speed */
+	/* Direct mode: FCLKOUT = FCCO = M*(FCLKIN/N) */
+	pll_reg = CGU_PLL1_CTRL;
+	/* Clear PLL1 bits */
+	pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK |  /* CLK SEL, PowerDown , FBSEL */
+				  CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
+				  CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
+				  CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
+	/* Set PLL1 up to 12MHz * 17 = 204MHz. */
+	pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
+			| CGU_PLL1_CTRL_PSEL(0)
+			| CGU_PLL1_CTRL_NSEL(0)
+			| CGU_PLL1_CTRL_MSEL(16)
+			| CGU_PLL1_CTRL_FBSEL(1)
+			| CGU_PLL1_CTRL_DIRECT(1);
+	CGU_PLL1_CTRL = pll_reg;
+	/* wait until stable */
+	while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
+
+}
+
+void ssp1_init(void)
+{
+	/*
+	 * Configure CS_AD pin to keep the MAX5864 SPI disabled while we use the
+	 * SPI bus for the MAX2837. FIXME: this should probably be somewhere else.
+	 */
+	scu_pinmux(SCU_AD_CS, SCU_GPIO_FAST);
+	GPIO_SET(PORT_AD_CS) = PIN_AD_CS;
+	GPIO_DIR(PORT_AD_CS) |= PIN_AD_CS;
+
+	scu_pinmux(SCU_XCVR_CS, SCU_GPIO_FAST);
+	GPIO_SET(PORT_XCVR_CS) = PIN_XCVR_CS;
+	GPIO_DIR(PORT_XCVR_CS) |= PIN_XCVR_CS;
+	
+	/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
+	scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+	scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+	scu_pinmux(SCU_SSP1_SCK,  (SCU_SSP_IO | SCU_CONF_FUNCTION1));
+}
+
+void ssp1_set_mode_max2837(void)
+{
+	/* FIXME speed up once everything is working reliably */
+	/*
+	// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
+	const uint8_t serial_clock_rate = 32;
+	const uint8_t clock_prescale_rate = 128;
+	*/
+	// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
+	const uint8_t serial_clock_rate = 21;
+	const uint8_t clock_prescale_rate = 2;
+	
+	ssp_init(SSP1_NUM,
+		SSP_DATA_16BITS,
+		SSP_FRAME_SPI,
+		SSP_CPOL_0_CPHA_0,
+		serial_clock_rate,
+		clock_prescale_rate,
+		SSP_MODE_NORMAL,
+		SSP_MASTER,
+		SSP_SLAVE_OUT_ENABLE);
+}
+
+void ssp1_set_mode_max5864(void)
+{
+	/* FIXME speed up once everything is working reliably */
+	/*
+	// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
+	const uint8_t serial_clock_rate = 32;
+	const uint8_t clock_prescale_rate = 128;
+	*/
+	// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
+	const uint8_t serial_clock_rate = 21;
+	const uint8_t clock_prescale_rate = 2;
+	
+	ssp_init(SSP1_NUM,
+		SSP_DATA_8BITS,
+		SSP_FRAME_SPI,
+		SSP_CPOL_0_CPHA_0,
+		serial_clock_rate,
+		clock_prescale_rate,
+		SSP_MODE_NORMAL,
+		SSP_MASTER,
+		SSP_SLAVE_OUT_ENABLE);
+}
+
+void pin_setup(void) {
+	/* Release CPLD JTAG pins */
+	scu_pinmux(SCU_PINMUX_CPLD_TDO, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION4);
+	scu_pinmux(SCU_PINMUX_CPLD_TCK, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_PINMUX_CPLD_TMS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_PINMUX_CPLD_TDI, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
+	
+	GPIO_DIR(PORT_CPLD_TDO) &= ~PIN_CPLD_TDO;
+	GPIO_DIR(PORT_CPLD_TCK) &= ~PIN_CPLD_TCK;
+	GPIO_DIR(PORT_CPLD_TMS) &= ~PIN_CPLD_TMS;
+	GPIO_DIR(PORT_CPLD_TDI) &= ~PIN_CPLD_TDI;
+	
+	/* Configure SCU Pin Mux as GPIO */
+	scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_NOPULL);
+	scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_NOPULL);
+	scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_NOPULL);
+	
+	scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_NOPULL);
+	
+	/* Configure USB indicators */
+#if (defined JELLYBEAN || defined JAWBREAKER)
+	scu_pinmux(SCU_PINMUX_USB_LED0, SCU_CONF_FUNCTION3);
+	scu_pinmux(SCU_PINMUX_USB_LED1, SCU_CONF_FUNCTION3);
+#endif
+
+	/* Configure all GPIO as Input (safe state) */
+	GPIO0_DIR = 0;
+	GPIO1_DIR = 0;
+	GPIO2_DIR = 0;
+	GPIO3_DIR = 0;
+	GPIO4_DIR = 0;
+	GPIO5_DIR = 0;
+	GPIO6_DIR = 0;
+	GPIO7_DIR = 0;
+
+	/* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
+	GPIO2_DIR |= (PIN_LED1 | PIN_LED2 | PIN_LED3);
+
+	/* GPIO3[6] on P6_10  as output. */
+	GPIO3_DIR |= PIN_EN1V8;
+
+	rf_path_pin_setup();
+	
+	/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
+	scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+	scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+	scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
+	scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
+	
+	/* Configure external clock in */
+	scu_pinmux(SCU_PINMUX_GP_CLKIN, SCU_CLK_IN | SCU_CONF_FUNCTION1);
+
+	sgpio_configure_pin_functions();
+}
+
+void enable_1v8_power(void) {
+	gpio_set(PORT_EN1V8, PIN_EN1V8);
+}
+
+void disable_1v8_power(void) {
+	gpio_clear(PORT_EN1V8, PIN_EN1V8);
+}
+
+#ifdef HACKRF_ONE
+void enable_rf_power(void) {
+	gpio_clear(PORT_NO_VAA_ENABLE, PIN_NO_VAA_ENABLE);
+}
+
+void disable_rf_power(void) {
+	gpio_set(PORT_NO_VAA_ENABLE, PIN_NO_VAA_ENABLE);
+}
+#endif

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/hackrf_core.h

@@ -0,0 +1,380 @@
+/*
+ * Copyright 2012 Michael Ossmann <mike@ossmann.com>
+ * Copyright 2012 Benjamin Vernoux <titanmkd@gmail.com>
+ * Copyright 2012 Jared Boone <jared@sharebrained.com>
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#ifndef __HACKRF_CORE_H
+#define __HACKRF_CORE_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/* hardware identification number */
+#define BOARD_ID_JELLYBEAN  0
+#define BOARD_ID_JAWBREAKER 1
+#define BOARD_ID_HACKRF_ONE 2
+
+#ifdef JELLYBEAN
+#define BOARD_ID BOARD_ID_JELLYBEAN
+#endif
+
+#ifdef JAWBREAKER
+#define BOARD_ID BOARD_ID_JAWBREAKER
+#endif
+
+#ifdef HACKRF_ONE
+#define BOARD_ID BOARD_ID_HACKRF_ONE
+#endif
+
+/*
+ * SCU PinMux
+ */
+
+/* GPIO Output PinMux */
+#define SCU_PINMUX_LED1     (P4_1)  /* GPIO2[1] on P4_1 */
+#define SCU_PINMUX_LED2     (P4_2)  /* GPIO2[2] on P4_2 */
+#define SCU_PINMUX_LED3     (P6_12) /* GPIO2[8] on P6_12 */
+
+#define SCU_PINMUX_EN1V8    (P6_10) /* GPIO3[6] on P6_10 */
+
+/* GPIO Input PinMux */
+#define SCU_PINMUX_BOOT0    (P1_1)  /* GPIO0[8] on P1_1 */
+#define SCU_PINMUX_BOOT1    (P1_2)  /* GPIO0[9] on P1_2 */
+#define SCU_PINMUX_BOOT2    (P2_8)  /* GPIO5[7] on P2_8 */
+#define SCU_PINMUX_BOOT3    (P2_9)  /* GPIO1[10] on P2_9 */
+
+/* USB peripheral */
+#if (defined JELLYBEAN || defined JAWBREAKER)
+#define SCU_PINMUX_USB_LED0 (P6_8)
+#define SCU_PINMUX_USB_LED1 (P6_7)
+#endif
+
+/* SSP1 Peripheral PinMux */
+#define SCU_SSP1_MISO       (P1_3)  /* P1_3 */
+#define SCU_SSP1_MOSI       (P1_4)  /* P1_4 */
+#define SCU_SSP1_SCK        (P1_19) /* P1_19 */
+#define SCU_SSP1_SSEL       (P1_20) /* P1_20 */
+
+/* CPLD JTAG interface */
+#define SCU_PINMUX_CPLD_TDO (P9_5)  /* GPIO5[18] */
+#define SCU_PINMUX_CPLD_TCK (P6_1)  /* GPIO3[ 0] */
+#ifdef HACKRF_ONE
+#define SCU_PINMUX_CPLD_TMS (P6_5)  /* GPIO3[ 4] */
+#define SCU_PINMUX_CPLD_TDI (P6_2)  /* GPIO3[ 1] */
+#else
+#define SCU_PINMUX_CPLD_TMS (P6_2)  /* GPIO3[ 1] */
+#define SCU_PINMUX_CPLD_TDI (P6_5)  /* GPIO3[ 4] */
+#endif
+
+/* CPLD SGPIO interface */
+#define SCU_PINMUX_SGPIO0   (P0_0)
+#define SCU_PINMUX_SGPIO1   (P0_1)
+#define SCU_PINMUX_SGPIO2   (P1_15)
+#define SCU_PINMUX_SGPIO3   (P1_16)
+#define SCU_PINMUX_SGPIO4   (P6_3)
+#define SCU_PINMUX_SGPIO5   (P6_6)
+#define SCU_PINMUX_SGPIO6   (P2_2)
+#define SCU_PINMUX_SGPIO7   (P1_0)
+#ifdef JELLYBEAN
+#define SCU_PINMUX_SGPIO8   (P1_12)
+#endif
+#if (defined JAWBREAKER || defined HACKRF_ONE)
+#define SCU_PINMUX_SGPIO8   (P9_6)
+#endif
+#define SCU_PINMUX_SGPIO9   (P4_3)
+#define SCU_PINMUX_SGPIO10  (P1_14)
+#define SCU_PINMUX_SGPIO11  (P1_17)
+#define SCU_PINMUX_SGPIO12  (P1_18)
+#define SCU_PINMUX_SGPIO13  (P4_8)
+#define SCU_PINMUX_SGPIO14  (P4_9)
+#define SCU_PINMUX_SGPIO15  (P4_10)
+
+/* MAX2837 GPIO (XCVR_CTL) PinMux */
+#ifdef JELLYBEAN
+#define SCU_XCVR_RXHP		(P4_0)	/* GPIO2[0] on P4_0 */
+#define SCU_XCVR_B1			(P5_0)	/* GPIO2[9] on P5_0 */
+#define SCU_XCVR_B2			(P5_1)	/* GPIO2[10] on P5_1 */
+#define SCU_XCVR_B3			(P5_2)	/* GPIO2[11] on P5_2 */
+#define SCU_XCVR_B4			(P5_3)	/* GPIO2[12] on P5_3 */
+#define SCU_XCVR_B5			(P5_4)	/* GPIO2[13] on P5_4 */
+#define SCU_XCVR_B6			(P5_5)	/* GPIO2[14] on P5_5 */
+#define SCU_XCVR_B7			(P5_6)	/* GPIO2[15] on P5_6 */
+#endif
+#define SCU_XCVR_ENABLE     (P4_6)  /* GPIO2[6] on P4_6 */
+#define SCU_XCVR_RXENABLE   (P4_5)  /* GPIO2[5] on P4_5 */
+#define SCU_XCVR_TXENABLE   (P4_4)  /* GPIO2[4] on P4_4 */
+#define SCU_XCVR_CS         (P1_20) /* GPIO0[15] on P1_20 */
+
+/* MAX5864 SPI chip select (AD_CS) GPIO PinMux */
+#define SCU_AD_CS           (P5_7)  /* GPIO2[7] on P5_7 */
+
+/* RFFC5071 GPIO serial interface PinMux */
+#ifdef JELLYBEAN
+#define SCU_MIXER_ENX       (P7_0)  /* GPIO3[8] on P7_0 */
+#define SCU_MIXER_SCLK      (P7_1)  /* GPIO3[9] on P7_1 */
+#define SCU_MIXER_SDATA     (P7_2)  /* GPIO3[10] on P7_2 */
+#define SCU_MIXER_RESETX    (P7_3)  /* GPIO3[11] on P7_3 */
+#endif
+#if (defined JAWBREAKER || defined HACKRF_ONE)
+#define SCU_MIXER_ENX       (P5_4)  /* GPIO2[13] on P5_4 */
+#define SCU_MIXER_SCLK      (P2_6)  /* GPIO5[6] on P2_6 */
+#define SCU_MIXER_SDATA     (P6_4)  /* GPIO3[3] on P6_4 */
+#define SCU_MIXER_RESETX    (P5_5)  /* GPIO2[14] on P5_5 */
+#endif
+
+/* RF LDO control */
+#ifdef JAWBREAKER
+#define SCU_RF_LDO_ENABLE   (P5_0)  /* GPIO2[9] on P5_0 */
+#endif
+
+/* RF supply (VAA) control */
+#ifdef HACKRF_ONE
+#define SCU_NO_VAA_ENABLE   (P5_0)  /* GPIO2[9] on P5_0 */
+#endif
+
+/* SPI flash */
+#define SCU_SSP0_MISO       (P3_6)
+#define SCU_SSP0_MOSI       (P3_7)
+#define SCU_SSP0_SCK        (P3_3)
+#define SCU_SSP0_SSEL       (P3_8) /* GPIO5[11] on P3_8 */
+#define SCU_FLASH_HOLD      (P3_4) /* GPIO1[14] on P3_4 */
+#define SCU_FLASH_WP        (P3_5) /* GPIO1[15] on P3_5 */
+
+/* RF switch control */
+#ifdef HACKRF_ONE
+#define SCU_HP              (P4_0)  /* GPIO2[0] on P4_0 */
+#define SCU_LP              (P5_1)  /* GPIO2[10] on P5_1 */
+#define SCU_TX_MIX_BP       (P5_2)  /* GPIO2[11] on P5_2 */
+#define SCU_NO_MIX_BYPASS   (P1_7)  /* GPIO1[0] on P1_7 */
+#define SCU_RX_MIX_BP       (P5_3)  /* GPIO2[12] on P5_3 */
+#define SCU_TX_AMP          (P5_6)  /* GPIO2[15] on P5_6 */
+#define SCU_TX              (P6_7)  /* GPIO5[15] on P6_7 */
+#define SCU_MIX_BYPASS      (P6_8)  /* GPIO5[16] on P6_8 */
+#define SCU_RX              (P2_5)  /* GPIO5[5] on P2_5 */
+#define SCU_NO_TX_AMP_PWR   (P6_9)  /* GPIO3[5] on P6_9 */
+#define SCU_AMP_BYPASS      (P2_10) /* GPIO0[14] on P2_10 */
+#define SCU_RX_AMP          (P2_11) /* GPIO1[11] on P2_11 */
+#define SCU_NO_RX_AMP_PWR   (P2_12) /* GPIO1[12] on P2_12 */
+#endif
+
+/* TODO add other Pins */
+#define SCU_PINMUX_GPIO3_8  (P7_0)  /* GPIO3[8] */
+#define SCU_PINMUX_GPIO3_9  (P7_1)  /* GPIO3[9] */
+#define SCU_PINMUX_GPIO3_10 (P7_2)  /* GPIO3[10] */
+#define SCU_PINMUX_GPIO3_11 (P7_3)  /* GPIO3[11] */
+#define SCU_PINMUX_GPIO3_12 (P7_4)  /* GPIO3[12] */
+#define SCU_PINMUX_GPIO3_13 (P7_5)  /* GPIO3[13] */
+#define SCU_PINMUX_GPIO3_14 (P7_6)  /* GPIO3[14] */
+#define SCU_PINMUX_GPIO3_15 (P7_7)  /* GPIO3[15] */
+
+#define SCU_PINMUX_SD_POW   (P1_5)  /* GPIO1[8] */
+#define SCU_PINMUX_SD_CMD   (P1_6)  /* GPIO1[9] */
+#define SCU_PINMUX_SD_VOLT0 (P1_8)  /* GPIO1[1] */
+#define SCU_PINMUX_SD_DAT0  (P1_9)  /* GPIO1[2] */
+#define SCU_PINMUX_SD_DAT1  (P1_10) /* GPIO1[3] */
+#define SCU_PINMUX_SD_DAT2  (P1_11) /* GPIO1[4] */
+#define SCU_PINMUX_SD_DAT3  (P1_12) /* GPIO1[5] */
+#define SCU_PINMUX_SD_CD    (P1_13) /* GPIO1[6] */
+
+#define SCU_PINMUX_U0_TXD   (P2_0)  /* GPIO5[0] */
+#define SCU_PINMUX_U0_RXD   (P2_1)  /* GPIO5[1] */
+
+#define SCU_PINMUX_ISP      (P2_7)  /* GPIO0[7] */
+
+#define SCU_PINMUX_GP_CLKIN	(P4_7)
+
+/*
+ * GPIO Pins
+ */
+
+/* GPIO Output */
+#define PIN_LED1    (BIT1) /* GPIO2[1] on P4_1 */
+#define PIN_LED2    (BIT2) /* GPIO2[2] on P4_2 */
+#define PIN_LED3    (BIT8) /* GPIO2[8] on P6_12 */
+#define PORT_LED1_3 (GPIO2) /* PORT for LED1, 2 & 3 */
+
+#define PIN_EN1V8   (BIT6) /* GPIO3[6] on P6_10 */
+#define PORT_EN1V8  (GPIO3)
+
+#define PIN_XCVR_CS       (BIT15) /* GPIO0[15] on P1_20 */
+#define PORT_XCVR_CS      (GPIO0) /* PORT for CS */
+#define PIN_XCVR_ENABLE   (BIT6)  /* GPIO2[6] on P4_6 */
+#define PIN_XCVR_RXENABLE (BIT5)  /* GPIO2[5] on P4_5 */
+#define PIN_XCVR_TXENABLE (BIT4)  /* GPIO2[4] on P4_4 */
+#define PORT_XCVR_ENABLE  (GPIO2) /* PORT for ENABLE, TXENABLE, RXENABLE */
+#ifdef JELLYBEAN
+#define PIN_XCVR_RXHP     (BIT0)  /* GPIO2[0] on P4_0 */
+#define PORT_XCVR_RXHP	  (GPIO2)
+#define PIN_XCVR_B1		  (BIT9)  /* GPIO2[9] on P5_0 */
+#define PIN_XCVR_B2		  (BIT10) /* GPIO2[10] on P5_1 */
+#define PIN_XCVR_B3		  (BIT11) /* GPIO2[11] on P5_2 */
+#define PIN_XCVR_B4		  (BIT12) /* GPIO2[12] on P5_3 */
+#define PIN_XCVR_B5		  (BIT13) /* GPIO2[13] on P5_4 */
+#define PIN_XCVR_B6		  (BIT14) /* GPIO2[14] on P5_5 */
+#define PIN_XCVR_B7		  (BIT15) /* GPIO2[15] on P5_6 */
+#define PORT_XCVR_B	  	  (GPIO2)
+#endif
+
+#define PIN_AD_CS  (BIT7)  /* GPIO2[7] on P5_7 */
+#define PORT_AD_CS (GPIO2) /* PORT for AD_CS */
+
+#ifdef JELLYBEAN
+#define PIN_MIXER_ENX     (BIT8)  /* GPIO3[8] on P7_0 */
+#define PORT_MIXER_ENX    (GPIO3)
+#define PIN_MIXER_SCLK    (BIT9)  /* GPIO3[9] on P7_1 */
+#define PORT_MIXER_SCLK   (GPIO3)
+#define PIN_MIXER_SDATA   (BIT10) /* GPIO3[10] on P7_2 */
+#define PORT_MIXER_SDATA  (GPIO3)
+#define PIN_MIXER_RESETX  (BIT11) /* GPIO3[11] on P7_3 */
+#define PORT_MIXER_RESETX (GPIO3)
+#endif
+#if (defined JAWBREAKER || defined HACKRF_ONE)
+#define PIN_MIXER_ENX     (BIT13) /* GPIO2[13] on P5_4 */
+#define PORT_MIXER_ENX    (GPIO2)
+#define PIN_MIXER_SCLK    (BIT6)  /* GPIO5[6] on P2_6 */
+#define PORT_MIXER_SCLK   (GPIO5)
+#define PIN_MIXER_SDATA   (BIT3)  /* GPIO3[3] on P6_4 */
+#define PORT_MIXER_SDATA  (GPIO3)
+#define PIN_MIXER_RESETX  (BIT14) /* GPIO2[14] on P5_5 */
+#define PORT_MIXER_RESETX (GPIO2)
+#endif
+
+#ifdef JAWBREAKER
+#define PIN_RF_LDO_ENABLE  (BIT9)  /* GPIO2[9] on P5_0 */
+#define PORT_RF_LDO_ENABLE (GPIO2) /* PORT for RF_LDO_ENABLE */
+#endif
+
+#ifdef HACKRF_ONE
+#define PIN_NO_VAA_ENABLE  (BIT9)  /* GPIO2[9] on P5_0 */
+#define PORT_NO_VAA_ENABLE (GPIO2) /* PORT for NO_VAA_ENABLE */
+#endif
+
+#define PIN_FLASH_HOLD (BIT14) /* GPIO1[14] on P3_4 */
+#define PIN_FLASH_WP   (BIT15) /* GPIO1[15] on P3_5 */
+#define PORT_FLASH     (GPIO1)
+#define PIN_SSP0_SSEL  (BIT11) /* GPIO5[11] on P3_8 */
+#define PORT_SSP0_SSEL (GPIO5)
+
+/* RF switch control */
+#ifdef HACKRF_ONE
+#define PIN_HP              (GPIOPIN0)  /* GPIO2[0] on P4_0 */
+#define PORT_HP             (GPIO2)
+#define PIN_LP              (GPIOPIN10) /* GPIO2[10] on P5_1 */
+#define PORT_LP             (GPIO2)
+#define PIN_TX_MIX_BP       (GPIOPIN11) /* GPIO2[11] on P5_2 */
+#define PORT_TX_MIX_BP      (GPIO2)
+#define PIN_NO_MIX_BYPASS   (GPIOPIN0)  /* GPIO1[0] on P1_7 */
+#define PORT_NO_MIX_BYPASS  (GPIO1)
+#define PIN_RX_MIX_BP       (GPIOPIN12) /* GPIO2[12] on P5_3 */
+#define PORT_RX_MIX_BP      (GPIO2)
+#define PIN_TX_AMP          (GPIOPIN15) /* GPIO2[15] on P5_6 */
+#define PORT_TX_AMP         (GPIO2)
+#define PIN_TX              (GPIOPIN15) /* GPIO5[15] on P6_7 */
+#define PORT_TX             (GPIO5)
+#define PIN_MIX_BYPASS      (GPIOPIN16) /* GPIO5[16] on P6_8 */
+#define PORT_MIX_BYPASS     (GPIO5)
+#define PIN_RX              (GPIOPIN5)  /* GPIO5[5] on P2_5 */
+#define PORT_RX             (GPIO5)
+#define PIN_NO_TX_AMP_PWR   (GPIOPIN5)  /* GPIO3[5] on P6_9 */
+#define PORT_NO_TX_AMP_PWR  (GPIO3)
+#define PIN_AMP_BYPASS      (GPIOPIN14) /* GPIO0[14] on P2_10 */
+#define PORT_AMP_BYPASS     (GPIO0)
+#define PIN_RX_AMP          (GPIOPIN11) /* GPIO1[11] on P2_11 */
+#define PORT_RX_AMP         (GPIO1)
+#define PIN_NO_RX_AMP_PWR   (GPIOPIN12) /* GPIO1[12] on P2_12 */
+#define PORT_NO_RX_AMP_PWR  (GPIO1)
+#endif
+
+/* GPIO Input */
+#define PIN_BOOT0   (BIT8)  /* GPIO0[8] on P1_1 */
+#define PIN_BOOT1   (BIT9)  /* GPIO0[9] on P1_2 */
+#define PIN_BOOT2   (BIT7)  /* GPIO5[7] on P2_8 */
+#define PIN_BOOT3   (BIT10) /* GPIO1[10] on P2_9 */
+
+/* CPLD JTAG interface GPIO pins */
+#define PIN_CPLD_TDO    (GPIOPIN18)
+#define PORT_CPLD_TDO   (GPIO5)
+#define PIN_CPLD_TCK    (GPIOPIN0)
+#define PORT_CPLD_TCK   (GPIO3)
+#ifdef HACKRF_ONE
+#define PIN_CPLD_TMS    (GPIOPIN4)
+#define PORT_CPLD_TMS   (GPIO3)
+#define PIN_CPLD_TDI    (GPIOPIN1)
+#define PORT_CPLD_TDI   (GPIO3)
+#else
+#define PIN_CPLD_TMS    (GPIOPIN1)
+#define PORT_CPLD_TMS   (GPIO3)
+#define PIN_CPLD_TDI    (GPIOPIN4)
+#define PORT_CPLD_TDI   (GPIO3)
+#endif
+ 
+/* Read GPIO Pin */
+#define GPIO_STATE(port, pin) ((GPIO_PIN(port) & (pin)) == (pin))
+#define BOOT0_STATE       GPIO_STATE(GPIO0, PIN_BOOT0)
+#define BOOT1_STATE       GPIO_STATE(GPIO0, PIN_BOOT1)
+#define BOOT2_STATE       GPIO_STATE(GPIO5, PIN_BOOT2)
+#define BOOT3_STATE       GPIO_STATE(GPIO1, PIN_BOOT3)
+#define MIXER_SDATA_STATE GPIO_STATE(PORT_MIXER_SDATA, PIN_MIXER_SDATA)
+#define CPLD_TDO_STATE    GPIO_STATE(PORT_CPLD_TDO, PIN_CPLD_TDO)
+
+/* TODO add other Pins */
+
+typedef enum {
+	TRANSCEIVER_MODE_OFF = 0,
+	TRANSCEIVER_MODE_RX = 1,
+	TRANSCEIVER_MODE_TX = 2,
+	TRANSCEIVER_MODE_SS = 3,
+	TRANSCEIVER_MODE_CPLD_UPDATE = 4
+} transceiver_mode_t;
+
+void delay(uint32_t duration);
+
+void cpu_clock_init(void);
+void cpu_clock_pll1_low_speed(void);
+void cpu_clock_pll1_max_speed(void);
+void ssp1_init(void);
+void ssp1_set_mode_max2837(void);
+void ssp1_set_mode_max5864(void);
+
+void pin_setup(void);
+
+void enable_1v8_power(void);
+void disable_1v8_power(void);
+
+bool sample_rate_frac_set(uint32_t rate_num, uint32_t rate_denom);
+bool sample_rate_set(const uint32_t sampling_rate_hz);
+bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz);
+
+#ifdef HACKRF_ONE
+void enable_rf_power(void);
+void disable_rf_power(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HACKRF_CORE_H */

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/m0_bin.s.cmake

@@ -0,0 +1,23 @@
+# Copyright 2013 Jared Boone <jared@sharebrained.com>
+#
+# This file is part of HackRF.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+
+	.data
+	.section	.m0_bin, "ax"
+	
+	.incbin		"${PROJECT_NAME}_m0.bin"

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/m0_sleep.c

@@ -0,0 +1,26 @@
+/*
+ * Copyright 2013 Jared Boone <jared@sharebrained.com>
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+int main() {
+	while(1) {
+		
+	}
+}

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/max2837.c

@@ -0,0 +1,507 @@
+/*
+ * 'gcc -DTEST -DDEBUG -O2 -o test max2837.c' prints out what test
+ * program would do if it had a real spi library
+ *
+ * 'gcc -DTEST -DBUS_PIRATE -O2 -o test max2837.c' prints out bus
+ * pirate commands to do the same thing.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include "max2837.h"
+#include "max2837_regs.def" // private register def macros
+
+#if (defined DEBUG || defined BUS_PIRATE)
+#include <stdio.h>
+#define LOG printf
+#else
+#define LOG(x,...)
+#include <libopencm3/lpc43xx/ssp.h>
+#include <libopencm3/lpc43xx/scu.h>
+#include <libopencm3/lpc43xx/gpio.h>
+#include "hackrf_core.h"
+#endif
+
+/* Default register values. */
+static uint16_t max2837_regs_default[MAX2837_NUM_REGS] = { 
+	0x150,   /* 0 */
+	0x002,   /* 1 */
+	0x1f4,   /* 2 */
+	0x1b9,   /* 3 */
+	0x00a,   /* 4 */
+	0x080,   /* 5 */
+	0x006,   /* 6 */
+	0x000,   /* 7 */
+	0x080,   /* 8 */
+	0x018,   /* 9 */
+	0x058,   /* 10 */
+	0x016,   /* 11 */
+	0x24f,   /* 12 */
+	0x150,   /* 13 */
+	0x1c5,   /* 14 */
+	0x081,   /* 15 */
+	0x01c,   /* 16 */
+	0x155,   /* 17 */
+	0x155,   /* 18 */
+	0x153,   /* 19 */
+	0x241,   /* 20 */
+	/*
+	 * Charge Pump Common Mode Enable bit (0) of register 21 must be set or TX
+	 * does not work.  Page 1 of the SPI doc says not to set it (0x02c), but
+	 * page 21 says it should be set by default (0x02d).
+	 */
+	0x02d,   /* 21 */
+	0x1a9,   /* 22 */
+	0x24f,   /* 23 */
+	0x180,   /* 24 */
+	0x100,   /* 25 */
+	0x3ca,   /* 26 */
+	0x3e3,   /* 27 */
+	0x0c0,   /* 28 */
+	0x3f0,   /* 29 */
+	0x080,   /* 30 */
+	0x000 }; /* 31 */
+
+uint16_t max2837_regs[MAX2837_NUM_REGS];
+
+/* Mark all regsisters dirty so all will be written at init. */
+uint32_t max2837_regs_dirty = 0xffffffff;
+
+/* Set up all registers according to defaults specified in docs. */
+void max2837_init(void)
+{
+	LOG("# max2837_init\n");
+	memcpy(max2837_regs, max2837_regs_default, sizeof(max2837_regs));
+	max2837_regs_dirty = 0xffffffff;
+
+	/* Write default register values to chip. */
+	max2837_regs_commit();
+}
+
+/*
+ * Set up pins for GPIO and SPI control, configure SSP peripheral for SPI, and
+ * set our own default register configuration.
+ */
+void max2837_setup(void)
+{
+	LOG("# max2837_setup\n");
+#if !defined TEST
+	/* Configure XCVR_CTL GPIO pins. */
+#ifdef JELLYBEAN
+	scu_pinmux(SCU_XCVR_RXHP, SCU_GPIO_FAST);
+	scu_pinmux(SCU_XCVR_B1, SCU_GPIO_FAST);
+	scu_pinmux(SCU_XCVR_B2, SCU_GPIO_FAST);
+	scu_pinmux(SCU_XCVR_B3, SCU_GPIO_FAST);
+	scu_pinmux(SCU_XCVR_B4, SCU_GPIO_FAST);
+	scu_pinmux(SCU_XCVR_B5, SCU_GPIO_FAST);
+	scu_pinmux(SCU_XCVR_B6, SCU_GPIO_FAST);
+	scu_pinmux(SCU_XCVR_B7, SCU_GPIO_FAST);
+#endif
+	scu_pinmux(SCU_XCVR_ENABLE, SCU_GPIO_FAST);
+	scu_pinmux(SCU_XCVR_RXENABLE, SCU_GPIO_FAST);
+	scu_pinmux(SCU_XCVR_TXENABLE, SCU_GPIO_FAST);
+
+	/* Set GPIO pins as outputs. */
+	GPIO2_DIR |= (PIN_XCVR_ENABLE | PIN_XCVR_RXENABLE | PIN_XCVR_TXENABLE);
+#ifdef JELLYBEAN
+	GPIO_DIR(PORT_XCVR_RXHP) |= PIN_XCVR_RXHP;
+	GPIO_DIR(PORT_XCVR_B) |=
+		  PIN_XCVR_B1
+		| PIN_XCVR_B2
+		| PIN_XCVR_B3
+		| PIN_XCVR_B4
+		| PIN_XCVR_B5
+		| PIN_XCVR_B6
+		| PIN_XCVR_B7
+		;
+#endif
+
+	max2837_mode_shutdown();
+#ifdef JELLYBEAN
+	gpio_set(PORT_XCVR_RXHP, PIN_XCVR_RXHP);
+	gpio_set(PORT_XCVR_B,
+		  PIN_XCVR_B1
+		| PIN_XCVR_B2
+		| PIN_XCVR_B3
+		| PIN_XCVR_B4
+		| PIN_XCVR_B5
+		| PIN_XCVR_B6
+		| PIN_XCVR_B7
+	);
+#endif
+#endif
+
+	max2837_init();
+	LOG("# max2837_init done\n");
+
+	/* Use SPI control instead of B1-B7 pins for gain settings. */
+	set_MAX2837_TXVGA_GAIN_SPI_EN(1);
+	set_MAX2837_TXVGA_GAIN_MSB_SPI_EN(1);
+	//set_MAX2837_TXVGA_GAIN(0x3f); /* maximum attenuation */
+	set_MAX2837_TXVGA_GAIN(0x00); /* minimum attenuation */
+	set_MAX2837_VGAMUX_enable(1);
+	set_MAX2837_VGA_EN(1);
+	set_MAX2837_HPC_RXGAIN_EN(0);
+	set_MAX2837_HPC_STOP(MAX2837_STOP_1K);
+	set_MAX2837_LNAgain_SPI_EN(1);
+	set_MAX2837_LNAgain(MAX2837_LNAgain_MAX); /* maximum gain */
+	set_MAX2837_VGAgain_SPI_EN(1);
+	set_MAX2837_VGA(0x18); /* reasonable gain for noisy 2.4GHz environment */
+
+	/* maximum rx output common-mode voltage */
+	set_MAX2837_BUFF_VCM(MAX2837_BUFF_VCM_1_25);
+
+	/* configure baseband filter for 8 MHz TX */
+	set_MAX2837_LPF_EN(1);
+	set_MAX2837_ModeCtrl(MAX2837_ModeCtrl_RxLPF);
+	set_MAX2837_FT(MAX2837_FT_5M);
+
+	max2837_regs_commit();
+}
+
+/* SPI register read. */
+uint16_t max2837_spi_read(uint8_t r) {
+	gpio_clear(PORT_XCVR_CS, PIN_XCVR_CS);
+	const uint16_t value = ssp_transfer(SSP1_NUM, (uint16_t)((1 << 15) | (r << 10)));
+	gpio_set(PORT_XCVR_CS, PIN_XCVR_CS);
+	return value & 0x3ff;
+}
+
+/* SPI register write */
+void max2837_spi_write(uint8_t r, uint16_t v) {
+
+#ifdef BUS_PIRATE
+	LOG("{0x%02x 0x%02x]\n", 0x00 | ((uint16_t)r<<2) | ((v>>8) & 0x3),
+	    v & 0xff);
+#elif DEBUG
+	LOG("0x%03x -> reg%d\n", v, r);
+#else
+	gpio_clear(PORT_XCVR_CS, PIN_XCVR_CS);
+	ssp_transfer(SSP1_NUM, (uint16_t)((r << 10) | (v & 0x3ff)));
+	gpio_set(PORT_XCVR_CS, PIN_XCVR_CS);
+#endif
+}
+
+uint16_t max2837_reg_read(uint8_t r)
+{
+	if ((max2837_regs_dirty >> r) & 0x1) {
+		max2837_regs[r] = max2837_spi_read(r);
+	};
+	return max2837_regs[r];
+}
+
+void max2837_reg_write(uint8_t r, uint16_t v)
+{
+	max2837_regs[r] = v;
+	max2837_spi_write(r, v);
+	MAX2837_REG_SET_CLEAN(r);
+}
+
+/* This functions should not be needed, and might be confusing. DELETE. */
+void max2837_regs_read(void)
+{
+	;
+}
+
+static inline void max2837_reg_commit(uint8_t r)
+{
+	max2837_reg_write(r,max2837_regs[r]);
+}
+
+void max2837_regs_commit(void)
+{
+	int r;
+	for(r = 0; r < MAX2837_NUM_REGS; r++) {
+		if ((max2837_regs_dirty >> r) & 0x1) {
+			max2837_reg_commit(r);
+		}
+	}
+}
+
+void max2837_mode_shutdown(void) {
+	/* All circuit blocks are powered down, except the 4-wire serial bus
+	 * and its internal programmable registers.
+	 */
+	gpio_clear(PORT_XCVR_ENABLE,
+			(PIN_XCVR_ENABLE | PIN_XCVR_RXENABLE | PIN_XCVR_TXENABLE));
+}
+
+void max2837_mode_standby(void) {
+	/* Used to enable the frequency synthesizer block while the rest of the
+	 * device is powered down. In this mode, PLL, VCO, and LO generator
+	 * are on, so that Tx or Rx modes can be quickly enabled from this mode.
+	 * These and other blocks can be selectively enabled in this mode.
+	 */
+	gpio_clear(PORT_XCVR_ENABLE, (PIN_XCVR_RXENABLE | PIN_XCVR_TXENABLE));
+	gpio_set(PORT_XCVR_ENABLE, PIN_XCVR_ENABLE);
+}
+
+void max2837_mode_tx(void) {
+	/* All Tx circuit blocks are powered on. The external PA is powered on
+	 * after a programmable delay using the on-chip PA bias DAC. The slow-
+	 * charging Rx circuits are in a precharged “idle-off” state for fast
+	 * Tx-to-Rx turnaround time.
+	 */
+	gpio_clear(PORT_XCVR_ENABLE, PIN_XCVR_RXENABLE);
+	gpio_set(PORT_XCVR_ENABLE,
+			(PIN_XCVR_ENABLE | PIN_XCVR_TXENABLE));
+}
+
+void max2837_mode_rx(void) {
+	/* All Rx circuit blocks are powered on and active. Antenna signal is
+	 * applied; RF is downconverted, filtered, and buffered at Rx BB I and Q
+	 * outputs. The slow- charging Tx circuits are in a precharged “idle-off”
+	 * state for fast Rx-to-Tx turnaround time.
+	 */
+	gpio_clear(PORT_XCVR_ENABLE, PIN_XCVR_TXENABLE);
+	gpio_set(PORT_XCVR_ENABLE,
+			(PIN_XCVR_ENABLE | PIN_XCVR_RXENABLE));
+}
+
+max2837_mode_t max2837_mode(void) {
+	if( gpio_get(PORT_XCVR_ENABLE, PIN_XCVR_ENABLE) ) {
+		if( gpio_get(PORT_XCVR_ENABLE, PIN_XCVR_TXENABLE) ) {
+			return MAX2837_MODE_TX;
+		} else if( gpio_get(PORT_XCVR_ENABLE, PIN_XCVR_RXENABLE) ) {
+			return MAX2837_MODE_RX;
+		} else {
+			return MAX2837_MODE_STANDBY;
+		}
+	} else {
+		return MAX2837_MODE_SHUTDOWN;
+	}
+}
+
+void max2837_set_mode(const max2837_mode_t new_mode) {
+	switch(new_mode) {
+	case MAX2837_MODE_SHUTDOWN:
+		max2837_mode_shutdown();
+		break;
+		
+	case MAX2837_MODE_STANDBY:
+		max2837_mode_standby();
+		break;
+		
+	case MAX2837_MODE_TX:
+		max2837_mode_tx();
+		break;
+
+	case MAX2837_MODE_RX:
+		max2837_mode_rx();
+		break;
+		
+	default:
+		break;
+	}
+}
+
+void max2837_start(void)
+{
+	LOG("# max2837_start\n");
+	set_MAX2837_EN_SPI(1);
+	max2837_regs_commit();
+#if !defined TEST
+	max2837_mode_standby();
+#endif
+}
+
+void max2837_tx(void)
+{
+	LOG("# max2837_tx\n");
+#if !defined TEST
+
+	set_MAX2837_ModeCtrl(MAX2837_ModeCtrl_TxLPF);
+	max2837_regs_commit();
+	max2837_mode_tx();
+#endif
+}
+
+void max2837_rx(void)
+{
+	LOG("# max2837_rx\n");
+
+	set_MAX2837_ModeCtrl(MAX2837_ModeCtrl_RxLPF);
+	max2837_regs_commit();
+
+#if !defined TEST
+	max2837_mode_rx();
+#endif
+}
+
+void max2837_stop(void)
+{
+	LOG("# max2837_stop\n");
+	set_MAX2837_EN_SPI(0);
+	max2837_regs_commit();
+#if !defined TEST
+	max2837_mode_shutdown();
+#endif
+}
+
+void max2837_set_frequency(uint32_t freq)
+{
+	uint8_t band;
+	uint8_t lna_band;
+	uint32_t div_frac;
+	uint32_t div_int;
+	uint32_t div_rem;
+	uint32_t div_cmp;
+	int i;
+
+	/* Select band. Allow tuning outside specified bands. */
+	if (freq < 2400000000U) {
+		band = MAX2837_LOGEN_BSW_2_3;
+		lna_band = MAX2837_LNAband_2_4;
+	}
+	else if (freq < 2500000000U) {
+		band = MAX2837_LOGEN_BSW_2_4;
+		lna_band = MAX2837_LNAband_2_4;
+	}
+	else if (freq < 2600000000U) {
+		band = MAX2837_LOGEN_BSW_2_5;
+		lna_band = MAX2837_LNAband_2_6;
+	}
+	else {
+		band = MAX2837_LOGEN_BSW_2_6;
+		lna_band = MAX2837_LNAband_2_6;
+	}
+
+	LOG("# max2837_set_frequency %ld, band %d, lna band %d\n",
+	    freq, band, lna_band);
+
+	/* ASSUME 40MHz PLL. Ratio = F*(4/3)/40,000,000 = F/30,000,000 */
+	div_int = freq / 30000000;
+	div_rem = freq % 30000000;
+	div_frac = 0;
+	div_cmp = 30000000;
+	for( i = 0; i < 20; i++) {
+		div_frac <<= 1;
+		div_cmp >>= 1;
+		if (div_rem > div_cmp) {
+			div_frac |= 0x1;
+			div_rem -= div_cmp;
+		}
+	}
+	LOG("# int %ld, frac %ld\n", div_int, div_frac);
+
+	/* Band settings */
+	set_MAX2837_LOGEN_BSW(band);
+	set_MAX2837_LNAband(lna_band);
+
+	/* Write order matters here, so commit INT and FRAC_HI before
+	 * committing FRAC_LO, which is the trigger for VCO
+	 * auto-select. TODO - it's cleaner this way, but it would be
+	 * faster to explicitly commit the registers explicitly so the
+	 * dirty bits aren't scanned twice. */
+	set_MAX2837_SYN_INT(div_int);
+	set_MAX2837_SYN_FRAC_HI((div_frac >> 10) & 0x3ff);
+	max2837_regs_commit();
+	set_MAX2837_SYN_FRAC_LO(div_frac & 0x3ff);
+	max2837_regs_commit();
+}
+
+typedef struct {
+	uint32_t bandwidth_hz;
+	uint32_t ft;
+} max2837_ft_t;
+
+static const max2837_ft_t max2837_ft[] = {
+	{  1750000, MAX2837_FT_1_75M },
+	{  2500000, MAX2837_FT_2_5M },
+	{  3500000, MAX2837_FT_3_5M },
+	{  5000000, MAX2837_FT_5M },
+	{  5500000, MAX2837_FT_5_5M },
+	{  6000000, MAX2837_FT_6M },
+	{  7000000, MAX2837_FT_7M },
+	{  8000000, MAX2837_FT_8M },
+	{  9000000, MAX2837_FT_9M },
+	{ 10000000, MAX2837_FT_10M },
+	{ 12000000, MAX2837_FT_12M },
+	{ 14000000, MAX2837_FT_14M },
+	{ 15000000, MAX2837_FT_15M },
+	{ 20000000, MAX2837_FT_20M },
+	{ 24000000, MAX2837_FT_24M },
+	{ 28000000, MAX2837_FT_28M },
+	{        0, 0 },
+};
+
+bool max2837_set_lpf_bandwidth(const uint32_t bandwidth_hz) {
+	const max2837_ft_t* p = max2837_ft;
+	while( p->bandwidth_hz != 0 ) {
+		if( p->bandwidth_hz >= bandwidth_hz ) {
+			break;
+		}
+		p++;
+	}
+	
+	if( p->bandwidth_hz != 0 ) {
+		set_MAX2837_FT(p->ft);
+		max2837_regs_commit();
+		return true;
+	} else {
+		return false;
+	}
+}
+
+bool max2837_set_lna_gain(const uint32_t gain_db) {
+	uint16_t val;
+	switch(gain_db){
+		case 40:
+			val = MAX2837_LNAgain_MAX;
+			break;
+		case 32:
+			val = MAX2837_LNAgain_M8;
+			break;
+		case 24:
+			val = MAX2837_LNAgain_M16;
+			break;
+		case 16:
+			val = MAX2837_LNAgain_M24;
+			break;
+		case 8:
+			val = MAX2837_LNAgain_M32;
+			break;
+		case 0:
+			val = MAX2837_LNAgain_M40;
+			break;
+		default:
+			return false;
+	}
+	set_MAX2837_LNAgain(val);
+	max2837_reg_commit(1);
+	return true;
+}
+
+bool max2837_set_vga_gain(const uint32_t gain_db) {
+	if( (gain_db & 0x1) || gain_db > 62)/* 0b11111*2 */
+		return false;
+		
+	set_MAX2837_VGA( 31-(gain_db >> 1) );
+	max2837_reg_commit(5);
+	return true;
+}
+
+bool max2837_set_txvga_gain(const uint32_t gain_db) {
+	uint16_t val=0;
+	if(gain_db <16){
+		val = 31-gain_db;
+		val |= (1 << 5); // bit6: 16db
+	} else{
+		val = 31-(gain_db-16);
+	}
+	
+	set_MAX2837_TXVGA_GAIN(val);
+	max2837_reg_commit(29);
+	return true;
+}
+
+#ifdef TEST
+int main(int ac, char **av)
+{
+	max2837_setup();
+	max2837_set_frequency(2441000000);
+	max2837_start();
+	max2837_tx();
+	max2837_stop();
+}
+#endif //TEST

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/max2837.h

@@ -0,0 +1,70 @@
+#ifndef __MAX2837_H
+#define __MAX2837_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/* TODO - make this a private header for max2837.c only, make new max2837.h */
+
+/* 32 registers, each containing 10 bits of data. */
+#define MAX2837_NUM_REGS 32
+#define MAX2837_DATA_REGS_MAX_VALUE 1024
+
+/* TODO - these externs will be local to max2837.c ... don't define here? */
+extern uint16_t max2837_regs[MAX2837_NUM_REGS];
+extern uint32_t max2837_regs_dirty;
+
+#define MAX2837_REG_SET_CLEAN(r) max2837_regs_dirty &= ~(1UL<<r)
+#define MAX2837_REG_SET_DIRTY(r) max2837_regs_dirty |= (1UL<<r)
+
+/* Initialize chip. */
+extern void max2837_init(void);
+extern void max2837_setup(void);
+
+/* Read a register via SPI. Save a copy to memory and return
+ * value. Mark clean. */
+extern uint16_t max2837_reg_read(uint8_t r);
+
+/* Write value to register via SPI and save a copy to memory. Mark
+ * clean. */
+extern void max2837_reg_write(uint8_t r, uint16_t v);
+
+/* Read all registers from chip and copy to memory. Mark all clean. */
+extern void max2837_regs_read(void);
+
+/* Write all dirty registers via SPI from memory. Mark all clean. Some
+ * operations require registers to be written in a certain order. Use
+ * provided routines for those operations. */
+extern void max2837_regs_commit(void);
+
+typedef enum {
+	MAX2837_MODE_SHUTDOWN,
+	MAX2837_MODE_STANDBY,
+	MAX2837_MODE_TX,
+	MAX2837_MODE_RX
+} max2837_mode_t;
+
+void max2837_mode_shutdown(void);
+void max2837_mode_standby(void);
+void max2837_mode_tx(void);
+void max2837_mode_rx(void);
+
+max2837_mode_t max2837_mode(void);
+void max2837_set_mode(const max2837_mode_t new_mode);
+
+/* Turn on/off all chip functions. Does not control oscillator and CLKOUT */
+extern void max2837_start(void);
+extern void max2837_stop(void);
+
+/* Set frequency in Hz. Frequency setting is a multi-step function
+ * where order of register writes matters. */
+extern void max2837_set_frequency(uint32_t freq);
+bool max2837_set_lpf_bandwidth(const uint32_t bandwidth_hz);
+bool max2837_set_lna_gain(const uint32_t gain_db);
+bool max2837_set_vga_gain(const uint32_t gain_db);
+bool max2837_set_txvga_gain(const uint32_t gain_db);
+	
+extern void max2837_tx(void);
+extern void max2837_rx(void);
+
+#endif // __MAX2837_H

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/max2837_regs.def

@@ -0,0 +1,405 @@
+/* -*- mode: c -*- */
+
+#ifndef __MAX2837_REGS_DEF
+#define __MAX2837_REGS_DEF
+
+/* Generate static inline accessors that operate on the global
+ * regs. Done this way to (1) allow defs to be scraped out and used
+ * elsewhere, e.g. in scripts, (2) to avoid dealing with endian
+ * (structs). This may be used in firmware, or on host predefined
+ * register loads. */
+
+/* On set_, register is always set dirty, even if nothing
+ * changed. This makes sure that write that have side effects,
+ * e.g. frequency setting, are not skipped. */
+
+/* n=name, r=regnum, o=offset (bits from LSB), l=length (bits) */
+#define __MREG__(n,r,o,l) \
+static inline uint16_t get_##n(void) { \
+	return (max2837_regs[r] >> (o-l+1)) & ((1<<l)-1);	\
+} \
+static inline void set_##n(uint16_t v) {      \
+	max2837_regs[r] &= ~(((1<<l)-1)<<(o-l+1));  \
+	max2837_regs[r] |= ((v&((1<<l)-1))<<(o-l+1)); \
+	MAX2837_REG_SET_DIRTY(r); \
+}
+
+/* REG 0 */
+__MREG__(MAX2837_LNA_EN,   0,0,1)
+__MREG__(MAX2837_Mixer_EN, 0,1,1)
+__MREG__(MAX2837_RxLO_EN,  0,2,1)
+__MREG__(MAX2837_Lbias,    0,4,2)
+#define MAX2837_Lbias_LOWEST  0
+#define MAX2837_Lbias_NOMINAL 2
+#define MAX2837_Lbias_HIGHEST 3
+__MREG__(MAX2837_Mbias,    0,6,2)
+#define MAX2837_Mbias_LOWEST  0
+#define MAX2837_Mbias_NOMINAL 2
+#define MAX2837_Mbias_HIGHEST 3
+__MREG__(MAX2837_buf,      0,8,2)
+#define MAX2837_buf_LOWEST  0
+#define MAX2837_buf_NOMINAL 2
+#define MAX2837_buf_HIGHEST 3
+__MREG__(MAX2837_LNAband,  0,9,1)
+#define MAX2837_LNAband_2_4 0   // 2.3-2.5 GHz
+#define MAX2837_LNAband_2_6 1   // 2.5-2.7 GHz
+
+/* REG 1 */
+__MREG__(MAX2837_LNAtune,  1,0,1)
+#define MAX2837_LNAtune_NOMINAL 0
+#define MAX2837_LNAtune_DOWN    1
+__MREG__(MAX2837_LNAde_Q,1,1,1)
+#define MAX2837_LNAde_Q_NOMINAL 0
+#define MAX2837_LNAde_Q_2DB     1
+__MREG__(MAX2837_LNAgain,1,4,3)
+#define MAX2837_LNAgain_MAX 0b000 // Pad in 8dB steps, bits reversed
+#define MAX2837_LNAgain_M8  0b100
+#define MAX2837_LNAgain_M16 0b010
+#define MAX2837_LNAgain_M24 0b110
+#define MAX2837_LNAgain_M32 0b011
+#define MAX2837_LNAgain_M40 0b111
+__MREG__(MAX2837_iqerr_trim,1,9,5)
+// 0b00000 = +4.0 degree phase error
+// 0b01111 =  0.0
+// 0b11111 = -4.0
+
+/* REG 2 */
+__MREG__(MAX2837_LPF_EN,2,0,1)
+__MREG__(MAX2837_TxBB_EN,2,1,1)
+__MREG__(MAX2837_ModeCtrl,2,3,2)
+#define MAX2837_ModeCtrl_RxCalibration 0
+#define MAX2837_ModeCtrl_RxLPF         1
+#define MAX2837_ModeCtrl_TxLPF         2
+#define MAX2837_ModeCtrl_LPFTrim       3
+__MREG__(MAX2837_FT,2,7,4)
+#define MAX2837_FT_1_75M 0
+#define MAX2837_FT_2_5M  1
+#define MAX2837_FT_3_5M  2
+#define MAX2837_FT_5M    3
+#define MAX2837_FT_5_5M  4
+#define MAX2837_FT_6M    5
+#define MAX2837_FT_7M    6
+#define MAX2837_FT_8M    7
+#define MAX2837_FT_9M    8
+#define MAX2837_FT_10M   9
+#define MAX2837_FT_12M   10
+#define MAX2837_FT_14M   11
+#define MAX2837_FT_15M   12
+#define MAX2837_FT_20M   13
+#define MAX2837_FT_24M   14
+#define MAX2837_FT_28M   15
+__MREG__(MAX2837_dF,2,9,2)
+#define MAX2837_dF_M10     0b00 // -10%
+#define MAX2837_dF_NOMINAL 0b01
+#define MAX2837_dF_10      0b11 // +10%
+
+/* REG 3 */
+__MREG__(MAX2837_PT_SPI,3,3,4)  // slowest=1111 fastest=0000 nom=1001
+__MREG__(MAX2837_Bqd,3,6,3)     // MSB doubles bias current, lower 2 25% each
+__MREG__(MAX2837_TxRPCM,3,9,3)  // 000=1.00V, 0.05V steps, 111 not allowed
+
+/* REG 4 */
+__MREG__(MAX2837_RP,4,1,2)      // 20% steps, 00=lowest, 11=highest
+__MREG__(MAX2837_TxBuff,4,3,2)  // 25% steps, 00=lowest, 11=highest
+__MREG__(MAX2837_VGA_EN,4,4,1)
+__MREG__(MAX2837_VGAMUX_enable,4,5,1)
+__MREG__(MAX2837_BUFF_Curr,4,7,2) // 250uA + 125uA steps
+__MREG__(MAX2837_BUFF_VCM,4,9,2)  // VGA common mode
+#define MAX2837_BUFF_VCM_0_9  0  // 0.9V
+#define MAX2837_BUFF_VCM_1_0  1  // 1.0V
+#define MAX2837_BUFF_VCM_1_1  2  // 1.1V
+#define MAX2837_BUFF_VCM_1_25 3  // 1.25V
+
+/* REG 5 */
+__MREG__(MAX2837_VGA,5,4,5) // max=00000, attenuation in 2dB steps
+__MREG__(MAX2837_sel_In1_In2,5,5,1)
+#define MAX2837_sel_In1_In2_RXVGA 0
+#define MAX2837_sel_In1_In2_TXAM  1
+__MREG__(MAX2837_turbo15n20,5,6,1)
+__MREG__(MAX2837_VGA_Curr,5,8,2) // 01=default, 00=-33%, 10=+33%, 11=+67%
+__MREG__(MAX2837_fuse_arm,5,9,1)
+
+/* REG 6 */
+__MREG__(MAX2837_RSSI_EN,6,6,1) // enable RSSI
+__MREG__(MAX2837_RSSI_MUX,6,7,1)
+#define MAX2837_RSSI_MUX_RSSI 0
+#define MAX2837_RSSI_MUX_TEMP 1
+__MREG__(MAX2837_RSSI_MODE,6,8,1)    // set to override RXHP pin
+__MREG__(MAX2837_LPF_MODE_SEL,6,9,1) // set to enable mode in reg 2 ModeCtrl
+
+/* REG 7 is R/O */
+// D4:0 ts_adc (temp sensor)
+// D9:5 zeros or test outputs
+
+/* REG 8 */
+__MREG__(MAX2837_LNAgain_SPI_EN,8,0,1)  // set to override pin control of LNA
+__MREG__(MAX2837_VGAgain_SPI_EN,8,1,1)  // set to override pin control of VGA
+__MREG__(MAX2837_EN_Bias_Trim,8,2,1)    // route bias current to bondpad
+__MREG__(MAX2837_BIAS_TRIM_SPI,8,7,5)   // down=00000, up=11111, nom=10000
+__MREG__(MAX2837_BIAS_TRIM_CNTRL,8,8,1) // enable BIAS_TRIM_SPI value
+__MREG__(MAX2837_RX_IQERR_SPI_EN,8,9,1) // ???
+
+/* REG 9 */
+__MREG__(MAX2837_ts_adc_trigger,9,0,1)  // temp sensor trigger (one shot)
+__MREG__(MAX2837_ts_en,9,1,1)           // temp sensor enable (before trigger)
+__MREG__(MAX2837_LPFtrim_SPI_EN,9,2,1)
+__MREG__(MAX2837_DOUT_DRVH,9,3,1)
+#define MAX2837_DOUT_DRVH_1X 0
+#define MAX2837_DOUT_DRVH_4X 1
+__MREG__(MAX2837_DOUT_PU,9,4,1) // set to enable CMOS PU (default), else OD
+__MREG__(MAX2837_DOUT_SEL,9,7,3)
+#define MAX2837_DOUT_SEL_SPI             0 // default, SPI comm
+#define MAX2837_DOUT_SEL_PLL_LOCK_DETECT 1
+#define MAX2837_DOUT_SEL_VAS_TEST_OUT    2
+#define MAX2837_DOUT_SEL_HPFSM_TEST_OUT  3
+#define MAX2837_DOUT_SEL_LOGEN_TRIM_OUT  4
+#define MAX2837_DOUT_SEL_RX_FUSE_GASKET  5
+#define MAX2837_DOUT_SEL_TX_FUSE_GASKET  6
+#define MAX2837_DOUT_SEL_ZERO            7
+__MREG__(MAX2837_fuse_sh,9,8,1)         // ???
+__MREG__(MAX2837_fuse_burn_gkt,9,9,1)   // enable (don't)
+
+/* REG 10 */
+__MREG__(MAX2837_TXCAL_GAIN,10,2,2)     // 00=default, steps of +10dB
+__MREG__(MAX2837_TXCAL_V2I_FILT,10,5,3) // 000=+12%, 111=-16%, 011=default
+__MREG__(MAX2837_TX_BIAS_ADJ,10,7,2)    // 00=-10%, 01=default, 10=+10%, 11=+20%
+
+/* REG 11 */
+__MREG__(MAX2837_AMD_SPI_EN,11,0,1)     // enable AM detector
+__MREG__(MAX2837_TXMXR_V2I_GAIN,11,4,4) // 0000=max, steps of -0.5dB
+
+/* REG 12 */
+__MREG__(MAX2837_HPC_10M,12,1,2)        // steps of 0.4uS (0.0-1.2)
+__MREG__(MAX2837_HPC_10M_GAIN,12,3,2)   // steps of 0.4uS (0.0-1.2)
+__MREG__(MAX2837_HPC_600K,12,6,3)       // steps of 0.8uS (0.0-4.8), 7=stay 1
+__MREG__(MAX2837_HPC_600K_GAIN,12,9,3)  // steps of 0.8uS (0.0-4.8), 7=stay 1
+
+/* REG 13 */
+__MREG__(MAX2837_HPC_100K,13,1,2)       // steps of 3.2uS (0.0-9.6)
+__MREG__(MAX2837_HPC_100K_GAIN,13,3,2)  // steps of 3.2uS (0.0-9.6)
+__MREG__(MAX2837_HPC_30K,13,5,2)        // steps of 3.2uS (0.0-9.6)
+__MREG__(MAX2837_HPC_30K_GAIN,13,7,2)   // steps of 3.2uS (0.0-9.6)
+__MREG__(MAX2837_HPC_1K,13,9,2)         // steps of 3.2uS (0.0-9.6)
+
+/* REG 14 */
+__MREG__(MAX2837_HPC_1K_GAIN,14,1,2)    // steps of 3.2uS (0.0-9.6)
+__MREG__(MAX2837_HPC_DELAY,14,3,2)      // steps of 0.2uS (0.0-0.6)
+__MREG__(MAX2837_HPC_STOP,14,5,2)
+#define MAX2837_STOP_100  0
+#define MAX2837_STOP_1K   1
+#define MAX2837_STOP_30K  2
+#define MAX2837_STOP_100K 3
+__MREG__(MAX2837_HPC_STOP_M2,14,7,2)
+#define MAX2837_STOP_M2_1K   0
+#define MAX2837_STOP_M2_30K  1
+#define MAX2837_STOP_M2_100K 2
+#define MAX2837_STOP_M2_600K 3
+__MREG__(MAX2837_HPC_RXGAIN_EN,14,8,1) // RXVGA HPFSM re-triggered by B7 & B6
+__MREG__(MAX2837_HPC_MODE,14,9,1)      // use RXHP
+
+/* REG 15 */
+__MREG__(MAX2837_HPC_DIVH,15,0,1)
+#define MAX2837_HPC_DIVH_20M 0
+#define MAX2837_HPC_DIVH_40M 1
+__MREG__(MAX2837_HPC_TST,15,5,5)       // filter test modes ... see doc
+__MREG__(MAX2837_HPC_SEQ_BYP,15,6,1)   // set to bypass programmed sequence
+__MREG__(MAX2837_DOUT_CSB_SEL,15,7,1)  // set to tri state DOUT when CSB high
+
+/* REG 16 */
+__MREG__(MAX2837_EN_SPI,16,0,1)        // enable overall chip
+__MREG__(MAX2837_CAL_SPI,16,1,1)       // enable calibration mode
+__MREG__(MAX2837_LOGEN_SPI_EN,16,2,1)  // ???
+__MREG__(MAX2837_SYN_SPI_EN,16,3,1)    // enable synthesizer
+__MREG__(MAX2837_VAS_SPI_EN,16,4,1)    // enable VCO autoselect
+__MREG__(MAX2837_PADRV_SPI_EN,16,5,1)  // enable power amp
+__MREG__(MAX2837_PADAC_SPI_EN,16,6,1)  // enable power amp bias DAC always
+__MREG__(MAX2837_PADAC_TX_EN,16,7,1)   // enable power amp bias only if TX pin
+__MREG__(MAX2837_TXMX_SPI_EN,16,8,1)   // enable TX mixer
+__MREG__(MAX2837_TXLO_SPI_EN,16,9,1)   // enable TX LO
+
+/* REG 17 */
+__MREG__(MAX2837_SYN_FRAC_LO,17,9,10)
+
+/* REG 18 */
+__MREG__(MAX2837_SYN_FRAC_HI,18,9,10)
+
+/* REG 19 */
+__MREG__(MAX2837_SYN_INT,19,7,8)
+__MREG__(MAX2837_LOGEN_BSW,19,9,2)
+#define MAX2837_LOGEN_BSW_2_3 0 // 2300 - <2400 MHz
+#define MAX2837_LOGEN_BSW_2_4 1 // 2400 - <2500 MHz
+#define MAX2837_LOGEN_BSW_2_5 2 // 2500 - <2600 MHz
+#define MAX2837_LOGEN_BSW_2_6 3 // 2600 - <2700 MHz
+
+/* REG 20 */
+__MREG__(MAX2837_SYN_MODE,20,0,1)
+#define MAX2837_SYN_MODE_INTEGER    0
+#define MAX2837_SYN_MODE_FRACTIONAL 1
+__MREG__(MAX2837_SYN_REF_DIV,20,2,2)
+#define MAX2837_SYN_REF_DIV_1 0
+#define MAX2837_SYN_REF_DIV_2 1
+#define MAX2837_SYN_REF_DIV_4 2
+#define MAX2837_SYN_REF_DIV_8 3
+__MREG__(MAX2837_SYN_CURRENT_,20,4,2)
+#define MAX2837_SYN_CURRENT_3_2_DIFF   0 // 3.2mA differential
+#define MAX2837_SYN_CURRENT_1_6_DIFF   1 // 1.6mA differential
+#define MAX2837_SYN_CURRENT_1_6_SINGLE 2 // 1.6mA single-ended
+#define MAX2837_SYN_CURRENT_0_8_SINGLE 3 // 0.8mA single-ended
+__MREG__(MAX2837_SYN_CLOCKOUT_DRIVE,20,5,1)
+#define MAX2837_SYN_CLOCKOUT_DRIVE_1X 0
+#define MAX2837_SYN_CLOCKOUT_DRIVE_4X 1
+__MREG__(MAX2837_SYN_TURBO_EN,20,6,1)  // ???
+__MREG__(MAX2837_SYN_BIAS_SPI,20,7,1)  // Use trim value below
+__MREG__(MAX2837_SYN_BIAS_TRIM,20,9,2) // 00=max 10=default 11=min
+
+/* REG 21 */
+__MREG__(MAX2837_SYN_CP_COMMON_MODE_EN,21,0,1)
+__MREG__(MAX2837_SYN_PRESCALER_BIAS_BOOST,21,1,1)  // 0=default 1=+20%
+__MREG__(MAX2837_SYN_CP_BETA_EN,21,2,1)
+__MREG__(MAX2837_SYN_SD_CLOCK_SEL,21,3,1)
+#define MAX2837_SYN_SD_CLOCK_PFD 0  // from PFD reset
+#define MAX2837_SYN_SD_CLOCK_PRE 1  // from prescaler
+__MREG__(MAX2837_SYN_CP_PULSE_WIDTH_ADJ,21,4,1)    // 0=default 1=-20%
+__MREG__(MAX2837_SYN_CP_LIN_CUR,21,6,2) // +3% per step
+__MREG__(MAX2837_SYN_TEST_OUT,21,9,3)   // high bit locks CP in test mode
+#define MAX2837_SYN_TEST_LOCK_DETECT         0b000
+#define MAX2837_SYN_TEST_SD                  0b001
+#define MAX2837_SYN_TEST_REF_DIV             0b010
+#define MAX2837_SYN_TEST_MAIN_DIV            0b011
+#define MAX2837_SYN_TEST_CP_LO_Z_LOCK_DETECT 0b100
+#define MAX2837_SYN_TEST_CP_SOURCE_SD        0b101
+#define MAX2837_SYN_TEST_CP_SINK_REF_DIV     0b110
+#define MAX2837_SYN_TEST_CP_HI_Z_MAIN_DIV    0b111
+
+/* REG 22 */
+__MREG__(MAX2837_VAS_EN,22,0,1)  // select VCO subband by VAS, vs. reg
+__MREG__(MAX2837_VAS_RELOCK_SEL,22,1,1)
+#define MAX2837_VAS_RELOCK_SELECTED 0
+#define MAX2837_VAS_RELOCK_PRESENT  1
+__MREG__(MAX2837_VAS_DIV,22,4,3)
+#define MAX2837_VAS_CLK_DIV_8  0
+#define MAX2837_VAS_CLK_DIV_9  1
+#define MAX2837_VAS_CLK_DIV_10 2
+#define MAX2837_VAS_CLK_DIV_11 3
+#define MAX2837_VAS_CLK_DIV_12 4
+#define MAX2837_VAS_CLK_DIV_13 5
+#define MAX2837_VAS_CLK_DIV_14 6
+#define MAX2837_VAS_CLK_DIV_2  7
+__MREG__(MAX2837_VAS_DLY,22,6,2) // Delay = Txtal * VAS_DIV * VAS_DLY * 7
+#define MAX2837_VAS_DLY_16
+#define MAX2837_VAS_DLY_32
+#define MAX2837_VAS_DLY_64
+#define MAX2837_VAS_DLY_128
+__MREG__(MAX2837_VAS_TRIG_EN,22,7,1)
+__MREG__(MAX2837_VAS_ADE,22,8,1)
+__MREG__(MAX2837_VAS_ADL_SPI,22,9,1)
+
+/* REG 23 */
+__MREG__(MAX2837_VAS_SPI,23,4,5) // subband selection default is center (15)
+__MREG__(MAX2837_XTAL_BIAS,23,6,2)
+#define MAX2837_XTAL_BIAS_240_20 0 // 240uA for 20MHz
+#define MAX2837_XTAL_BIAS_420_20 1
+#define MAX2837_XTAL_BIAS_600_40 2
+#define MAX2837_XTAL_BIAS_780_40 3
+__MREG__(MAX2837_XTAL_E2C_BIAS,23,7,1)
+#define MAX2837_XTAL_E2C_BIAS_360 0 // uA
+#define MAX2837_XTAL_E2C_BIAS_540 1
+__MREG__(MAX2837_VAS_SE,23,8,1)
+#define MAX2837_VAS_SE_DIFF   0
+#define MAX2837_VAS_SE_SINGLE 1
+__MREG__(MAX2837_VCO_SPI_EN,23,9,1) // set to override mode
+
+/* REG 24 */
+__MREG__(MAX2837_XTAL_TUNE,24,6,7)  // 0=max 127=min freq
+__MREG__(MAX2837_CLKOUT_PIN_EN,24,7,1)
+__MREG__(MAX2837_CLKOUT_DIV,24,8,1)
+#define MAX2837_CLKOUT_DIV_1 0
+#define MAX2837_CLKOUT_DIV_2 1
+__MREG__(MAX2837_XTAL_CORE_EN,24,9,1)    // set to override mode
+
+/* REG 25 */
+__MREG__(MAX2837_VCO_BIAS_SPI_EN,25,0,1) // enable override of vco bias trim
+__MREG__(MAX2837_VCO_BIAS,25,4,4)        // 0b1000 nominal
+__MREG__(MAX2837_VCO_CMEN,25,5,1)        // enable Miller capacitor
+__MREG__(MAX2837_VCO_PDET_TST,25,7,2)    // peak detector test output select
+#define MAX2837_VCO_PDET_TST_NORMAL 0
+#define MAX2837_VCO_PDET_TST_PDOUT  1 // peak detector output
+#define MAX2837_VCO_PDET_TST_PDREF  2 // peak detector reference
+#define MAX2837_VCO_PDET_TST_TEMP   3 // VCO temperature sensor
+__MREG__(MAX2837_VCO_BUF_BIAS,25,9,2)    // VCO buffer bias
+#define MAX2837_VCO_BUF_BIAS_800uA  0
+#define MAX2837_VCO_BUF_BIAS_1200uA 1 // default
+#define MAX2837_VCO_BUF_BIAS_1600uA 2
+#define MAX2837_VCO_BUF_BIAS_2000uA 3
+
+/* REG 26 */
+__MREG__(MAX2837_LOGEN_BIAS1,26,1,2)  // LOGEN emitter follower bias
+#define MAX2837_LOGEN_BIAS1_400u    0
+#define MAX2837_LOGEN_BIAS1_600u    1
+#define MAX2837_LOGEN_BIAS1_800u    2
+#define MAX2837_LOGEN_BIAS1_1000u   3
+__MREG__(MAX2837_LOGEN_BIAS2,26,2,1)  // LOGEN RX/TX Gm bias
+#define MAX2837_LOGEN_BIAS2_DEFAULT 0 // default
+#define MAX2837_LOGEN_BIAS2_PLUS25  1 // +25%
+__MREG__(MAX2837_LOGEN_2GM,26,3,1)    //
+__MREG__(MAX2837_LOGEN_TRIM1,26,4,1)  // mixer tank trim enable
+__MREG__(MAX2837_LOGEN_TRIM2,26,5,1)  // bandpass filter trim enable
+__MREG__(MAX2837_VAS_TST,26,9,4)       // DOUT test signal select
+#define MAX2837_VAS_TST_VCO_BSW0    0  // VAS band select output (5 bits)
+#define MAX2837_VAS_TST_VCO_BSW1    1
+#define MAX2837_VAS_TST_VCO_BSW2    2
+#define MAX2837_VAS_TST_VCO_BSW3    3
+#define MAX2837_VAS_TST_VCO_BSW4    4
+#define MAX2837_VAS_TST_Vtune_ADC0  5  // VCO Vtune ADC output (3 bits)
+#define MAX2837_VAS_TST_Vtune_ADC1  6
+#define MAX2837_VAS_TST_Vtune_ADC2  7
+#define MAX2837_VAS_TST_VASA        8  // VAS accomplish (success)
+#define MAX2837_VAS_TST_VASE        9  // VAS end (success or gave up)
+#define MAX2837_VAS_TST_ZERO        15 // default
+
+/* REG 27 */
+__MREG__(MAX2837_PADRV_BIAS,27,2,3)    // PA driver bias (0-7), default 3
+__MREG__(MAX2837_PADRV_DOWN_SPI_EN,27,3,1) // PA drv down process select enable
+__MREG__(MAX2837_PADRV_DOWN,27,4,1)    // PA driver down select
+#define MAX2837_PADRV_DOWN_DOWN     0
+#define MAX2837_PADRV_DOWN_UP       1  // default
+__MREG__(MAX2837_PADAC_IV,27,5,1)      // PA DAC I/V output select
+#define MAX2837_PADAC_IV_VOLTAGE    0
+#define MAX2837_PADAC_IV_CURRENT    1  // default
+__MREG__(MAX2837_PADAC_VMODE,27,6,1)   // set logic 0 or 1 for PADAC_IV out
+__MREG__(MAX2837_PADAC_DIV,27,7,1)     // PA DAC clock divide ratio
+#define MAX2837_PADAC_DIV_20MHz     0
+#define MAX2837_PADAC_DIV_40MHz     1
+__MREG__(MAX2837_TXGATE_EN,27,8,1)     // set to relock when TXOOL=1 or LD=0
+__MREG__(MAX2837_TXDCCORR_EN,27,9,1)   // TX DC offset correction enable
+
+/* REG 28 */
+__MREG__(MAX2837_PADAC_BIAS,28,5,6)    // PADAC output current control, 5uA step
+__MREG__(MAX2837_PADAC_DLY,28,9,4)     // PADAC turn-on delay control
+                                       // 0,1 are both 0us
+                                       // then 0.5us steps to 7.0us
+
+/* REG 29 */
+__MREG__(MAX2837_TXVGA_GAIN_SPI_EN,29,0,1) // Enable SPI control of TXVGA gain
+__MREG__(MAX2837_TXVGA_GAIN_MSB_SPI_EN,29,1,1)
+__MREG__(MAX2837_TX_DCCORR_SPI_EN,29,2,1)
+__MREG__(MAX2837_FUSE_ARM,29,3,1)      // Fuse burn enable
+__MREG__(MAX2837_TXVGA_GAIN,29,9,6)    // 0 = min atten, 63 = max atten
+
+/* REG 30 */
+__MREG__(MAX2837_TXLO_IQ,30,4,5)
+__MREG__(MAX2837_TXLO_IQ_SPI_EN,30,5,1)
+__MREG__(MAX2837_TXLO_BUFF_BIAS,30,7,2)
+#define MAX2837_TXLO_BUFF_BIAS_1_0mA 0
+#define MAX2837_TXLO_BUFF_BIAS_1_5mA 1
+#define MAX2837_TXLO_BUFF_BIAS_2_0mA 2 // default
+#define MAX2837_TXLO_BUFF_BIAS_2_5mA 3
+__MREG__(MAX2837_FUSE_GKT,30,8,1)
+__MREG__(MAX2837_FUSE_RTH,30,9,1)
+
+/* REG 31 */
+// 0 -> 992/0uA correction, 15 -> 0/992uA correction ... if TX_DCCORR_SPI_EN
+__MREG__(MAX2837_TX_DCCORR_I,31,4,5)
+__MREG__(MAX2837_TX_DCCORR_Q,31,9,5)
+
+#endif // __MAX2837_REGS_DEF

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/max5864.c

@@ -0,0 +1,100 @@
+/*
+ * Copyright 2012 Jared Boone <jared@sharebrained.com>
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#include <stdint.h>
+
+#include <libopencm3/lpc43xx/gpio.h>
+#include <libopencm3/lpc43xx/ssp.h>
+
+#include "hackrf_core.h"
+#include "max5864.h"
+
+void max5864_spi_write(uint_fast8_t value) {
+	gpio_clear(PORT_AD_CS, PIN_AD_CS);
+	ssp_transfer(SSP1_NUM, value);
+	gpio_set(PORT_AD_CS, PIN_AD_CS);
+}
+
+/* Set MAX5864 operation mode to "Shutdown":
+ *   REF: off
+ *   CLK: off
+ *   ADCs: off (bus is tri-stated)
+ *   DACs: off (set input bus to zero or OVdd)
+ */
+void max5864_shutdown()
+{
+	max5864_spi_write(0x00);
+}
+
+/* Set MAX5864 operation mode to "Standby":
+ *   REF: on
+ *   CLK: off?
+ *   ADCs: off (bus is tri-stated)
+ *   DACs: off (set input bus to zero or OVdd)
+ */
+void max5864_standby()
+{
+	max5864_spi_write(0x05);
+}
+
+/* Set MAX5864 operation mode to "Idle":
+ *   REF: on
+ *   CLK: on
+ *   ADCs: off (bus is tri-stated)
+ *   DACs: off (set input bus to zero or OVdd)
+ */
+void max5864_idle()
+{
+	max5864_spi_write(0x01);
+}
+
+/* Set MAX5864 operation mode to "Rx":
+ *   REF: on
+ *   CLK: on
+ *   ADCs: on
+ *   DACs: off (set input bus to zero or OVdd)
+ */
+void max5864_rx()
+{
+	max5864_spi_write(0x02);
+}
+
+/* Set MAX5864 operation mode to "Tx":
+ *   REF: on
+ *   CLK: on
+ *   ADCs: off (bus is tri-stated)
+ *   DACs: on
+ */
+void max5864_tx()
+{
+	max5864_spi_write(0x03);
+}
+
+/* Set MAX5864 operation mode to "Xcvr":
+ *   REF: on
+ *   CLK: on
+ *   ADCs: on
+ *   DACs: on
+ */
+void max5864_xcvr()
+{
+	max5864_spi_write(0x04);
+}

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/max5864.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright 2012 Jared Boone <jared@sharebrained.com>
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#ifndef __MAX5864_H
+#define __MAX5864_H
+
+void max5864_shutdown();
+void max5864_standby();
+void max5864_idle();
+void max5864_rx();
+void max5864_tx();
+void max5864_xcvr();
+
+#endif // __MAX5864_H

SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/rf_path.c

@@ -0,0 +1,335 @@
+/*
+ * Copyright 2012 Jared Boone
+ * Copyright 2013 Benjamin Vernoux
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#include "rf_path.h"
+
+#include <libopencm3/lpc43xx/gpio.h>
+#include <libopencm3/lpc43xx/scu.h>
+
+#include <hackrf_core.h>
+
+#include <rffc5071.h>
+#include <max2837.h>
+#include <max5864.h>
+#include <sgpio.h>
+
+#if (defined JAWBREAKER || defined HACKRF_ONE)
+/*
+ * RF switches on Jawbreaker are controlled by General Purpose Outputs (GPO) on
+ * the RFFC5072.
+ *
+ * On HackRF One, the same signals are controlled by GPIO on the LPC.
+ * SWITCHCTRL_NO_TX_AMP_PWR and SWITCHCTRL_NO_RX_AMP_PWR are not normally used
+ * on HackRF One as the amplifier power is instead controlled only by
+ * SWITCHCTRL_AMP_BYPASS.
+ */
+#define SWITCHCTRL_NO_TX_AMP_PWR (1 << 0) /* GPO1 turn off TX amp power */
+#define SWITCHCTRL_AMP_BYPASS    (1 << 1) /* GPO2 bypass amp section */
+#define SWITCHCTRL_TX            (1 << 2) /* GPO3 1 for TX mode, 0 for RX mode */
+#define SWITCHCTRL_MIX_BYPASS    (1 << 3) /* GPO4 bypass RFFC5072 mixer section */
+#define SWITCHCTRL_HP            (1 << 4) /* GPO5 1 for high-pass, 0 for low-pass */
+#define SWITCHCTRL_NO_RX_AMP_PWR (1 << 5) /* GPO6 turn off RX amp power */
+
+/*
+ GPO6  GPO5  GPO4 GPO3  GPO2  GPO1
+!RXAMP  HP  MIXBP  TX  AMPBP !TXAMP  Mix mode   Amp mode
+   1    X     1    1     1      1    TX bypass  Bypass
+   1    X     1    1     0      0    TX bypass  TX amplified
+   1    1     0    1     1      1    TX high    Bypass
+   1    1     0    1     0      0    TX high    TX amplified
+   1    0     0    1     1      1    TX low     Bypass
+   1    0     0    1     0      0    TX low     TX amplified
+   1    X     1    0     1      1    RX bypass  Bypass
+   0    X     1    0     0      1    RX bypass  RX amplified
+   1    1     0    0     1      1    RX high    Bypass
+   0    1     0    0     0      1    RX high    RX amplified
+   1    0     0    0     1      1    RX low     Bypass
+   0    0     0    0     0      1    RX low     RX amplified
+*/
+
+/*
+ * Safe (initial) switch settings turn off both amplifiers and enable both amp
+ * bypass and mixer bypass.
+ */
+#define SWITCHCTRL_SAFE (SWITCHCTRL_NO_TX_AMP_PWR | SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_TX | SWITCHCTRL_MIX_BYPASS | SWITCHCTRL_HP | SWITCHCTRL_NO_RX_AMP_PWR)
+#endif
+
+uint8_t switchctrl = SWITCHCTRL_SAFE;
+
+/*
+ * Antenna port power on HackRF One is controlled by GPO1 on the RFFC5072.
+ * This is the only thing we use RFFC5072 GPO for on HackRF One.  The value of
+ * SWITCHCTRL_NO_ANT_PWR does not correspond to the GPO1 bit in the gpo
+ * register.
+ */
+#define SWITCHCTRL_ANT_PWR (1 << 6) /* turn on antenna port power */
+
+#ifdef HACKRF_ONE
+static void switchctrl_set_hackrf_one(uint8_t ctrl) {
+	if (ctrl & SWITCHCTRL_TX) {
+		gpio_set(PORT_TX, PIN_TX);
+		gpio_clear(PORT_RX, PIN_RX);
+	} else {
+		gpio_clear(PORT_TX, PIN_TX);
+		gpio_set(PORT_RX, PIN_RX);
+	}
+
+	if (ctrl & SWITCHCTRL_MIX_BYPASS) {
+		gpio_set(PORT_MIX_BYPASS, PIN_MIX_BYPASS);
+		gpio_clear(PORT_NO_MIX_BYPASS, PIN_NO_MIX_BYPASS);
+		if (ctrl & SWITCHCTRL_TX) {
+			gpio_set(PORT_TX_MIX_BP, PIN_TX_MIX_BP);
+			gpio_clear(PORT_RX_MIX_BP, PIN_RX_MIX_BP);
+		} else {
+			gpio_clear(PORT_TX_MIX_BP, PIN_TX_MIX_BP);
+			gpio_set(PORT_RX_MIX_BP, PIN_RX_MIX_BP);
+		}
+	} else {
+		gpio_clear(PORT_MIX_BYPASS, PIN_MIX_BYPASS);
+		gpio_set(PORT_NO_MIX_BYPASS, PIN_NO_MIX_BYPASS);
+		gpio_clear(PORT_TX_MIX_BP, PIN_TX_MIX_BP);
+		gpio_clear(PORT_RX_MIX_BP, PIN_RX_MIX_BP);
+	}
+
+	if (ctrl & SWITCHCTRL_HP) {
+		gpio_set(PORT_HP, PIN_HP);
+		gpio_clear(PORT_LP, PIN_LP);
+	} else {
+		gpio_clear(PORT_HP, PIN_HP);
+		gpio_set(PORT_LP, PIN_LP);
+	}
+
+	if (ctrl & SWITCHCTRL_AMP_BYPASS) {
+		gpio_set(PORT_AMP_BYPASS, PIN_AMP_BYPASS);
+		gpio_clear(PORT_TX_AMP, PIN_TX_AMP);
+		gpio_set(PORT_NO_TX_AMP_PWR, PIN_NO_TX_AMP_PWR);
+		gpio_clear(PORT_RX_AMP, PIN_RX_AMP);
+		gpio_set(PORT_NO_RX_AMP_PWR, PIN_NO_RX_AMP_PWR);
+	} else if (ctrl & SWITCHCTRL_TX) {
+		gpio_clear(PORT_AMP_BYPASS, PIN_AMP_BYPASS);
+		gpio_set(PORT_TX_AMP, PIN_TX_AMP);
+		gpio_clear(PORT_NO_TX_AMP_PWR, PIN_NO_TX_AMP_PWR);
+		gpio_clear(PORT_RX_AMP, PIN_RX_AMP);
+		gpio_set(PORT_NO_RX_AMP_PWR, PIN_NO_RX_AMP_PWR);
+	} else {
+		gpio_clear(PORT_AMP_BYPASS, PIN_AMP_BYPASS);
+		gpio_clear(PORT_TX_AMP, PIN_TX_AMP);
+		gpio_set(PORT_NO_TX_AMP_PWR, PIN_NO_TX_AMP_PWR);
+		gpio_set(PORT_RX_AMP, PIN_RX_AMP);
+		gpio_clear(PORT_NO_RX_AMP_PWR, PIN_NO_RX_AMP_PWR);
+	}
+
+	/*
+	 * These normally shouldn't be set post-Jawbreaker, but they can be
+	 * used to explicitly turn off power to the amplifiers while AMP_BYPASS
+	 * is unset:
+	 */
+	if (ctrl & SWITCHCTRL_NO_TX_AMP_PWR)
+		gpio_set(PORT_NO_TX_AMP_PWR, PIN_NO_TX_AMP_PWR);
+	if (ctrl & SWITCHCTRL_NO_RX_AMP_PWR)
+		gpio_set(PORT_NO_RX_AMP_PWR, PIN_NO_RX_AMP_PWR);
+
+	if (ctrl & SWITCHCTRL_ANT_PWR) {
+		rffc5071_set_gpo(0x00); /* turn on antenna power by clearing GPO1 */
+	} else {
+		rffc5071_set_gpo(0x01); /* turn off antenna power by setting GPO1 */
+	}
+}
+#endif
+
+static void switchctrl_set(const uint8_t gpo) {
+#ifdef JAWBREAKER
+	rffc5071_set_gpo(gpo);
+#elif HACKRF_ONE
+	switchctrl_set_hackrf_one(gpo);
+#else
+	(void)gpo;
+#endif
+}
+
+void rf_path_pin_setup() {
+#ifdef HACKRF_ONE
+	/* Configure RF switch control signals */
+	scu_pinmux(SCU_HP,             SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_LP,             SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_TX_MIX_BP,      SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_NO_MIX_BYPASS,  SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_RX_MIX_BP,      SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_TX_AMP,         SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_TX,             SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
+	scu_pinmux(SCU_MIX_BYPASS,     SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
+	scu_pinmux(SCU_RX,             SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
+	scu_pinmux(SCU_NO_TX_AMP_PWR,  SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_AMP_BYPASS,     SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_RX_AMP,         SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_NO_RX_AMP_PWR,  SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
+
+	/* Configure RF power supply (VAA) switch */
+	scu_pinmux(SCU_NO_VAA_ENABLE,  SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
+
+	/* Configure RF switch control signals as outputs */
+	GPIO0_DIR |= PIN_AMP_BYPASS;
+	GPIO1_DIR |= (PIN_NO_MIX_BYPASS | PIN_RX_AMP | PIN_NO_RX_AMP_PWR);
+	GPIO2_DIR |= (PIN_HP | PIN_LP | PIN_TX_MIX_BP | PIN_RX_MIX_BP | PIN_TX_AMP);
+	GPIO3_DIR |= PIN_NO_TX_AMP_PWR;
+	GPIO5_DIR |= (PIN_TX | PIN_MIX_BYPASS | PIN_RX);
+
+	/*
+	 * Safe (initial) switch settings turn off both amplifiers and antenna port
+	 * power and enable both amp bypass and mixer bypass.
+	 */
+	switchctrl_set(SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_MIX_BYPASS);
+
+	/* Configure RF power supply (VAA) switch control signal as output */
+	GPIO_DIR(PORT_NO_VAA_ENABLE) |= PIN_NO_VAA_ENABLE;
+
+	/* Safe state: start with VAA turned off: */
+	disable_rf_power();
+#endif
+}
+
+void rf_path_init(void) {
+	ssp1_set_mode_max5864();
+	max5864_shutdown();
+	
+	ssp1_set_mode_max2837();
+	max2837_setup();
+	max2837_start();
+	
+	rffc5071_setup();
+	switchctrl_set(switchctrl);
+}
+
+void rf_path_set_direction(const rf_path_direction_t direction) {
+	/* Turn off TX and RX amplifiers, then enable based on direction and bypass state. */
+	switchctrl |= SWITCHCTRL_NO_TX_AMP_PWR | SWITCHCTRL_NO_RX_AMP_PWR;
+	switch(direction) {
+	case RF_PATH_DIRECTION_TX:
+		switchctrl |= SWITCHCTRL_TX;
+		if( (switchctrl & SWITCHCTRL_AMP_BYPASS) == 0 ) {
+			/* TX amplifier is in path, be sure to enable TX amplifier. */
+			switchctrl &= ~SWITCHCTRL_NO_TX_AMP_PWR;
+		}
+		rffc5071_tx();
+		if( switchctrl & SWITCHCTRL_MIX_BYPASS ) {
+			rffc5071_disable();
+		} else {
+			rffc5071_enable();
+		}
+		ssp1_set_mode_max5864();
+		max5864_tx();
+		ssp1_set_mode_max2837();
+		max2837_tx();
+		sgpio_configure(SGPIO_DIRECTION_TX);
+		break;
+	
+	case RF_PATH_DIRECTION_RX:
+		switchctrl &= ~SWITCHCTRL_TX;
+		if( (switchctrl & SWITCHCTRL_AMP_BYPASS) == 0 ) {
+			/* RX amplifier is in path, be sure to enable RX amplifier. */
+			switchctrl &= ~SWITCHCTRL_NO_RX_AMP_PWR;
+		}
+		rffc5071_rx();
+		if( switchctrl & SWITCHCTRL_MIX_BYPASS ) {
+			rffc5071_disable();
+		} else {
+			rffc5071_enable();
+		}
+		ssp1_set_mode_max5864();
+		max5864_rx();
+		ssp1_set_mode_max2837();
+		max2837_rx();
+		sgpio_configure(SGPIO_DIRECTION_RX);
+		break;
+		
+	case RF_PATH_DIRECTION_OFF:
+	default:
+#ifdef HACKRF_ONE
+		rf_path_set_antenna(0);
+#endif
+		rf_path_set_lna(0);
+		/* Set RF path to receive direction when "off" */
+		switchctrl &= ~SWITCHCTRL_TX;
+		rffc5071_disable();
+		ssp1_set_mode_max5864();
+		max5864_standby();
+		ssp1_set_mode_max2837();
+		max2837_set_mode(MAX2837_MODE_STANDBY);
+		sgpio_configure(SGPIO_DIRECTION_RX);
+		break;
+	}
+
+	switchctrl_set(switchctrl);
+}
+
+void rf_path_set_filter(const rf_path_filter_t filter) {
+	switch(filter) {
+	default:
+	case RF_PATH_FILTER_BYPASS:
+		switchctrl |= SWITCHCTRL_MIX_BYPASS;
+		rffc5071_disable();
+		break;
+		
+	case RF_PATH_FILTER_LOW_PASS:
+		switchctrl &= ~(SWITCHCTRL_HP | SWITCHCTRL_MIX_BYPASS);
+		rffc5071_enable();
+		break;
+		
+	case RF_PATH_FILTER_HIGH_PASS:
+		switchctrl &= ~SWITCHCTRL_MIX_BYPASS;
+		switchctrl |= SWITCHCTRL_HP;
+		rffc5071_enable();
+		break;
+	}
+
+	switchctrl_set(switchctrl);
+}
+
+void rf_path_set_lna(const uint_fast8_t enable) {
+	if( enable ) {
+		if( switchctrl & SWITCHCTRL_TX ) {
+			/* AMP_BYPASS=0, NO_RX_AMP_PWR=1, NO_TX_AMP_PWR=0 */
+			switchctrl |= SWITCHCTRL_NO_RX_AMP_PWR;
+			switchctrl &= ~(SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_NO_TX_AMP_PWR);
+		} else {
+			/* AMP_BYPASS=0, NO_RX_AMP_PWR=0, NO_TX_AMP_PWR=1 */
+			switchctrl |= SWITCHCTRL_NO_TX_AMP_PWR;
+			switchctrl &= ~(SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_NO_RX_AMP_PWR);
+		}
+	} else {
+		/* AMP_BYPASS=1, NO_RX_AMP_PWR=1, NO_TX_AMP_PWR=1 */
+		switchctrl |= SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_NO_TX_AMP_PWR | SWITCHCTRL_NO_RX_AMP_PWR;
+	}
+	
+	switchctrl_set(switchctrl);
+}
+
+/* antenna port power control */
+void rf_path_set_antenna(const uint_fast8_t enable) {
+	if (enable) {
+		switchctrl |= SWITCHCTRL_ANT_PWR;
+	} else {
+		switchctrl &= ~(SWITCHCTRL_ANT_PWR);
+	}
+
+	switchctrl_set(switchctrl);
+}