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Updated HackRF firmware

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This commit is contained in:
Neal Probert
2022-05-13 13:08:12 -04:00
parent 3618a32734
commit 8dae36514e
611 changed files with 286269 additions and 159089 deletions
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10
SoftwareDefined/HackRF/hackrf-2015.07.2/Readme.md
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This repository contains hardware designs and software for HackRF, a project to
produce a low cost, open source software radio platform.
![Jawbreaker](https://raw.github.com/mossmann/hackrf/master/doc/jawbreaker-fd0-145436.jpeg)
(photo by fd0 from https://github.com/fd0/jawbreaker-pictures)
principal author: Michael Ossmann <mike@ossmann.com>
http://greatscottgadgets.com/hackrf/

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SoftwareDefined/HackRF/hackrf-2015.07.2/TRADEMARK
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"HackRF" is a trademark of Michael Ossmann. Permission to use the trademark
with attribution to Michael Ossmann is granted to all licensees of HackRF for
the purpose of naming or describing copies or derived works. (See COPYING.)

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SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/README
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These files are generated from KiCad source. They are provided for
convenience but may not be as up to date as the KiCad source files.

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SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/hackrf-one-assembly.pdf
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SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/hackrf-one-bom.csv
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ref;value;Field1;Field2;Field3;Field4;Field5;Field6;Field7;Field8
C1;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C2;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
C3;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C4;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
C5;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C6;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
C7;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C8;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
C9;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C10;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C11;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C12;330pF;Murata;GRM155R71H331KA01D;CAP CER 330PF 50V 10% X7R 0402;;;;;
C13;330pF;Murata;GRM155R71H331KA01D;CAP CER 330PF 50V 10% X7R 0402;;;;;
C14;8p2;Taiyo Yuden;UMK105CG8R2DV-F;CAP CER 8.2PF 50V NP0 0402;;;;;
C15;180pF;Murata;GRM1555C1H181JA01D;CAP CER 180PF 50V 5% NP0 0402;;;;;
C16;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C17;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C18;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C19;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C20;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C21;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
C22;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C23;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C24;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C25;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C26;47pF;Murata;GRM1555C1H470JA01D;CAP CER 47PF 50V 5% NP0 0402;;;;;
C27;47pF;Murata;GRM1555C1H470JA01D;CAP CER 47PF 50V 5% NP0 0402;;;;;
C28;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C29;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C30;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C31;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C32;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
C33;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C34;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C35;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C36;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C37;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C38;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C39;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C40;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C41;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;;;;;
C42;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;;;;;
C43;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
C44;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C45;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C46;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C47;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C48;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
C49;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C50;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C51;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
C52;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;;;;;
C53;1uF;Taiyo Yuden;LMK105BJ105KV-F;CAP CER 1UF 10V 10% X5R 0402;;;;;
C54;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C55;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C56;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C57;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C58;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C59;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C60;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C61;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C62;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C63;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C64;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C65;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C66;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C67;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C68;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;DNP;;;;
C69;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;DNP;;;;
C70;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;;;;;
C71;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C72;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402;;;;;
C73;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C74;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402;;;;;
C75;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C76;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402;;;;;
C77;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C78;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402;;;;;
C79;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C80;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402;;;;;
C81;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C82;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402;;;;;
C83;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C84;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
C85;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
C86;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
C87;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
C88;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
C89;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
C90;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;;;;;
C91;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C92;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
C93;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
C94;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
C95;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
C96;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
C97;330nF;Murata;GRM155R61A334KE15D;CAP CER 0.33UF 10V 10% X5R 0402;;;;;
C98;330nF;Murata;GRM155R61A334KE15D;CAP CER 0.33UF 10V 10% X5R 0402;;;;;
C99;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
C100;330nF;Murata;GRM155R61A334KE15D;CAP CER 0.33UF 10V 10% X5R 0402;;;;;
C101;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
C102;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;;;;;
C103;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
C104;3pF;Murata;GRM1555C1H3R0CA01D;CAP CER 3PF 50V NP0 0402;;;;;
C105;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805;;;;;
C106;1uF;Taiyo Yuden;LMK105BJ105KV-F;CAP CER 1UF 10V 10% X5R 0402;;;;;
C107;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
C108;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
C109;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
C110;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP;;;;
C111;3pF;Murata;GRM1555C1H3R0CA01D;CAP CER 3PF 50V NP0 0402;;;;;
C112;180pF;Murata;GRM1555C1H181JA01D;CAP CER 180PF 50V 5% NP0 0402;;;;;
C113;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C114;3.3nF;Murata;GRM155R71H332KA01D;CAP CER 3300PF 50V 10% X7R 0402;;;;;
C115;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C116;47pF;Murata;GRM1555C1H470JA01D;CAP CER 47PF 50V 5% NP0 0402;;;;;
C118;18pF;Murata;GRM1555C1H180JA01D;CAP CER 18PF 50V 5% NP0 0402;;;;;
C119;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C120;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C121;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C122;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C123;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C124;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402;;;;;
C125;33pF;Murata;GRM1555C1H330JA01D;CAP CER 33PF 50V 5% NP0 0402;;;;;
C126;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805;;;;;
C127;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805;;;;;
C128;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C129;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C130;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C131;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C132;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C133;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C134;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C135;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C136;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C137;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C138;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C139;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C140;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C141;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C142;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C143;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805;;;;;
C144;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C145;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805;;;;;
C146;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805;;;;;
C147;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C148;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C149;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C150;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C151;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C152;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C153;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C154;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C155;DNP;DNP;;;;;;;
C156;47pF;Murata;GRM1555C1H470JA01D;CAP CER 47PF 50V 5% NP0 0402;DNP;;;;
C157;18pF;Murata;GRM1555C1H180JA01D;CAP CER 18PF 50V 5% NP0 0402;;;;;
C158;18pF;Murata;GRM1555C1H180JA01D;CAP CER 18PF 50V 5% NP0 0402;;;;;
C159;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;DNP;;;;
C160;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;;;;;
C161;1uF;Taiyo Yuden;LMK105BJ105KV-F;CAP CER 1UF 10V 10% X5R 0402;;;;;
C162;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
C163;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402;;;;;
C164;18pF;Murata;GRM1555C1H180JA01D;CAP CER 18PF 50V 5% NP0 0402;;;;;
C165;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;DNP;;;;
C166;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C167;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402;;;;;
C168;100pF;Murata;GRM1555C1H101JA01D;CAP CER 100PF 50V 5% NP0 0402;DNP;;;;
C169;DNP;DNP;;;;;;;
C170;DNP;DNP;;;;;;;
C171;1uF;Taiyo Yuden;LMK105BJ105KV-F;CAP CER 1UF 10V 10% X5R 0402;;;;;
D1;GSG-DIODE-TVS-BI;Murata;LXES15AAA1-100;TVS DIODE ESD .05PF 15KV 0402;;;;;
D2;VAALED;Lite-On;LTST-S220KRKT;LED SUPR RED CLR RT ANG 0805;;;;;
D3;GSG-DIODE-TVS-BI;Murata;LXES15AAA1-100;TVS DIODE ESD .05PF 15KV 0402;;;;;
D4;USBLED;Lite-On;LTST-S220KGKT;LED GREEN CLEAR RT ANG 0805;;;;;
D5;RXLED;Lite-On;LTST-S220KSKT;LED YELLOW CLEAR RT ANG 0805;;;;;
D6;TXLED;Lite-On;LTST-S220KRKT;LED SUPR RED CLR RT ANG 0805;;;;;
D7;VCCLED;Lite-On;LTST-S220KGKT;LED GREEN CLEAR RT ANG 0805;;;;;
D8;1V8LED;Lite-On;LTST-S220KSKT;LED YELLOW CLEAR RT ANG 0805;;;;;
D9;GSG-DIODE-TVS-BI;Murata;LXES15AAA1-100;TVS DIODE ESD .05PF 15KV 0402;;;;;
FB1;FILTER;Murata;BLM21PG221SN1D;FERRITE CHIP 220 OHM 2000MA 0805;;;;;
FB2;FILTER;Murata;BLM21PG221SN1D;FERRITE CHIP 220 OHM 2000MA 0805;;;;;
FB3;FILTER;Murata;BLM21PG221SN1D;FERRITE CHIP 220 OHM 2000MA 0805;;;;;
J1;USB-MICRO-B;FCI;10103592-0001LF;CONN RCPT REV MICRO USB TYPE B;;;;;
J2;RF-SHIELD-FRAME;Laird;BMI-S-230-F-R;BOARD SHIELD 2INX1.5IN FRAME;DNP;;;;
J3;RF-SHIELD-COVER;Laird;BMI-S-230-C;BOARD SHIELD 2INX1.5IN COVER;DNP;;;;
J4;MOUNTING_HOLE;DNP;;;;;;;
J5;MOUNTING_HOLE;DNP;;;;;;;
J6;MOUNTING_HOLE;DNP;;;;;;;
J7;MOUNTING_HOLE;DNP;;;;;;;
J8;MOUNTING_HOLE;DNP;;;;;;;
J9;MOUNTING_HOLE;DNP;;;;;;;
J10;GND_CLIP;Harwin;S1751-46R;PC TEST POINT TIN SMD;DNP;;;;
L1;DNP;DNP;;;;;;;
L2;10uH;Taiyo Yuden;BRL1608T100M;INDUCTR 10UH 220MA 20% 0603 SMD;;;;;
L3;10uH;Taiyo Yuden;BRL1608T100M;INDUCTR 10UH 220MA 20% 0603 SMD;;;;;
L4;DNP;DNP;;;;;;;
L5;10uH;Taiyo Yuden;BRL1608T100M;INDUCTR 10UH 220MA 20% 0603 SMD;;;;;
L6;DNP;DNP;;;;;;;
L7;6.2nH;Taiyo Yuden;HK10056N2S-T;INDUCTOR HIFREQ 6.2+/-0.3NH 0402;;;;;
L8;DNP;DNP;;;;;;;
L9;DNP;DNP;;;;;;;
L10;4u7;Taiyo Yuden;NRG4026T4R7M;INDUCTOR 4.7UH 1.6A 20% SMD;;;;;
L11;4u7;Taiyo Yuden;NRG4026T4R7M;INDUCTOR 4.7UH 1.6A 20% SMD;;;;;
L12;10uH;Taiyo Yuden;BRL1608T100M;INDUCTR 10UH 220MA 20% 0603 SMD;;;;;
L13;10uH;Taiyo Yuden;BRL1608T100M;INDUCTR 10UH 220MA 20% 0603 SMD;;;;;
P1;1V8;DNP;;;;;;;
P2;CLKOUT;Molex;73251-2121;CONN SMA JACK 50 OHM EDGE MNT W/JAM NUT & LOCK WASHER;;;;;
P3;GND;DNP;;;;;;;
P4;ANTENNA;Molex;73251-2121;CONN SMA JACK 50 OHM EDGE MNT W/JAM NUT & LOCK WASHER;;;;;
P5;LEDS;DNP;;;;;;;
P6;GPO4;DNP;;;;;;;
P7;GPO2;DNP;;;;;;;
P8;VCC;DNP;;;;;;;
P9;BASEBAND;Sullins;PPPC082LFBN-RC;CONN HEADER FMAL 16PS.1" DL GOLD;;;;;
P13;GPO1;DNP;;;;;;;
P14;XCVR_CLKOUT;DNP;;;;;;;
P15;INTR;DNP;;;;;;;
P16;CLKIN;Molex;73251-2121;CONN SMA JACK 50 OHM EDGE MNT W/JAM NUT & LOCK WASHER;;;;;
P17;GPO6;DNP;;;;;;;
P18;OEB;DNP;;;;;;;
P19;GPO3;DNP;;;;;;;
P20;GPIO;Sullins;PPPC112LFBN-RC;CONN HEADER FMAL 22PS.1" DL GOLD;;;;;
P21;REF_IN;DNP;;;;;;;
P22;I2S;Sullins;PPPC132LFBN-RC;CONN HEADER FMAL 26PS.1" DL GOLD;;;;;
P23;DBGEN;DNP;;;;;;;
P24;TRST;DNP;;;;;;;
P25;LPC_ISP;DNP;;;;;;;
P26;LPC_JTAG;Sullins;GRPB052VWVN-RC;CONN HEADER .050" 10PS DL PCB AU;DNP;;;;
P27;MIXER_SDATA;DNP;;;;;;;
P28;SD;Sullins;PPPC112LFBN-RC;CONN HEADER FMAL 22PS.1" DL GOLD;;;;;
P29;CPLD_JTAG;DNP;;;;;;;
P30;BANK2_AUX;DNP;;;;;;;
P31;MIXER_SCLK;DNP;;;;;;;
P32;MIXER_ENX;DNP;;;;;;;
P33;MIXER_RESETX;DNP;;;;;;;
P34;MIX_BYPASS;DNP;;;;;;;
P35;!MIX_BYPASS;DNP;;;;;;;
P36;VAA;DNP;;;;;;;
P37;SCL;DNP;;;;;;;
P38;SDA;DNP;;;;;;;
P39;SSP1_SCK;DNP;;;;;;;
P40;SSP1_MOSI;DNP;;;;;;;
P41;SSP1_MISO;DNP;;;;;;;
P42;TX;DNP;;;;;;;
P43;RX;DNP;;;;;;;
P44;HP;DNP;;;;;;;
P45;LP;DNP;;;;;;;
P46;TX_MIX_BP;DNP;;;;;;;
P47;RX_MIX_BP;DNP;;;;;;;
P48;TX_AMP;DNP;;;;;;;
P49;RX_AMP;DNP;;;;;;;
P50;AMP_BYPASS;DNP;;;;;;;
P51;!TX_AMP_PWR;DNP;;;;;;;
P52;!RX_AMP_PWR;DNP;;;;;;;
P53;CS_XCVR;DNP;;;;;;;
P54;CS_AD;DNP;;;;;;;
P55;TXENABLE;DNP;;;;;;;
P56;RXENABLE;DNP;;;;;;;
P57;XTAL2;DNP;;;;;;;
P58;GCK1;DNP;;;;;;;
P59;GCK2;DNP;;;;;;;
P60;SGPIO_CLK;DNP;;;;;;;
P61;DA0;DNP;;;;;;;
P62;DA7;DNP;;;;;;;
P63;DD0;DNP;;;;;;;
P64;DD9;DNP;;;;;;;
P65;DA4;DNP;;;;;;;
P66;DD5;DNP;;;;;;;
P67;RSSI;DNP;;;;;;;
P68;SPIFI_CS;DNP;;;;;;;
P69;VREGMODE;DNP;;;;;;;
P70;EN_1V8;DNP;;;;;;;
P71;ID;DNP;;;;;;;
P72;GP_CLKIN;DNP;;;;;;;
P73;P1_2;DNP;;;;;;;
P74;P1_1;DNP;;;;;;;
P75;GP_CLKIN;DNP;;;;;;;
P76;GP_CLKIN;DNP;;;;;;;
P77;GP_CLKIN;DNP;;;;;;;
P78;GP_CLKIN;DNP;;;;;;;
P79;GP_CLKIN;DNP;;;;;;;
P80;SHIELD;DNP;;;;;;;
P81;SPIFI_SIO2;DNP;;;;;;;
P82;SPIFI_SIO3;DNP;;;;;;;
P83;GND;DNP;;;;;;;
P84;GND;DNP;;;;;;;
P85;GND;DNP;;;;;;;
P86;GND;DNP;;;;;;;
P87;GND;DNP;;;;;;;
P88;GND;DNP;;;;;;;
P89;GND;DNP;;;;;;;
P90;GND;DNP;;;;;;;
P91;GND;DNP;;;;;;;
P92;GND;DNP;;;;;;;
Q1;MOSFET_P;Fairchild;BSS84;MOSFET P-CH 50V 130MA SOT-23;;;;;
Q2;MOSFET_P;Fairchild;BSS84;MOSFET P-CH 50V 130MA SOT-23;;;;;
Q3;MOSFET_P;Diodes Inc.;DMP2305U-7;MOSFET P-CH 20V 4.2A SOT-23;;;;;
Q4;MOSFET_P;Fairchild;BSS84;MOSFET P-CH 50V 130MA SOT-23;;;;;
Q5;MOSFET_P;Alpha and Omega;AO3407A;MOSFET P-CH -30V -4.3A SOT23;;;;;
R1;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402;;;;;
R2;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402;;;;;
R3;22k;Panasonic;ERJ-2GEJ223X;RES 22K OHM 1/10W 5% 0402 SMD;;;;;
R4;51k;Stackpole;RMCF0402FT51K0;RES TF 51K OHM 1% 0.0625W 0402;;;;;
R5;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R6;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R7;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R8;1k;Stackpole;RMCF0402FT1K00;RES 1K OHM 1/16W 1% 0402;;;;;
R9;1k;Stackpole;RMCF0402FT1K00;RES 1K OHM 1/16W 1% 0402;;;;;
R10;1k;Stackpole;RMCF0402FT1K00;RES 1K OHM 1/16W 1% 0402;;;;;
R11;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R12;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R13;1k;Stackpole;RMCF0402FT1K00;RES 1K OHM 1/16W 1% 0402;;;;;
R14;4k7;Stackpole;RMCF0402FT4K70;RES 4.7K OHM 1/16W 1% 0402;;;;;
R15;4k7;Stackpole;RMCF0402FT4K70;RES 4.7K OHM 1/16W 1% 0402;;;;;
R16;4k7;Stackpole;RMCF0402FT4K70;RES 4.7K OHM 1/16W 1% 0402;;;;;
R17;4k7;Stackpole;RMCF0402FT4K70;RES 4.7K OHM 1/16W 1% 0402;;;;;
R18;1k8;Stackpole;RMCF0402JT1K80;RES TF 1.8K OHM 5% 1/16W 0402;;;;;
R19;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R20;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD;;;;;
R21;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD;;;;;
R22;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD;;;;;
R23;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD;;;;;
R24;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R25;475;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402;;;;;
R26;475;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402;;;;;
R27;1k8;Stackpole;RMCF0402JT1K80;RES TF 1.8K OHM 5% 1/16W 0402;;;;;
R28;1k8;Stackpole;RMCF0402JT1K80;RES TF 1.8K OHM 5% 1/16W 0402;;;;;
R29;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R30;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R31;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R32;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R33;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R34;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R35;DNP;DNP;;;;;;;
R36;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R37;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R41;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R46;162k;Stackpole;RMCF0402FT162K;RES TF 1/16W 162K OHM 1% 0402;;;;;
R47;330k;Stackpole;RMCF0402FT330K;RES TF 1/16W 330K OHM 1% 0402;;;;;
R48;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R49;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R51;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R52;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R54;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R55;162k;Stackpole;RMCF0402FT162K;RES TF 1/16W 162K OHM 1% 0402;;;;;
R56;715k;Stackpole;RMCF0402FT715K;RES TF 1/16W 715K OHM 1% 0402;;;;;
R57;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD;;;;;
R58;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD;;;;;
R59;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R62;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD;;;;;
R63;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R64;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R65;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R66;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R67;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R68;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R69;12k;Rohm;MCR01MRTF1202;RES 12.0K OHM 1/16W 1% 0402 SMD;;;;;
R72;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402;;;;;
R73;1k;Stackpole;RMCF0402FT1K00;RES 1K OHM 1/16W 1% 0402;;;;;
R74;1k8;Stackpole;RMCF0402JT1K80;RES TF 1.8K OHM 5% 1/16W 0402;;;;;
R75;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402;;;;;
R76;1k;Stackpole;RMCF0402FT1K00;RES 1K OHM 1/16W 1% 0402;;;;;
R77;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R78;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R79;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R80;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R81;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R85;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R86;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R87;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R88;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R89;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R90;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R91;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R93;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R94;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R96;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R98;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R99;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R100;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;;;;;
R104;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
R105;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;;;;;
SW1;DFU;TE Connectivity;FSMRA3JH;SWITCH TACTILE SPST-NO 0.05A 12V;;;;;
SW2;RESET;TE Connectivity;FSMRA3JH;SWITCH TACTILE SPST-NO 0.05A 12V;;;;;
T1;MIX_IN_BALUN;Anaren;B0310J50100AHF;Ultra Low Profile 0805 Balun 50 to 100 ohm Balanced;;;;;
T2;MIX_OUT_BALUN;Anaren;B0310J50100AHF;Ultra Low Profile 0805 Balun 50 to 100 ohm Balanced;;;;;
T3;RX_BALUN;Johanson Technology;2500BL14M100T;BALUN CERAMIC CHIP WIMAX 2.5GHZ;;;;;
T4;TX_BALUN;Johanson Technology;2500BL14M100T;BALUN CERAMIC CHIP WIMAX 2.5GHZ;;;;;
U1;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch;;;;;
U2;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch;;;;;
U3;RX_LOWPASS_FILTER;AVX;LP0603A1880ANTR;FILTER LOW PASS 1880MHZ 0603 SMD;;;;;
U4;RFFC5072;RFMD;RFFC5072TR7;WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6GHz MIXER;;;;;
U5;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch;;;;;
U6;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch;;;;;
U7;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch;;;;;
U8;RX_HIGHPASS_FILTER;TDK;DEA162400HT-8004B1;FILTER HIGHPASS WLAN&BLUETOOTH;;;;;
U9;SKY13317;Skyworks;SKY13317-373LF;20 MHz-6.0 GHz pHEMT GaAs SP3T Switch;;;;;
U10;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch;;;;;
U11;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch;;;;;
U12;SKY13317;Skyworks;SKY13317-373LF;20 MHz-6.0 GHz pHEMT GaAs SP3T Switch;;;;;
U13;MGA-81563;Avago;MGA-81563-TR1G;0.1-6 GHz 3 V, 14 dBm Amplifier;;;;;
U14;SKY13317;Skyworks;SKY13317-373LF;20 MHz-6.0 GHz pHEMT GaAs SP3T Switch;;;;;
U15;LXES1TBCC2-004;Murata;LXES1TBCC2-004;ESD Suppressors 0.55pF 6V 2ch;;;;;
U17;MAX2837;Maxim;MAX2837ETM+;IC TXRX 2.3GHZ-2.7GHZ 48TQFN;;;;;
U18;MAX5864;Maxim;MAX5864ETM+;IC ANLG FRONT END 22MSPS 48-TQFN;;;;;
U19;SI5351C;Silicon Laboratories Inc;SI5351C-B-GM;IC CLK GENERATOR 160MHZ 20QFN;;;;;
U20;W25Q80BV;Winbond;W25Q80BVSSIG;IC FLASH 8MBIT 8SOIC;;;;;
U21;TPS62410;Texas Instruments;TPS62410DRCR;IC BUCK SYNC DUAL ADJ 0.8A 10SON;;;;;
U23;LPC4320FBD144;NXP;LPC4320FBD144,551;IC MCU 32BIT 144LQFP;;;;;
U24;GSG-XC2C64A-7VQG100C;Xilinx;XC2C64A-7VQG100C;IC CR-II CPLD 64MCELL 100-VQFP;;;;;
U25;MGA-81563;Avago;MGA-81563-TR1G;0.1-6 GHz 3 V, 14 dBm Amplifier;;;;;
X1;GSG-XTAL4PIN;AVX;CX3225GB25000D0HEQZ1;CRYSTAL 25.000MHZ 8PF SMD;;;;;
X2;MCU_XTAL;TXC;7V-12.000MAAE-T;CRYSTAL 12.000 MHZ 12PF SMD;;;;;
X3;RTC_XTAL;Abracon;AB26TRQ-32.768KHZ-T;CRYSTAL 32.768KHZ 12.5PF SMD;;;;;
Can't render this file because it contains an unexpected character in line 215 and column 59.

329
SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/hackrf-one-gerbers/hackrf-one-B_Mask.gbs
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@ -1,329 +0,0 @@
G04 (created by PCBNEW (2012-nov-02)-stable) date Sat 15 Mar 2014 07:07:26 PM MDT*
%MOIN*%
G04 Gerber Fmt 3.4, Leading zero omitted, Abs format*
%FSLAX34Y34*%
G01*
G70*
G90*
G04 APERTURE LIST*
%ADD10C,0*%
%ADD11R,0.066X0.066*%
%ADD12C,0.066*%
%ADD13C,0.0650551*%
%ADD14C,0.0847402*%
%ADD15C,0.0306*%
%ADD16C,0.029*%
%ADD17R,0.048X0.048*%
%ADD18C,0.048*%
%ADD19C,0.029222*%
%ADD20C,0.0290315*%
%ADD21C,0.226472*%
%ADD22C,0.029622*%
%ADD23R,0.170961X0.110921*%
%ADD24C,0.0611181*%
%ADD25C,0.0787402*%
G04 APERTURE END LIST*
G54D10*
G54D11*
X68122Y-61397D03*
G54D12*
X67122Y-61397D03*
X68122Y-60397D03*
X67122Y-60397D03*
X68122Y-59397D03*
X67122Y-59397D03*
X68122Y-58397D03*
X67122Y-58397D03*
X68122Y-57397D03*
X67122Y-57397D03*
X68122Y-56397D03*
X67122Y-56397D03*
X68122Y-55397D03*
X67122Y-55397D03*
X68122Y-54397D03*
X67122Y-54397D03*
X68122Y-53397D03*
X67122Y-53397D03*
X68122Y-52397D03*
X67122Y-52397D03*
X68122Y-51397D03*
X67122Y-51397D03*
G54D13*
X24685Y-48090D03*
X24685Y-49862D03*
G54D14*
X25665Y-50356D03*
X25665Y-47596D03*
G54D15*
X40510Y-44276D03*
X40510Y-44925D03*
X39860Y-44925D03*
X39860Y-44276D03*
X39860Y-43626D03*
X40510Y-43626D03*
X41159Y-43626D03*
X41159Y-44276D03*
X41159Y-44925D03*
G54D16*
X42775Y-55865D03*
X42775Y-56455D03*
X42184Y-56455D03*
X42184Y-55865D03*
X42184Y-55274D03*
X42775Y-55274D03*
X43365Y-55274D03*
X43365Y-55865D03*
X43365Y-56455D03*
G54D11*
X54122Y-62397D03*
G54D12*
X55122Y-62397D03*
X56122Y-62397D03*
X57122Y-62397D03*
X58122Y-62397D03*
X59122Y-62397D03*
G54D17*
X59709Y-45065D03*
G54D18*
X60209Y-45065D03*
X59709Y-45565D03*
X60209Y-45565D03*
X59709Y-46065D03*
X60209Y-46065D03*
X59709Y-46565D03*
X60209Y-46565D03*
X59709Y-47065D03*
X60209Y-47065D03*
G54D11*
X63122Y-41397D03*
G54D12*
X63122Y-42397D03*
X62122Y-41397D03*
X62122Y-42397D03*
X61122Y-41397D03*
X61122Y-42397D03*
X60122Y-41397D03*
X60122Y-42397D03*
X59122Y-41397D03*
X59122Y-42397D03*
X58122Y-41397D03*
X58122Y-42397D03*
X57122Y-41397D03*
X57122Y-42397D03*
X56122Y-41397D03*
X56122Y-42397D03*
X55122Y-41397D03*
X55122Y-42397D03*
X54122Y-41397D03*
X54122Y-42397D03*
G54D19*
X36464Y-62111D03*
X36464Y-61678D03*
X36897Y-61678D03*
X36897Y-62111D03*
X36897Y-62544D03*
X36464Y-62544D03*
X36031Y-62544D03*
X36031Y-62111D03*
X36031Y-61678D03*
X50184Y-64144D03*
X49924Y-64403D03*
X49924Y-63884D03*
X50444Y-63884D03*
X50444Y-64403D03*
G54D11*
X33122Y-50397D03*
G54D12*
X33122Y-49397D03*
G54D11*
X57122Y-44397D03*
G54D12*
X58122Y-44397D03*
G54D11*
X62122Y-44397D03*
G54D12*
X63122Y-44397D03*
G54D20*
X66744Y-44075D03*
X66547Y-44370D03*
X66940Y-44370D03*
X66940Y-43780D03*
X66547Y-43780D03*
G54D13*
X24685Y-42972D03*
X24685Y-44744D03*
G54D14*
X25665Y-45238D03*
X25665Y-42478D03*
G54D11*
X66122Y-64397D03*
G54D12*
X66122Y-65397D03*
X65122Y-64397D03*
X65122Y-65397D03*
X64122Y-64397D03*
X64122Y-65397D03*
X63122Y-64397D03*
X63122Y-65397D03*
X62122Y-64397D03*
X62122Y-65397D03*
X61122Y-64397D03*
X61122Y-65397D03*
X60122Y-64397D03*
X60122Y-65397D03*
X59122Y-64397D03*
X59122Y-65397D03*
X58122Y-64397D03*
X58122Y-65397D03*
X57122Y-64397D03*
X57122Y-65397D03*
X56122Y-64397D03*
X56122Y-65397D03*
X55122Y-64397D03*
X55122Y-65397D03*
X54122Y-64397D03*
X54122Y-65397D03*
G54D11*
X36122Y-41397D03*
G54D12*
X36122Y-42397D03*
X35122Y-41397D03*
X35122Y-42397D03*
X34122Y-41397D03*
X34122Y-42397D03*
G54D11*
X57122Y-46397D03*
G54D12*
X57122Y-47397D03*
G54D11*
X70122Y-51397D03*
G54D12*
X70122Y-52397D03*
G54D11*
X49122Y-61397D03*
G54D12*
X48122Y-61397D03*
X49122Y-60397D03*
X48122Y-60397D03*
X49122Y-59397D03*
X48122Y-59397D03*
X49122Y-58397D03*
X48122Y-58397D03*
X49122Y-57397D03*
X48122Y-57397D03*
X49122Y-56397D03*
X48122Y-56397D03*
X49122Y-55397D03*
X48122Y-55397D03*
X49122Y-54397D03*
X48122Y-54397D03*
X49122Y-53397D03*
X48122Y-53397D03*
X49122Y-52397D03*
X48122Y-52397D03*
X49122Y-51397D03*
X48122Y-51397D03*
G54D11*
X51122Y-52397D03*
G54D12*
X52122Y-52397D03*
G54D21*
X25196Y-40944D03*
G54D22*
X25196Y-40078D03*
X24330Y-40944D03*
X25196Y-41811D03*
X26062Y-40944D03*
X25807Y-40334D03*
X24586Y-40334D03*
X24586Y-41555D03*
X25807Y-41555D03*
G54D21*
X25196Y-67322D03*
G54D22*
X25196Y-66456D03*
X24330Y-67322D03*
X25196Y-68188D03*
X26062Y-67322D03*
X25807Y-66712D03*
X24586Y-66712D03*
X24586Y-67933D03*
X25807Y-67933D03*
G54D21*
X69291Y-67322D03*
G54D22*
X69291Y-66456D03*
X68425Y-67322D03*
X69291Y-68188D03*
X70157Y-67322D03*
X69901Y-66712D03*
X68681Y-66712D03*
X68681Y-67933D03*
X69901Y-67933D03*
G54D21*
X69291Y-40944D03*
G54D22*
X69291Y-40078D03*
X68425Y-40944D03*
X69291Y-41811D03*
X70157Y-40944D03*
X69901Y-40334D03*
X68681Y-40334D03*
X68681Y-41555D03*
X69901Y-41555D03*
G54D21*
X49606Y-40944D03*
G54D22*
X49606Y-40078D03*
X48740Y-40944D03*
X49606Y-41811D03*
X50472Y-40944D03*
X50216Y-40334D03*
X48996Y-40334D03*
X48996Y-41555D03*
X50216Y-41555D03*
G54D21*
X51574Y-56692D03*
G54D22*
X51574Y-55826D03*
X50708Y-56692D03*
X51574Y-57559D03*
X52440Y-56692D03*
X52185Y-56082D03*
X50964Y-56082D03*
X50964Y-57303D03*
X52185Y-57303D03*
G54D11*
X42122Y-50397D03*
G54D12*
X42122Y-51397D03*
X41122Y-50397D03*
X41122Y-51397D03*
X40122Y-50397D03*
X40122Y-51397D03*
X39122Y-50397D03*
X39122Y-51397D03*
X38122Y-50397D03*
X38122Y-51397D03*
X37122Y-50397D03*
X37122Y-51397D03*
X36122Y-50397D03*
X36122Y-51397D03*
X35122Y-50397D03*
X35122Y-51397D03*
G54D23*
X24848Y-62010D03*
X24848Y-64760D03*
X69639Y-65548D03*
X69639Y-62798D03*
X69639Y-58461D03*
X69639Y-55711D03*
G54D13*
X70393Y-50442D03*
X70393Y-47194D03*
G54D24*
X69200Y-49799D03*
X69200Y-47838D03*
G54D25*
X67322Y-40157D03*
M02*

10737
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24585
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22220
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SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/hackrf-one-gerbers/hackrf-one-Edge_Cuts.gbr
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@ -1,120 +0,0 @@
G04 (created by PCBNEW (2012-nov-02)-stable) date Sat 15 Mar 2014 07:07:26 PM MDT*
%MOIN*%
G04 Gerber Fmt 3.4, Leading zero omitted, Abs format*
%FSLAX34Y34*%
G01*
G70*
G90*
G04 APERTURE LIST*
%ADD10C,0*%
%ADD11C,0.015*%
G04 APERTURE END LIST*
G54D10*
G54D11*
X70866Y-49931D02*
X70866Y-54622D01*
X70866Y-48061D02*
X70866Y-49576D01*
X70866Y-40944D02*
X70866Y-47706D01*
X70413Y-49576D02*
G75*
G03X70413Y-49931I0J-177D01*
G74*
G01*
X70866Y-49931D02*
X70413Y-49931D01*
X70866Y-49576D02*
X70413Y-49576D01*
X70413Y-47706D02*
G75*
G03X70413Y-48061I0J-177D01*
G74*
G01*
X70413Y-48061D02*
X70866Y-48061D01*
X70866Y-47706D02*
X70413Y-47706D01*
X23850Y-61393D02*
X23795Y-61338D01*
X23795Y-65433D02*
X23850Y-65377D01*
X23795Y-65432D02*
G75*
G03X23622Y-65850I417J-417D01*
G74*
G01*
X23850Y-65378D02*
G75*
G03X24023Y-64960I-417J417D01*
G74*
G01*
X23795Y-61338D02*
G75*
G02X23622Y-60921I417J417D01*
G74*
G01*
X23850Y-61393D02*
G75*
G02X24023Y-61811I-417J-417D01*
G74*
G01*
X70866Y-67322D02*
X70866Y-66637D01*
X70637Y-66165D02*
X70692Y-66220D01*
X70693Y-66220D02*
G75*
G02X70866Y-66637I-417J-417D01*
G74*
G01*
X70637Y-66165D02*
G75*
G02X70464Y-65748I417J417D01*
G74*
G01*
X70637Y-55094D02*
X70692Y-55039D01*
X70693Y-55039D02*
G75*
G03X70866Y-54622I-417J417D01*
G74*
G01*
X70637Y-55094D02*
G75*
G03X70464Y-55511I417J-417D01*
G74*
G01*
X23622Y-65850D02*
X23622Y-67322D01*
X23622Y-60921D02*
X23622Y-40944D01*
X24023Y-61811D02*
X24023Y-64960D01*
X70464Y-55511D02*
X70464Y-65748D01*
X69291Y-39370D02*
X25196Y-39370D01*
X25196Y-68897D02*
X69291Y-68897D01*
X69291Y-68897D02*
G75*
G03X70866Y-67322I0J1574D01*
G74*
G01*
X70866Y-40944D02*
G75*
G03X69291Y-39370I-1574J0D01*
G74*
G01*
X23622Y-67322D02*
G75*
G03X25196Y-68897I1574J0D01*
G74*
G01*
X25196Y-39370D02*
G75*
G03X23622Y-40944I0J-1574D01*
G74*
G01*
M02*

3208
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2737
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5631
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832
SoftwareDefined/HackRF/hackrf-2015.07.2/doc/hardware/hackrf-one-gerbers/hackrf-one.drl
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@ -1,832 +0,0 @@
M48
INCH,TZ
T1C0.013
T2C0.013
T3C0.014
T4C0.015
T5C0.016
T6C0.020
T7C0.025
T8C0.028
T9C0.028
T10C0.035
T11C0.039
T12C0.040
T13C0.051
T14C0.126
%
G90
G05
T1
X066547Y-044371
X066744Y-044075
T2
X027744Y-061755
X027744Y-062605
X028644Y-061705
X028834Y-063305
X028874Y-057845
X029035Y-061890
X029092Y-056731
X029112Y-056231
X029754Y-059245
X030050Y-066064
X030302Y-054621
X030352Y-055881
X030464Y-061305
X030784Y-061455
X031434Y-060765
X031660Y-057780
X031752Y-053831
X031752Y-054281
X031752Y-054731
X031972Y-066158
X033352Y-054681
X033352Y-055931
X034152Y-063008
X034750Y-061560
X034838Y-056789
X036128Y-056939
X036150Y-049756
X036650Y-049756
X037380Y-049756
X037805Y-059962
X037882Y-049758
X038240Y-061360
X038255Y-060062
X038335Y-061712
X038343Y-065364
X038700Y-060440
X038765Y-042911
X039400Y-047546
X039900Y-047546
X040335Y-046101
X040630Y-047546
X040960Y-056980
X041100Y-061650
X041105Y-056465
X041130Y-047546
X041175Y-055555
X041240Y-057330
X041607Y-066367
X042330Y-053880
X042330Y-054270
X042600Y-061280
X042820Y-053040
X044025Y-054405
X050935Y-065394
X050942Y-065738
X053662Y-047208
X054292Y-063508
X054402Y-058688
X054582Y-058408
X054652Y-061393
X054887Y-061668
X055642Y-057088
X055982Y-057118
X056352Y-054078
X056539Y-050409
X056546Y-059976
X056765Y-053336
X057092Y-056008
X057122Y-045578
X057122Y-053708
X057122Y-055608
X057132Y-052638
X057252Y-051918
X057282Y-060598
X057322Y-053118
X057442Y-059168
X057562Y-052178
X057662Y-053078
X057742Y-051228
X058002Y-059768
X058186Y-049143
X058252Y-048428
X058252Y-059998
X058502Y-055668
X058522Y-048108
X058742Y-055958
X059070Y-051484
X059572Y-052538
X059772Y-062808
X060132Y-056858
X060182Y-057578
X060512Y-057228
X060542Y-060438
X060712Y-060728
X060774Y-060132
X060792Y-055738
X060802Y-056108
X060812Y-055038
X060842Y-055408
X060906Y-052322
X061882Y-057258
X062192Y-055788
X062606Y-055557
X063044Y-055288
X063150Y-055635
X064994Y-044325
X065444Y-043625
X066547Y-043780
X066941Y-043780
X066941Y-044371
X068224Y-045075
X068904Y-042575
T3
X036032Y-061679
X036032Y-062112
X036032Y-062545
X036465Y-061679
X036465Y-062112
X036465Y-062545
X036898Y-061679
X036898Y-062112
X036898Y-062545
X049925Y-063884
X049925Y-064404
X050185Y-064144
X050445Y-063884
X050445Y-064404
T4
X024331Y-040945
X024331Y-067323
X024587Y-040335
X024587Y-041555
X024587Y-066713
X024587Y-067933
X024614Y-061614
X024614Y-062008
X024614Y-062402
X024614Y-064370
X024614Y-064764
X024614Y-065157
X025008Y-061614
X025008Y-062008
X025008Y-062402
X025008Y-064370
X025008Y-064764
X025008Y-065157
X025197Y-040079
X025197Y-041811
X025197Y-066457
X025197Y-068189
X025402Y-061614
X025402Y-062008
X025402Y-062402
X025402Y-064370
X025402Y-064764
X025402Y-065157
X025807Y-040335
X025807Y-041555
X025807Y-066713
X025807Y-067933
X026063Y-040945
X026063Y-067323
X039860Y-043627
X039860Y-044276
X039860Y-044926
X040510Y-043627
X040510Y-044276
X040510Y-044926
X041160Y-043627
X041160Y-044276
X041160Y-044926
X042184Y-055274
X042184Y-055865
X042184Y-056456
X042775Y-055274
X042775Y-055865
X042775Y-056456
X043366Y-055274
X043366Y-055865
X043366Y-056456
X048740Y-040945
X048996Y-040335
X048996Y-041555
X049606Y-040079
X049606Y-041811
X050217Y-040335
X050217Y-041555
X050472Y-040945
X050709Y-056693
X050965Y-056083
X050965Y-057303
X051575Y-055827
X051575Y-057559
X052185Y-056083
X052185Y-057303
X052441Y-056693
X068425Y-040945
X068425Y-067323
X068681Y-040335
X068681Y-041555
X068681Y-066713
X068681Y-067933
X069087Y-055315
X069087Y-055709
X069087Y-056102
X069087Y-058071
X069087Y-058465
X069087Y-058858
X069087Y-062402
X069087Y-062795
X069087Y-063189
X069087Y-065157
X069087Y-065551
X069087Y-065945
X069291Y-040079
X069291Y-041811
X069291Y-066457
X069291Y-068189
X069480Y-055315
X069480Y-055709
X069480Y-056102
X069480Y-058071
X069480Y-058465
X069480Y-058858
X069480Y-062402
X069480Y-062795
X069480Y-063189
X069480Y-065157
X069480Y-065551
X069480Y-065945
X069874Y-055315
X069874Y-055709
X069874Y-056102
X069874Y-058071
X069874Y-058465
X069874Y-058858
X069874Y-062402
X069874Y-062795
X069874Y-063189
X069874Y-065157
X069874Y-065551
X069874Y-065945
X069902Y-040335
X069902Y-041555
X069902Y-066713
X069902Y-067933
X070157Y-040945
X070157Y-067323
T5
X025032Y-046368
X036355Y-058922
X036355Y-059452
X036755Y-059452
X037155Y-059452
X037452Y-059098
X037805Y-058812
X037960Y-047176
X038255Y-058962
X038360Y-047176
X038705Y-059262
X038760Y-047176
X039020Y-064630
X039160Y-047176
X039212Y-042148
X039268Y-042578
X039560Y-046076
X039560Y-047176
X039892Y-063158
X040052Y-064648
X040400Y-047176
X040760Y-047136
X040952Y-064558
X041055Y-055195
X041532Y-047228
X041922Y-063588
X041992Y-047288
X042690Y-064830
X044375Y-055305
X044435Y-055845
X044602Y-056588
X044725Y-055475
X045460Y-053640
X046100Y-043930
X046192Y-047448
X046232Y-048048
X047360Y-068120
X047462Y-047868
X048042Y-046878
X048042Y-048028
X048052Y-047648
X048062Y-047268
X048542Y-062188
X048902Y-063418
X049232Y-049848
X049642Y-058258
X049792Y-058908
X049942Y-059438
X050062Y-058648
X050082Y-044088
X050102Y-043698
X050202Y-058998
X050602Y-044328
X050692Y-043748
X050832Y-053108
X050892Y-044068
X050912Y-051178
X050972Y-053458
X051082Y-044398
X051202Y-053988
X051792Y-059088
X052052Y-051268
X052442Y-059538
X052792Y-062628
X053072Y-059548
X053082Y-064048
X053223Y-051069
X053292Y-064428
X053622Y-063928
X053662Y-063488
X054302Y-050778
X054422Y-050198
X054990Y-056410
X055920Y-055320
X056182Y-050338
X056212Y-060358
X056332Y-058068
X056410Y-055370
X056722Y-045148
X056912Y-057288
X057022Y-058718
X057282Y-048168
X057712Y-048158
X058522Y-054918
X059062Y-052108
X059222Y-052468
X059692Y-053098
X060762Y-056748
X060800Y-058460
X061080Y-045976
X061082Y-046388
X061170Y-062700
X061492Y-047878
X061632Y-061358
X061782Y-061008
X061872Y-051258
X062042Y-053228
X062082Y-046858
X062172Y-061048
X062342Y-045988
X062342Y-048668
X062358Y-058647
X062772Y-049368
X062832Y-060688
X063202Y-048768
X063572Y-046988
X063701Y-048583
X063900Y-061910
X064170Y-062210
X064472Y-059808
X064900Y-054850
X065082Y-050818
X065682Y-059148
X065990Y-058910
X066142Y-052108
X066280Y-061980
X066650Y-058060
X067934Y-043505
X068044Y-044675
X068894Y-043075
X068894Y-045575
X069250Y-042336
T6
X028774Y-064385
X029234Y-063705
X035715Y-064792
X036765Y-064792
X037335Y-044801
X040015Y-055375
X040810Y-046076
X042855Y-059445
X042995Y-059885
X043275Y-053055
X043385Y-054105
X045575Y-055065
X045585Y-055845
X050985Y-066144
X051885Y-065594
X062591Y-056646
X063348Y-052495
T7
X024622Y-046738
X024722Y-051898
X024722Y-053698
X024722Y-055488
X024722Y-057288
X024722Y-059088
X025122Y-052898
X025822Y-064098
X026673Y-053937
X026673Y-056299
X026673Y-058661
X026673Y-061024
X026673Y-065748
X026722Y-043088
X026722Y-048188
X027165Y-062598
X027244Y-060205
X027284Y-060995
X027284Y-061825
X027342Y-058268
X027594Y-059405
X027704Y-058805
X027894Y-060875
X027932Y-056721
X028254Y-062705
X028312Y-055851
X028346Y-052362
X028346Y-067323
X028702Y-065008
X028982Y-066198
X029324Y-059245
X029344Y-058605
X029480Y-055000
X029494Y-061135
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T0
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/*
* Copyright 2012 Michael Ossmann <mike@ossmann.com>
* Copyright 2012 Jared Boone <jared@sharebrained.com>
* Copyright 2013 Benjamin Vernoux <titanmkd@gmail.com>
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include "hackrf_core.h"
#include "si5351c.h"
#include "max2837.h"
#include "rffc5071.h"
#include "sgpio.h"
#include "rf_path.h"
#include <libopencm3/lpc43xx/i2c.h>
#include <libopencm3/lpc43xx/cgu.h>
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/ssp.h>
#define WAIT_CPU_CLOCK_INIT_DELAY (10000)
void delay(uint32_t duration)
{
uint32_t i;
for (i = 0; i < duration; i++)
__asm__("nop");
}
/* GCD algo from wikipedia */
/* http://en.wikipedia.org/wiki/Greatest_common_divisor */
static uint32_t
gcd(uint32_t u, uint32_t v)
{
int s;
if (!u || !v)
return u | v;
for (s=0; !((u|v)&1); s++) {
u >>= 1;
v >>= 1;
}
while (!(u&1))
u >>= 1;
do {
while (!(v&1))
v >>= 1;
if (u>v) {
uint32_t t;
t = v;
v = u;
u = t;
}
v = v - u;
}
while (v);
return u << s;
}
bool sample_rate_frac_set(uint32_t rate_num, uint32_t rate_denom)
{
const uint64_t VCO_FREQ = 800 * 1000 * 1000; /* 800 MHz */
uint32_t MSx_P1,MSx_P2,MSx_P3;
uint32_t a, b, c;
uint32_t rem;
/* Find best config */
a = (VCO_FREQ * rate_denom) / rate_num;
rem = (VCO_FREQ * rate_denom) - (a * rate_num);
if (!rem) {
/* Integer mode */
b = 0;
c = 1;
} else {
/* Fractional */
uint32_t g = gcd(rem, rate_num);
rem /= g;
rate_num /= g;
if (rate_num < (1<<20)) {
/* Perfect match */
b = rem;
c = rate_num;
} else {
/* Approximate */
c = (1<<20) - 1;
b = ((uint64_t)c * (uint64_t)rem) / rate_num;
g = gcd(b, c);
b /= g;
c /= g;
}
}
/* Can we enable integer mode ? */
if (a & 0x1 || b)
si5351c_set_int_mode(0, 0);
else
si5351c_set_int_mode(0, 1);
/* Final MS values */
MSx_P1 = 128*a + (128 * b/c) - 512;
MSx_P2 = (128*b) % c;
MSx_P3 = c;
/* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */
si5351c_configure_multisynth(0, MSx_P1, MSx_P2, MSx_P3, 1);
/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
si5351c_configure_multisynth(1, 0, 0, 0, 0);//p1 doesn't matter
/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
si5351c_configure_multisynth(2, 0, 0, 0, 0);//p1 doesn't matter
return true;
}
bool sample_rate_set(const uint32_t sample_rate_hz) {
#ifdef JELLYBEAN
/* Due to design issues, Jellybean/Lemondrop frequency plan is limited.
* Long version of the story: The MAX2837 reference frequency
* originates from the same PLL as the sample clocks, and in order to
* keep the sample clocks in phase and keep jitter noise down, the MAX2837
* and sample clocks must be integer-related.
*/
uint32_t r_div_sample = 2;
uint32_t r_div_sgpio = 1;
switch( sample_rate_hz ) {
case 5000000:
r_div_sample = 3; /* 800 MHz / 20 / 8 = 5 MHz */
r_div_sgpio = 2; /* 800 MHz / 20 / 4 = 10 MHz */
break;
case 10000000:
r_div_sample = 2; /* 800 MHz / 20 / 4 = 10 MHz */
r_div_sgpio = 1; /* 800 MHz / 20 / 2 = 20 MHz */
break;
case 20000000:
r_div_sample = 1; /* 800 MHz / 20 / 2 = 20 MHz */
r_div_sgpio = 0; /* 800 MHz / 20 / 1 = 40 MHz */
break;
default:
return false;
}
/* NOTE: Because MS1, 2, 3 outputs are slaved to PLLA, the p1, p2, p3
* values are irrelevant. */
/* MS0/CLK1 is the source for the MAX5864 codec. */
si5351c_configure_multisynth(1, 4608, 0, 1, r_div_sample);
/* MS0/CLK2 is the source for the CPLD codec clock (same as CLK1). */
si5351c_configure_multisynth(2, 4608, 0, 1, r_div_sample);
/* MS0/CLK3 is the source for the SGPIO clock. */
si5351c_configure_multisynth(3, 4608, 0, 1, r_div_sgpio);
return true;
#endif
#if (defined JAWBREAKER || defined HACKRF_ONE)
uint32_t p1 = 4608;
uint32_t p2 = 0;
uint32_t p3 = 0;
switch(sample_rate_hz) {
case 8000000:
p1 = SI_INTDIV(50); // 800MHz / 50 = 16 MHz (SGPIO), 8 MHz (codec)
break;
case 9216000:
// 43.40277777777778: a = 43; b = 29; c = 72
p1 = 5043;
p2 = 40;
p3 = 72;
break;
case 10000000:
p1 = SI_INTDIV(40); // 800MHz / 40 = 20 MHz (SGPIO), 10 MHz (codec)
break;
case 12288000:
// 32.552083333333336: a = 32; b = 159; c = 288
p1 = 3654;
p2 = 192;
p3 = 288;
break;
case 12500000:
p1 = SI_INTDIV(32); // 800MHz / 32 = 25 MHz (SGPIO), 12.5 MHz (codec)
break;
case 16000000:
p1 = SI_INTDIV(25); // 800MHz / 25 = 32 MHz (SGPIO), 16 MHz (codec)
break;
case 18432000:
// 21.70138888889: a = 21; b = 101; c = 144
p1 = 2265;
p2 = 112;
p3 = 144;
break;
case 20000000:
p1 = SI_INTDIV(20); // 800MHz / 20 = 40 MHz (SGPIO), 20 MHz (codec)
break;
default:
return false;
}
/* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */
si5351c_configure_multisynth(0, p1, p2, p3, 1);
/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
si5351c_configure_multisynth(1, p1, 0, 1, 0);//p1 doesn't matter
/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
si5351c_configure_multisynth(2, p1, 0, 1, 0);//p1 doesn't matter
return true;
#endif
}
bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz) {
return max2837_set_lpf_bandwidth(bandwidth_hz);
}
/* clock startup for Jellybean with Lemondrop attached
Configure PLL1 to max speed (204MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */
void cpu_clock_init(void)
{
/* use IRC as clock source for APB1 (including I2C0) */
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);
/* use IRC as clock source for APB3 */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC);
i2c0_init(15);
si5351c_disable_all_outputs();
si5351c_disable_oeb_pin_control();
si5351c_power_down_all_clocks();
si5351c_set_crystal_configuration();
si5351c_enable_xo_and_ms_fanout();
si5351c_configure_pll_sources();
si5351c_configure_pll_multisynth();
#ifdef JELLYBEAN
/*
* Jellybean/Lemondrop clocks:
* CLK0 -> MAX2837
* CLK1 -> MAX5864/CPLD.GCLK0
* CLK2 -> CPLD.GCLK1
* CLK3 -> CPLD.GCLK2
* CLK4 -> LPC4330
* CLK5 -> RFFC5072
* CLK6 -> extra
* CLK7 -> extra
*/
/* MS0/CLK0 is the source for the MAX2837 clock input. */
si5351c_configure_multisynth(0, 2048, 0, 1, 0); /* 40MHz */
/* MS4/CLK4 is the source for the LPC43xx microcontroller. */
si5351c_configure_multisynth(4, 8021, 0, 3, 0); /* 12MHz */
/* MS5/CLK5 is the source for the RFFC5071 mixer. */
si5351c_configure_multisynth(5, 1536, 0, 1, 0); /* 50MHz */
#endif
#if (defined JAWBREAKER || defined HACKRF_ONE)
/*
* Jawbreaker clocks:
* CLK0 -> MAX5864/CPLD
* CLK1 -> CPLD
* CLK2 -> SGPIO
* CLK3 -> external clock output
* CLK4 -> RFFC5072
* CLK5 -> MAX2837
* CLK6 -> none
* CLK7 -> LPC4330 (but LPC4330 starts up on its own crystal)
*/
/* MS3/CLK3 is the source for the external clock output. */
si5351c_configure_multisynth(3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */
/* MS4/CLK4 is the source for the RFFC5071 mixer. */
si5351c_configure_multisynth(4, 16*128-512, 0, 1, 0); /* 800/16 = 50MHz */
/* MS5/CLK5 is the source for the MAX2837 clock input. */
si5351c_configure_multisynth(5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
/* MS6/CLK6 is unused. */
/* MS7/CLK7 is the source for the LPC43xx microcontroller. */
uint8_t ms7data[] = { 90, 255, 20, 0 };
si5351c_write(ms7data, sizeof(ms7data));
#endif
/* Set to 10 MHz, the common rate between Jellybean and Jawbreaker. */
sample_rate_set(10000000);
si5351c_set_clock_source(PLL_SOURCE_XTAL);
// soft reset
uint8_t resetdata[] = { 177, 0xac };
si5351c_write(resetdata, sizeof(resetdata));
si5351c_enable_clock_outputs();
//FIXME disable I2C
/* Kick I2C0 down to 400kHz when we switch over to APB1 clock = 204MHz */
i2c0_init(255);
/*
* 12MHz clock is entering LPC XTAL1/OSC input now. On
* Jellybean/Lemondrop, this is a signal from the clock generator. On
* Jawbreaker, there is a 12 MHz crystal at the LPC.
* Set up PLL1 to run from XTAL1 input.
*/
//FIXME a lot of the details here should be in a CGU driver
#ifdef JELLYBEAN
/* configure xtal oscillator for external clock input signal */
CGU_XTAL_OSC_CTRL |= CGU_XTAL_OSC_CTRL_BYPASS;
#endif
/* set xtal oscillator to low frequency mode */
CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF_MASK;
/* power on the oscillator and wait until stable */
CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE_MASK;
/* Wait about 100us after Crystal Power ON */
delay(WAIT_CPU_CLOCK_INIT_DELAY);
/* use XTAL_OSC as clock source for BASE_M4_CLK (CPU) */
CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
/* use XTAL_OSC as clock source for APB1 */
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
/* use XTAL_OSC as clock source for APB3 */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);
cpu_clock_pll1_low_speed();
/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
/* use XTAL_OSC as clock source for PLL0USB */
CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1)
| CGU_PLL0USB_CTRL_AUTOBLOCK(1)
| CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL);
while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK);
/* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */
/* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */
CGU_PLL0USB_MDIV = 0x06167FFA;
CGU_PLL0USB_NP_DIV = 0x00302062;
CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD(1)
| CGU_PLL0USB_CTRL_DIRECTI(1)
| CGU_PLL0USB_CTRL_DIRECTO(1)
| CGU_PLL0USB_CTRL_CLKEN(1));
/* power on PLL0USB and wait until stable */
CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD_MASK;
while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK));
/* use PLL0USB as clock source for USB0 */
CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK(1)
| CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);
/* Switch peripheral clock over to use PLL1 (204MHz) */
CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK(1)
| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
/* Switch APB1 clock over to use PLL1 (204MHz) */
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
/* Switch APB3 clock over to use PLL1 (204MHz) */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1);
}
/*
Configure PLL1 to low speed (48MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1.
This function shall be called after cpu_clock_init().
This function is mainly used to lower power consumption.
*/
void cpu_clock_pll1_low_speed(void)
{
uint32_t pll_reg;
/* Configure PLL1 Clock (48MHz) */
/* Integer mode:
FCLKOUT = M*(FCLKIN/N)
FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N)
*/
pll_reg = CGU_PLL1_CTRL;
/* Clear PLL1 bits */
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */
CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
/* Set PLL1 up to 12MHz * 4 = 48MHz. */
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
| CGU_PLL1_CTRL_PSEL(0)
| CGU_PLL1_CTRL_NSEL(0)
| CGU_PLL1_CTRL_MSEL(3)
| CGU_PLL1_CTRL_FBSEL(1)
| CGU_PLL1_CTRL_DIRECT(1);
CGU_PLL1_CTRL = pll_reg;
/* wait until stable */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
/* Wait a delay after switch to new frequency with Direct mode */
delay(WAIT_CPU_CLOCK_INIT_DELAY);
}
/*
Configure PLL1 (Main MCU Clock) to max speed (204MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1.
This function shall be called after cpu_clock_init().
*/
void cpu_clock_pll1_max_speed(void)
{
uint32_t pll_reg;
/* Configure PLL1 to Intermediate Clock (between 90 MHz and 110 MHz) */
/* Integer mode:
FCLKOUT = M*(FCLKIN/N)
FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N)
*/
pll_reg = CGU_PLL1_CTRL;
/* Clear PLL1 bits */
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */
CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
/* Set PLL1 up to 12MHz * 8 = 96MHz. */
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
| CGU_PLL1_CTRL_PSEL(0)
| CGU_PLL1_CTRL_NSEL(0)
| CGU_PLL1_CTRL_MSEL(7)
| CGU_PLL1_CTRL_FBSEL(1);
CGU_PLL1_CTRL = pll_reg;
/* wait until stable */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
/* Wait before to switch to max speed */
delay(WAIT_CPU_CLOCK_INIT_DELAY);
/* Configure PLL1 Max Speed */
/* Direct mode: FCLKOUT = FCCO = M*(FCLKIN/N) */
pll_reg = CGU_PLL1_CTRL;
/* Clear PLL1 bits */
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */
CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
/* Set PLL1 up to 12MHz * 17 = 204MHz. */
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
| CGU_PLL1_CTRL_PSEL(0)
| CGU_PLL1_CTRL_NSEL(0)
| CGU_PLL1_CTRL_MSEL(16)
| CGU_PLL1_CTRL_FBSEL(1)
| CGU_PLL1_CTRL_DIRECT(1);
CGU_PLL1_CTRL = pll_reg;
/* wait until stable */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
}
void ssp1_init(void)
{
/*
* Configure CS_AD pin to keep the MAX5864 SPI disabled while we use the
* SPI bus for the MAX2837. FIXME: this should probably be somewhere else.
*/
scu_pinmux(SCU_AD_CS, SCU_GPIO_FAST);
GPIO_SET(PORT_AD_CS) = PIN_AD_CS;
GPIO_DIR(PORT_AD_CS) |= PIN_AD_CS;
scu_pinmux(SCU_XCVR_CS, SCU_GPIO_FAST);
GPIO_SET(PORT_XCVR_CS) = PIN_XCVR_CS;
GPIO_DIR(PORT_XCVR_CS) |= PIN_XCVR_CS;
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
}
void ssp1_set_mode_max2837(void)
{
/* FIXME speed up once everything is working reliably */
/*
// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
const uint8_t serial_clock_rate = 32;
const uint8_t clock_prescale_rate = 128;
*/
// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
const uint8_t serial_clock_rate = 21;
const uint8_t clock_prescale_rate = 2;
ssp_init(SSP1_NUM,
SSP_DATA_16BITS,
SSP_FRAME_SPI,
SSP_CPOL_0_CPHA_0,
serial_clock_rate,
clock_prescale_rate,
SSP_MODE_NORMAL,
SSP_MASTER,
SSP_SLAVE_OUT_ENABLE);
}
void ssp1_set_mode_max5864(void)
{
/* FIXME speed up once everything is working reliably */
/*
// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
const uint8_t serial_clock_rate = 32;
const uint8_t clock_prescale_rate = 128;
*/
// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
const uint8_t serial_clock_rate = 21;
const uint8_t clock_prescale_rate = 2;
ssp_init(SSP1_NUM,
SSP_DATA_8BITS,
SSP_FRAME_SPI,
SSP_CPOL_0_CPHA_0,
serial_clock_rate,
clock_prescale_rate,
SSP_MODE_NORMAL,
SSP_MASTER,
SSP_SLAVE_OUT_ENABLE);
}
void pin_setup(void) {
/* Release CPLD JTAG pins */
scu_pinmux(SCU_PINMUX_CPLD_TDO, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_PINMUX_CPLD_TCK, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_CPLD_TMS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_CPLD_TDI, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
GPIO_DIR(PORT_CPLD_TDO) &= ~PIN_CPLD_TDO;
GPIO_DIR(PORT_CPLD_TCK) &= ~PIN_CPLD_TCK;
GPIO_DIR(PORT_CPLD_TMS) &= ~PIN_CPLD_TMS;
GPIO_DIR(PORT_CPLD_TDI) &= ~PIN_CPLD_TDI;
/* Configure SCU Pin Mux as GPIO */
scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_NOPULL);
scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_NOPULL);
scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_NOPULL);
scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_NOPULL);
/* Configure USB indicators */
#if (defined JELLYBEAN || defined JAWBREAKER)
scu_pinmux(SCU_PINMUX_USB_LED0, SCU_CONF_FUNCTION3);
scu_pinmux(SCU_PINMUX_USB_LED1, SCU_CONF_FUNCTION3);
#endif
/* Configure all GPIO as Input (safe state) */
GPIO0_DIR = 0;
GPIO1_DIR = 0;
GPIO2_DIR = 0;
GPIO3_DIR = 0;
GPIO4_DIR = 0;
GPIO5_DIR = 0;
GPIO6_DIR = 0;
GPIO7_DIR = 0;
/* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
GPIO2_DIR |= (PIN_LED1 | PIN_LED2 | PIN_LED3);
/* GPIO3[6] on P6_10 as output. */
GPIO3_DIR |= PIN_EN1V8;
rf_path_pin_setup();
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
/* Configure external clock in */
scu_pinmux(SCU_PINMUX_GP_CLKIN, SCU_CLK_IN | SCU_CONF_FUNCTION1);
sgpio_configure_pin_functions();
}
void enable_1v8_power(void) {
gpio_set(PORT_EN1V8, PIN_EN1V8);
}
void disable_1v8_power(void) {
gpio_clear(PORT_EN1V8, PIN_EN1V8);
}
#ifdef HACKRF_ONE
void enable_rf_power(void) {
gpio_clear(PORT_NO_VAA_ENABLE, PIN_NO_VAA_ENABLE);
}
void disable_rf_power(void) {
gpio_set(PORT_NO_VAA_ENABLE, PIN_NO_VAA_ENABLE);
}
#endif

507
SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/max2837.c
View File

@ -1,507 +0,0 @@
/*
* 'gcc -DTEST -DDEBUG -O2 -o test max2837.c' prints out what test
* program would do if it had a real spi library
*
* 'gcc -DTEST -DBUS_PIRATE -O2 -o test max2837.c' prints out bus
* pirate commands to do the same thing.
*/
#include <stdint.h>
#include <string.h>
#include "max2837.h"
#include "max2837_regs.def" // private register def macros
#if (defined DEBUG || defined BUS_PIRATE)
#include <stdio.h>
#define LOG printf
#else
#define LOG(x,...)
#include <libopencm3/lpc43xx/ssp.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/gpio.h>
#include "hackrf_core.h"
#endif
/* Default register values. */
static uint16_t max2837_regs_default[MAX2837_NUM_REGS] = {
0x150, /* 0 */
0x002, /* 1 */
0x1f4, /* 2 */
0x1b9, /* 3 */
0x00a, /* 4 */
0x080, /* 5 */
0x006, /* 6 */
0x000, /* 7 */
0x080, /* 8 */
0x018, /* 9 */
0x058, /* 10 */
0x016, /* 11 */
0x24f, /* 12 */
0x150, /* 13 */
0x1c5, /* 14 */
0x081, /* 15 */
0x01c, /* 16 */
0x155, /* 17 */
0x155, /* 18 */
0x153, /* 19 */
0x241, /* 20 */
/*
* Charge Pump Common Mode Enable bit (0) of register 21 must be set or TX
* does not work. Page 1 of the SPI doc says not to set it (0x02c), but
* page 21 says it should be set by default (0x02d).
*/
0x02d, /* 21 */
0x1a9, /* 22 */
0x24f, /* 23 */
0x180, /* 24 */
0x100, /* 25 */
0x3ca, /* 26 */
0x3e3, /* 27 */
0x0c0, /* 28 */
0x3f0, /* 29 */
0x080, /* 30 */
0x000 }; /* 31 */
uint16_t max2837_regs[MAX2837_NUM_REGS];
/* Mark all regsisters dirty so all will be written at init. */
uint32_t max2837_regs_dirty = 0xffffffff;
/* Set up all registers according to defaults specified in docs. */
void max2837_init(void)
{
LOG("# max2837_init\n");
memcpy(max2837_regs, max2837_regs_default, sizeof(max2837_regs));
max2837_regs_dirty = 0xffffffff;
/* Write default register values to chip. */
max2837_regs_commit();
}
/*
* Set up pins for GPIO and SPI control, configure SSP peripheral for SPI, and
* set our own default register configuration.
*/
void max2837_setup(void)
{
LOG("# max2837_setup\n");
#if !defined TEST
/* Configure XCVR_CTL GPIO pins. */
#ifdef JELLYBEAN
scu_pinmux(SCU_XCVR_RXHP, SCU_GPIO_FAST);
scu_pinmux(SCU_XCVR_B1, SCU_GPIO_FAST);
scu_pinmux(SCU_XCVR_B2, SCU_GPIO_FAST);
scu_pinmux(SCU_XCVR_B3, SCU_GPIO_FAST);
scu_pinmux(SCU_XCVR_B4, SCU_GPIO_FAST);
scu_pinmux(SCU_XCVR_B5, SCU_GPIO_FAST);
scu_pinmux(SCU_XCVR_B6, SCU_GPIO_FAST);
scu_pinmux(SCU_XCVR_B7, SCU_GPIO_FAST);
#endif
scu_pinmux(SCU_XCVR_ENABLE, SCU_GPIO_FAST);
scu_pinmux(SCU_XCVR_RXENABLE, SCU_GPIO_FAST);
scu_pinmux(SCU_XCVR_TXENABLE, SCU_GPIO_FAST);
/* Set GPIO pins as outputs. */
GPIO2_DIR |= (PIN_XCVR_ENABLE | PIN_XCVR_RXENABLE | PIN_XCVR_TXENABLE);
#ifdef JELLYBEAN
GPIO_DIR(PORT_XCVR_RXHP) |= PIN_XCVR_RXHP;
GPIO_DIR(PORT_XCVR_B) |=
PIN_XCVR_B1
| PIN_XCVR_B2
| PIN_XCVR_B3
| PIN_XCVR_B4
| PIN_XCVR_B5
| PIN_XCVR_B6
| PIN_XCVR_B7
;
#endif
max2837_mode_shutdown();
#ifdef JELLYBEAN
gpio_set(PORT_XCVR_RXHP, PIN_XCVR_RXHP);
gpio_set(PORT_XCVR_B,
PIN_XCVR_B1
| PIN_XCVR_B2
| PIN_XCVR_B3
| PIN_XCVR_B4
| PIN_XCVR_B5
| PIN_XCVR_B6
| PIN_XCVR_B7
);
#endif
#endif
max2837_init();
LOG("# max2837_init done\n");
/* Use SPI control instead of B1-B7 pins for gain settings. */
set_MAX2837_TXVGA_GAIN_SPI_EN(1);
set_MAX2837_TXVGA_GAIN_MSB_SPI_EN(1);
//set_MAX2837_TXVGA_GAIN(0x3f); /* maximum attenuation */
set_MAX2837_TXVGA_GAIN(0x00); /* minimum attenuation */
set_MAX2837_VGAMUX_enable(1);
set_MAX2837_VGA_EN(1);
set_MAX2837_HPC_RXGAIN_EN(0);
set_MAX2837_HPC_STOP(MAX2837_STOP_1K);
set_MAX2837_LNAgain_SPI_EN(1);
set_MAX2837_LNAgain(MAX2837_LNAgain_MAX); /* maximum gain */
set_MAX2837_VGAgain_SPI_EN(1);
set_MAX2837_VGA(0x18); /* reasonable gain for noisy 2.4GHz environment */
/* maximum rx output common-mode voltage */
set_MAX2837_BUFF_VCM(MAX2837_BUFF_VCM_1_25);
/* configure baseband filter for 8 MHz TX */
set_MAX2837_LPF_EN(1);
set_MAX2837_ModeCtrl(MAX2837_ModeCtrl_RxLPF);
set_MAX2837_FT(MAX2837_FT_5M);
max2837_regs_commit();
}
/* SPI register read. */
uint16_t max2837_spi_read(uint8_t r) {
gpio_clear(PORT_XCVR_CS, PIN_XCVR_CS);
const uint16_t value = ssp_transfer(SSP1_NUM, (uint16_t)((1 << 15) | (r << 10)));
gpio_set(PORT_XCVR_CS, PIN_XCVR_CS);
return value & 0x3ff;
}
/* SPI register write */
void max2837_spi_write(uint8_t r, uint16_t v) {
#ifdef BUS_PIRATE
LOG("{0x%02x 0x%02x]\n", 0x00 | ((uint16_t)r<<2) | ((v>>8) & 0x3),
v & 0xff);
#elif DEBUG
LOG("0x%03x -> reg%d\n", v, r);
#else
gpio_clear(PORT_XCVR_CS, PIN_XCVR_CS);
ssp_transfer(SSP1_NUM, (uint16_t)((r << 10) | (v & 0x3ff)));
gpio_set(PORT_XCVR_CS, PIN_XCVR_CS);
#endif
}
uint16_t max2837_reg_read(uint8_t r)
{
if ((max2837_regs_dirty >> r) & 0x1) {
max2837_regs[r] = max2837_spi_read(r);
};
return max2837_regs[r];
}
void max2837_reg_write(uint8_t r, uint16_t v)
{
max2837_regs[r] = v;
max2837_spi_write(r, v);
MAX2837_REG_SET_CLEAN(r);
}
/* This functions should not be needed, and might be confusing. DELETE. */
void max2837_regs_read(void)
{
;
}
static inline void max2837_reg_commit(uint8_t r)
{
max2837_reg_write(r,max2837_regs[r]);
}
void max2837_regs_commit(void)
{
int r;
for(r = 0; r < MAX2837_NUM_REGS; r++) {
if ((max2837_regs_dirty >> r) & 0x1) {
max2837_reg_commit(r);
}
}
}
void max2837_mode_shutdown(void) {
/* All circuit blocks are powered down, except the 4-wire serial bus
* and its internal programmable registers.
*/
gpio_clear(PORT_XCVR_ENABLE,
(PIN_XCVR_ENABLE | PIN_XCVR_RXENABLE | PIN_XCVR_TXENABLE));
}
void max2837_mode_standby(void) {
/* Used to enable the frequency synthesizer block while the rest of the
* device is powered down. In this mode, PLL, VCO, and LO generator
* are on, so that Tx or Rx modes can be quickly enabled from this mode.
* These and other blocks can be selectively enabled in this mode.
*/
gpio_clear(PORT_XCVR_ENABLE, (PIN_XCVR_RXENABLE | PIN_XCVR_TXENABLE));
gpio_set(PORT_XCVR_ENABLE, PIN_XCVR_ENABLE);
}
void max2837_mode_tx(void) {
/* All Tx circuit blocks are powered on. The external PA is powered on
* after a programmable delay using the on-chip PA bias DAC. The slow-
* charging Rx circuits are in a precharged “idle-off” state for fast
* Tx-to-Rx turnaround time.
*/
gpio_clear(PORT_XCVR_ENABLE, PIN_XCVR_RXENABLE);
gpio_set(PORT_XCVR_ENABLE,
(PIN_XCVR_ENABLE | PIN_XCVR_TXENABLE));
}
void max2837_mode_rx(void) {
/* All Rx circuit blocks are powered on and active. Antenna signal is
* applied; RF is downconverted, filtered, and buffered at Rx BB I and Q
* outputs. The slow- charging Tx circuits are in a precharged “idle-off”
* state for fast Rx-to-Tx turnaround time.
*/
gpio_clear(PORT_XCVR_ENABLE, PIN_XCVR_TXENABLE);
gpio_set(PORT_XCVR_ENABLE,
(PIN_XCVR_ENABLE | PIN_XCVR_RXENABLE));
}
max2837_mode_t max2837_mode(void) {
if( gpio_get(PORT_XCVR_ENABLE, PIN_XCVR_ENABLE) ) {
if( gpio_get(PORT_XCVR_ENABLE, PIN_XCVR_TXENABLE) ) {
return MAX2837_MODE_TX;
} else if( gpio_get(PORT_XCVR_ENABLE, PIN_XCVR_RXENABLE) ) {
return MAX2837_MODE_RX;
} else {
return MAX2837_MODE_STANDBY;
}
} else {
return MAX2837_MODE_SHUTDOWN;
}
}
void max2837_set_mode(const max2837_mode_t new_mode) {
switch(new_mode) {
case MAX2837_MODE_SHUTDOWN:
max2837_mode_shutdown();
break;
case MAX2837_MODE_STANDBY:
max2837_mode_standby();
break;
case MAX2837_MODE_TX:
max2837_mode_tx();
break;
case MAX2837_MODE_RX:
max2837_mode_rx();
break;
default:
break;
}
}
void max2837_start(void)
{
LOG("# max2837_start\n");
set_MAX2837_EN_SPI(1);
max2837_regs_commit();
#if !defined TEST
max2837_mode_standby();
#endif
}
void max2837_tx(void)
{
LOG("# max2837_tx\n");
#if !defined TEST
set_MAX2837_ModeCtrl(MAX2837_ModeCtrl_TxLPF);
max2837_regs_commit();
max2837_mode_tx();
#endif
}
void max2837_rx(void)
{
LOG("# max2837_rx\n");
set_MAX2837_ModeCtrl(MAX2837_ModeCtrl_RxLPF);
max2837_regs_commit();
#if !defined TEST
max2837_mode_rx();
#endif
}
void max2837_stop(void)
{
LOG("# max2837_stop\n");
set_MAX2837_EN_SPI(0);
max2837_regs_commit();
#if !defined TEST
max2837_mode_shutdown();
#endif
}
void max2837_set_frequency(uint32_t freq)
{
uint8_t band;
uint8_t lna_band;
uint32_t div_frac;
uint32_t div_int;
uint32_t div_rem;
uint32_t div_cmp;
int i;
/* Select band. Allow tuning outside specified bands. */
if (freq < 2400000000U) {
band = MAX2837_LOGEN_BSW_2_3;
lna_band = MAX2837_LNAband_2_4;
}
else if (freq < 2500000000U) {
band = MAX2837_LOGEN_BSW_2_4;
lna_band = MAX2837_LNAband_2_4;
}
else if (freq < 2600000000U) {
band = MAX2837_LOGEN_BSW_2_5;
lna_band = MAX2837_LNAband_2_6;
}
else {
band = MAX2837_LOGEN_BSW_2_6;
lna_band = MAX2837_LNAband_2_6;
}
LOG("# max2837_set_frequency %ld, band %d, lna band %d\n",
freq, band, lna_band);
/* ASSUME 40MHz PLL. Ratio = F*(4/3)/40,000,000 = F/30,000,000 */
div_int = freq / 30000000;
div_rem = freq % 30000000;
div_frac = 0;
div_cmp = 30000000;
for( i = 0; i < 20; i++) {
div_frac <<= 1;
div_cmp >>= 1;
if (div_rem > div_cmp) {
div_frac |= 0x1;
div_rem -= div_cmp;
}
}
LOG("# int %ld, frac %ld\n", div_int, div_frac);
/* Band settings */
set_MAX2837_LOGEN_BSW(band);
set_MAX2837_LNAband(lna_band);
/* Write order matters here, so commit INT and FRAC_HI before
* committing FRAC_LO, which is the trigger for VCO
* auto-select. TODO - it's cleaner this way, but it would be
* faster to explicitly commit the registers explicitly so the
* dirty bits aren't scanned twice. */
set_MAX2837_SYN_INT(div_int);
set_MAX2837_SYN_FRAC_HI((div_frac >> 10) & 0x3ff);
max2837_regs_commit();
set_MAX2837_SYN_FRAC_LO(div_frac & 0x3ff);
max2837_regs_commit();
}
typedef struct {
uint32_t bandwidth_hz;
uint32_t ft;
} max2837_ft_t;
static const max2837_ft_t max2837_ft[] = {
{ 1750000, MAX2837_FT_1_75M },
{ 2500000, MAX2837_FT_2_5M },
{ 3500000, MAX2837_FT_3_5M },
{ 5000000, MAX2837_FT_5M },
{ 5500000, MAX2837_FT_5_5M },
{ 6000000, MAX2837_FT_6M },
{ 7000000, MAX2837_FT_7M },
{ 8000000, MAX2837_FT_8M },
{ 9000000, MAX2837_FT_9M },
{ 10000000, MAX2837_FT_10M },
{ 12000000, MAX2837_FT_12M },
{ 14000000, MAX2837_FT_14M },
{ 15000000, MAX2837_FT_15M },
{ 20000000, MAX2837_FT_20M },
{ 24000000, MAX2837_FT_24M },
{ 28000000, MAX2837_FT_28M },
{ 0, 0 },
};
bool max2837_set_lpf_bandwidth(const uint32_t bandwidth_hz) {
const max2837_ft_t* p = max2837_ft;
while( p->bandwidth_hz != 0 ) {
if( p->bandwidth_hz >= bandwidth_hz ) {
break;
}
p++;
}
if( p->bandwidth_hz != 0 ) {
set_MAX2837_FT(p->ft);
max2837_regs_commit();
return true;
} else {
return false;
}
}
bool max2837_set_lna_gain(const uint32_t gain_db) {
uint16_t val;
switch(gain_db){
case 40:
val = MAX2837_LNAgain_MAX;
break;
case 32:
val = MAX2837_LNAgain_M8;
break;
case 24:
val = MAX2837_LNAgain_M16;
break;
case 16:
val = MAX2837_LNAgain_M24;
break;
case 8:
val = MAX2837_LNAgain_M32;
break;
case 0:
val = MAX2837_LNAgain_M40;
break;
default:
return false;
}
set_MAX2837_LNAgain(val);
max2837_reg_commit(1);
return true;
}
bool max2837_set_vga_gain(const uint32_t gain_db) {
if( (gain_db & 0x1) || gain_db > 62)/* 0b11111*2 */
return false;
set_MAX2837_VGA( 31-(gain_db >> 1) );
max2837_reg_commit(5);
return true;
}
bool max2837_set_txvga_gain(const uint32_t gain_db) {
uint16_t val=0;
if(gain_db <16){
val = 31-gain_db;
val |= (1 << 5); // bit6: 16db
} else{
val = 31-(gain_db-16);
}
set_MAX2837_TXVGA_GAIN(val);
max2837_reg_commit(29);
return true;
}
#ifdef TEST
int main(int ac, char **av)
{
max2837_setup();
max2837_set_frequency(2441000000);
max2837_start();
max2837_tx();
max2837_stop();
}
#endif //TEST

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#ifndef __MAX2837_H
#define __MAX2837_H
#include <stdint.h>
#include <stdbool.h>
/* TODO - make this a private header for max2837.c only, make new max2837.h */
/* 32 registers, each containing 10 bits of data. */
#define MAX2837_NUM_REGS 32
#define MAX2837_DATA_REGS_MAX_VALUE 1024
/* TODO - these externs will be local to max2837.c ... don't define here? */
extern uint16_t max2837_regs[MAX2837_NUM_REGS];
extern uint32_t max2837_regs_dirty;
#define MAX2837_REG_SET_CLEAN(r) max2837_regs_dirty &= ~(1UL<<r)
#define MAX2837_REG_SET_DIRTY(r) max2837_regs_dirty |= (1UL<<r)
/* Initialize chip. */
extern void max2837_init(void);
extern void max2837_setup(void);
/* Read a register via SPI. Save a copy to memory and return
* value. Mark clean. */
extern uint16_t max2837_reg_read(uint8_t r);
/* Write value to register via SPI and save a copy to memory. Mark
* clean. */
extern void max2837_reg_write(uint8_t r, uint16_t v);
/* Read all registers from chip and copy to memory. Mark all clean. */
extern void max2837_regs_read(void);
/* Write all dirty registers via SPI from memory. Mark all clean. Some
* operations require registers to be written in a certain order. Use
* provided routines for those operations. */
extern void max2837_regs_commit(void);
typedef enum {
MAX2837_MODE_SHUTDOWN,
MAX2837_MODE_STANDBY,
MAX2837_MODE_TX,
MAX2837_MODE_RX
} max2837_mode_t;
void max2837_mode_shutdown(void);
void max2837_mode_standby(void);
void max2837_mode_tx(void);
void max2837_mode_rx(void);
max2837_mode_t max2837_mode(void);
void max2837_set_mode(const max2837_mode_t new_mode);
/* Turn on/off all chip functions. Does not control oscillator and CLKOUT */
extern void max2837_start(void);
extern void max2837_stop(void);
/* Set frequency in Hz. Frequency setting is a multi-step function
* where order of register writes matters. */
extern void max2837_set_frequency(uint32_t freq);
bool max2837_set_lpf_bandwidth(const uint32_t bandwidth_hz);
bool max2837_set_lna_gain(const uint32_t gain_db);
bool max2837_set_vga_gain(const uint32_t gain_db);
bool max2837_set_txvga_gain(const uint32_t gain_db);
extern void max2837_tx(void);
extern void max2837_rx(void);
#endif // __MAX2837_H

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/*
* Copyright 2012 Jared Boone
* Copyright 2013 Benjamin Vernoux
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include "rf_path.h"
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h>
#include <hackrf_core.h>
#include <rffc5071.h>
#include <max2837.h>
#include <max5864.h>
#include <sgpio.h>
#if (defined JAWBREAKER || defined HACKRF_ONE)
/*
* RF switches on Jawbreaker are controlled by General Purpose Outputs (GPO) on
* the RFFC5072.
*
* On HackRF One, the same signals are controlled by GPIO on the LPC.
* SWITCHCTRL_NO_TX_AMP_PWR and SWITCHCTRL_NO_RX_AMP_PWR are not normally used
* on HackRF One as the amplifier power is instead controlled only by
* SWITCHCTRL_AMP_BYPASS.
*/
#define SWITCHCTRL_NO_TX_AMP_PWR (1 << 0) /* GPO1 turn off TX amp power */
#define SWITCHCTRL_AMP_BYPASS (1 << 1) /* GPO2 bypass amp section */
#define SWITCHCTRL_TX (1 << 2) /* GPO3 1 for TX mode, 0 for RX mode */
#define SWITCHCTRL_MIX_BYPASS (1 << 3) /* GPO4 bypass RFFC5072 mixer section */
#define SWITCHCTRL_HP (1 << 4) /* GPO5 1 for high-pass, 0 for low-pass */
#define SWITCHCTRL_NO_RX_AMP_PWR (1 << 5) /* GPO6 turn off RX amp power */
/*
GPO6 GPO5 GPO4 GPO3 GPO2 GPO1
!RXAMP HP MIXBP TX AMPBP !TXAMP Mix mode Amp mode
1 X 1 1 1 1 TX bypass Bypass
1 X 1 1 0 0 TX bypass TX amplified
1 1 0 1 1 1 TX high Bypass
1 1 0 1 0 0 TX high TX amplified
1 0 0 1 1 1 TX low Bypass
1 0 0 1 0 0 TX low TX amplified
1 X 1 0 1 1 RX bypass Bypass
0 X 1 0 0 1 RX bypass RX amplified
1 1 0 0 1 1 RX high Bypass
0 1 0 0 0 1 RX high RX amplified
1 0 0 0 1 1 RX low Bypass
0 0 0 0 0 1 RX low RX amplified
*/
/*
* Safe (initial) switch settings turn off both amplifiers and enable both amp
* bypass and mixer bypass.
*/
#define SWITCHCTRL_SAFE (SWITCHCTRL_NO_TX_AMP_PWR | SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_TX | SWITCHCTRL_MIX_BYPASS | SWITCHCTRL_HP | SWITCHCTRL_NO_RX_AMP_PWR)
#endif
uint8_t switchctrl = SWITCHCTRL_SAFE;
/*
* Antenna port power on HackRF One is controlled by GPO1 on the RFFC5072.
* This is the only thing we use RFFC5072 GPO for on HackRF One. The value of
* SWITCHCTRL_NO_ANT_PWR does not correspond to the GPO1 bit in the gpo
* register.
*/
#define SWITCHCTRL_ANT_PWR (1 << 6) /* turn on antenna port power */
#ifdef HACKRF_ONE
static void switchctrl_set_hackrf_one(uint8_t ctrl) {
if (ctrl & SWITCHCTRL_TX) {
gpio_set(PORT_TX, PIN_TX);
gpio_clear(PORT_RX, PIN_RX);
} else {
gpio_clear(PORT_TX, PIN_TX);
gpio_set(PORT_RX, PIN_RX);
}
if (ctrl & SWITCHCTRL_MIX_BYPASS) {
gpio_set(PORT_MIX_BYPASS, PIN_MIX_BYPASS);
gpio_clear(PORT_NO_MIX_BYPASS, PIN_NO_MIX_BYPASS);
if (ctrl & SWITCHCTRL_TX) {
gpio_set(PORT_TX_MIX_BP, PIN_TX_MIX_BP);
gpio_clear(PORT_RX_MIX_BP, PIN_RX_MIX_BP);
} else {
gpio_clear(PORT_TX_MIX_BP, PIN_TX_MIX_BP);
gpio_set(PORT_RX_MIX_BP, PIN_RX_MIX_BP);
}
} else {
gpio_clear(PORT_MIX_BYPASS, PIN_MIX_BYPASS);
gpio_set(PORT_NO_MIX_BYPASS, PIN_NO_MIX_BYPASS);
gpio_clear(PORT_TX_MIX_BP, PIN_TX_MIX_BP);
gpio_clear(PORT_RX_MIX_BP, PIN_RX_MIX_BP);
}
if (ctrl & SWITCHCTRL_HP) {
gpio_set(PORT_HP, PIN_HP);
gpio_clear(PORT_LP, PIN_LP);
} else {
gpio_clear(PORT_HP, PIN_HP);
gpio_set(PORT_LP, PIN_LP);
}
if (ctrl & SWITCHCTRL_AMP_BYPASS) {
gpio_set(PORT_AMP_BYPASS, PIN_AMP_BYPASS);
gpio_clear(PORT_TX_AMP, PIN_TX_AMP);
gpio_set(PORT_NO_TX_AMP_PWR, PIN_NO_TX_AMP_PWR);
gpio_clear(PORT_RX_AMP, PIN_RX_AMP);
gpio_set(PORT_NO_RX_AMP_PWR, PIN_NO_RX_AMP_PWR);
} else if (ctrl & SWITCHCTRL_TX) {
gpio_clear(PORT_AMP_BYPASS, PIN_AMP_BYPASS);
gpio_set(PORT_TX_AMP, PIN_TX_AMP);
gpio_clear(PORT_NO_TX_AMP_PWR, PIN_NO_TX_AMP_PWR);
gpio_clear(PORT_RX_AMP, PIN_RX_AMP);
gpio_set(PORT_NO_RX_AMP_PWR, PIN_NO_RX_AMP_PWR);
} else {
gpio_clear(PORT_AMP_BYPASS, PIN_AMP_BYPASS);
gpio_clear(PORT_TX_AMP, PIN_TX_AMP);
gpio_set(PORT_NO_TX_AMP_PWR, PIN_NO_TX_AMP_PWR);
gpio_set(PORT_RX_AMP, PIN_RX_AMP);
gpio_clear(PORT_NO_RX_AMP_PWR, PIN_NO_RX_AMP_PWR);
}
/*
* These normally shouldn't be set post-Jawbreaker, but they can be
* used to explicitly turn off power to the amplifiers while AMP_BYPASS
* is unset:
*/
if (ctrl & SWITCHCTRL_NO_TX_AMP_PWR)
gpio_set(PORT_NO_TX_AMP_PWR, PIN_NO_TX_AMP_PWR);
if (ctrl & SWITCHCTRL_NO_RX_AMP_PWR)
gpio_set(PORT_NO_RX_AMP_PWR, PIN_NO_RX_AMP_PWR);
if (ctrl & SWITCHCTRL_ANT_PWR) {
rffc5071_set_gpo(0x00); /* turn on antenna power by clearing GPO1 */
} else {
rffc5071_set_gpo(0x01); /* turn off antenna power by setting GPO1 */
}
}
#endif
static void switchctrl_set(const uint8_t gpo) {
#ifdef JAWBREAKER
rffc5071_set_gpo(gpo);
#elif HACKRF_ONE
switchctrl_set_hackrf_one(gpo);
#else
(void)gpo;
#endif
}
void rf_path_pin_setup() {
#ifdef HACKRF_ONE
/* Configure RF switch control signals */
scu_pinmux(SCU_HP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_LP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_TX_MIX_BP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_NO_MIX_BYPASS, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_RX_MIX_BP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_TX_AMP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_TX, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_MIX_BYPASS, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_RX, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_NO_TX_AMP_PWR, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_AMP_BYPASS, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_RX_AMP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_NO_RX_AMP_PWR, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
/* Configure RF power supply (VAA) switch */
scu_pinmux(SCU_NO_VAA_ENABLE, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
/* Configure RF switch control signals as outputs */
GPIO0_DIR |= PIN_AMP_BYPASS;
GPIO1_DIR |= (PIN_NO_MIX_BYPASS | PIN_RX_AMP | PIN_NO_RX_AMP_PWR);
GPIO2_DIR |= (PIN_HP | PIN_LP | PIN_TX_MIX_BP | PIN_RX_MIX_BP | PIN_TX_AMP);
GPIO3_DIR |= PIN_NO_TX_AMP_PWR;
GPIO5_DIR |= (PIN_TX | PIN_MIX_BYPASS | PIN_RX);
/*
* Safe (initial) switch settings turn off both amplifiers and antenna port
* power and enable both amp bypass and mixer bypass.
*/
switchctrl_set(SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_MIX_BYPASS);
/* Configure RF power supply (VAA) switch control signal as output */
GPIO_DIR(PORT_NO_VAA_ENABLE) |= PIN_NO_VAA_ENABLE;
/* Safe state: start with VAA turned off: */
disable_rf_power();
#endif
}
void rf_path_init(void) {
ssp1_set_mode_max5864();
max5864_shutdown();
ssp1_set_mode_max2837();
max2837_setup();
max2837_start();
rffc5071_setup();
switchctrl_set(switchctrl);
}
void rf_path_set_direction(const rf_path_direction_t direction) {
/* Turn off TX and RX amplifiers, then enable based on direction and bypass state. */
switchctrl |= SWITCHCTRL_NO_TX_AMP_PWR | SWITCHCTRL_NO_RX_AMP_PWR;
switch(direction) {
case RF_PATH_DIRECTION_TX:
switchctrl |= SWITCHCTRL_TX;
if( (switchctrl & SWITCHCTRL_AMP_BYPASS) == 0 ) {
/* TX amplifier is in path, be sure to enable TX amplifier. */
switchctrl &= ~SWITCHCTRL_NO_TX_AMP_PWR;
}
rffc5071_tx();
if( switchctrl & SWITCHCTRL_MIX_BYPASS ) {
rffc5071_disable();
} else {
rffc5071_enable();
}
ssp1_set_mode_max5864();
max5864_tx();
ssp1_set_mode_max2837();
max2837_tx();
sgpio_configure(SGPIO_DIRECTION_TX);
break;
case RF_PATH_DIRECTION_RX:
switchctrl &= ~SWITCHCTRL_TX;
if( (switchctrl & SWITCHCTRL_AMP_BYPASS) == 0 ) {
/* RX amplifier is in path, be sure to enable RX amplifier. */
switchctrl &= ~SWITCHCTRL_NO_RX_AMP_PWR;
}
rffc5071_rx();
if( switchctrl & SWITCHCTRL_MIX_BYPASS ) {
rffc5071_disable();
} else {
rffc5071_enable();
}
ssp1_set_mode_max5864();
max5864_rx();
ssp1_set_mode_max2837();
max2837_rx();
sgpio_configure(SGPIO_DIRECTION_RX);
break;
case RF_PATH_DIRECTION_OFF:
default:
#ifdef HACKRF_ONE
rf_path_set_antenna(0);
#endif
rf_path_set_lna(0);
/* Set RF path to receive direction when "off" */
switchctrl &= ~SWITCHCTRL_TX;
rffc5071_disable();
ssp1_set_mode_max5864();
max5864_standby();
ssp1_set_mode_max2837();
max2837_set_mode(MAX2837_MODE_STANDBY);
sgpio_configure(SGPIO_DIRECTION_RX);
break;
}
switchctrl_set(switchctrl);
}
void rf_path_set_filter(const rf_path_filter_t filter) {
switch(filter) {
default:
case RF_PATH_FILTER_BYPASS:
switchctrl |= SWITCHCTRL_MIX_BYPASS;
rffc5071_disable();
break;
case RF_PATH_FILTER_LOW_PASS:
switchctrl &= ~(SWITCHCTRL_HP | SWITCHCTRL_MIX_BYPASS);
rffc5071_enable();
break;
case RF_PATH_FILTER_HIGH_PASS:
switchctrl &= ~SWITCHCTRL_MIX_BYPASS;
switchctrl |= SWITCHCTRL_HP;
rffc5071_enable();
break;
}
switchctrl_set(switchctrl);
}
void rf_path_set_lna(const uint_fast8_t enable) {
if( enable ) {
if( switchctrl & SWITCHCTRL_TX ) {
/* AMP_BYPASS=0, NO_RX_AMP_PWR=1, NO_TX_AMP_PWR=0 */
switchctrl |= SWITCHCTRL_NO_RX_AMP_PWR;
switchctrl &= ~(SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_NO_TX_AMP_PWR);
} else {
/* AMP_BYPASS=0, NO_RX_AMP_PWR=0, NO_TX_AMP_PWR=1 */
switchctrl |= SWITCHCTRL_NO_TX_AMP_PWR;
switchctrl &= ~(SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_NO_RX_AMP_PWR);
}
} else {
/* AMP_BYPASS=1, NO_RX_AMP_PWR=1, NO_TX_AMP_PWR=1 */
switchctrl |= SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_NO_TX_AMP_PWR | SWITCHCTRL_NO_RX_AMP_PWR;
}
switchctrl_set(switchctrl);
}
/* antenna port power control */
void rf_path_set_antenna(const uint_fast8_t enable) {
if (enable) {
switchctrl |= SWITCHCTRL_ANT_PWR;
} else {
switchctrl &= ~(SWITCHCTRL_ANT_PWR);
}
switchctrl_set(switchctrl);
}

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/*
* Copyright 2012 Michael Ossmann
* Copyright 2014 Jared Boone <jared@sharebrained.com>
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
/*
* 'gcc -DTEST -DDEBUG -O2 -o test rffc5071.c' prints out what test
* program would do if it had a real spi library
*/
/*
* The actual part on Jawbreaker is the RFFC5072, not the RFFC5071, but the
* RFFC5071 may be installed instead. The only difference between the parts is
* that the RFFC5071 includes a second mixer.
*/
#include <stdint.h>
#include <string.h>
#include "rffc5071.h"
#include "rffc5071_regs.def" // private register def macros
#if (defined DEBUG)
#include <stdio.h>
#define LOG printf
#else
#define LOG(x,...)
#include <libopencm3/lpc43xx/ssp.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/gpio.h>
#include "hackrf_core.h"
#endif
/* Default register values. */
static uint16_t rffc5071_regs_default[RFFC5071_NUM_REGS] = {
0xbefa, /* 00 */
0x4064, /* 01 */
0x9055, /* 02 */
0x2d02, /* 03 */
0xacbf, /* 04 */
0xacbf, /* 05 */
0x0028, /* 06 */
0x0028, /* 07 */
0xff00, /* 08 */
0x8220, /* 09 */
0x0202, /* 0A */
0x4800, /* 0B */
0x1a94, /* 0C */
0xd89d, /* 0D */
0x8900, /* 0E */
0x1e84, /* 0F */
0x89d8, /* 10 */
0x9d00, /* 11 */
0x2a20, /* 12 */
0x0000, /* 13 */
0x0000, /* 14 */
0x0000, /* 15 */
0x0000, /* 16 */
0x4900, /* 17 */
0x0281, /* 18 */
0xf00f, /* 19 */
0x0000, /* 1A */
0x0000, /* 1B */
0xc840, /* 1C */
0x1000, /* 1D */
0x0005, /* 1E */ };
uint16_t rffc5071_regs[RFFC5071_NUM_REGS];
/* Mark all regsisters dirty so all will be written at init. */
uint32_t rffc5071_regs_dirty = 0x7fffffff;
/* Set up all registers according to defaults specified in docs. */
void rffc5071_init(void)
{
LOG("# rffc5071_init\n");
memcpy(rffc5071_regs, rffc5071_regs_default, sizeof(rffc5071_regs));
rffc5071_regs_dirty = 0x7fffffff;
/* Write default register values to chip. */
rffc5071_regs_commit();
}
/*
* Set up pins for GPIO and SPI control, configure SSP peripheral for SPI, and
* set our own default register configuration.
*/
void rffc5071_setup(void)
{
rffc5071_init();
LOG("# rffc5071_setup\n");
#if !defined TEST
/* Configure GPIO pins. */
scu_pinmux(SCU_MIXER_ENX, SCU_GPIO_FAST);
scu_pinmux(SCU_MIXER_SCLK, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_MIXER_SDATA, SCU_GPIO_FAST);
scu_pinmux(SCU_MIXER_RESETX, SCU_GPIO_FAST);
/* Set GPIO pins as outputs. */
GPIO_DIR(PORT_MIXER_ENX) |= PIN_MIXER_ENX;
GPIO_DIR(PORT_MIXER_SCLK) |= PIN_MIXER_SCLK;
GPIO_DIR(PORT_MIXER_SDATA) |= PIN_MIXER_SDATA;
GPIO_DIR(PORT_MIXER_RESETX) |= PIN_MIXER_RESETX;
/* set to known state */
gpio_set(PORT_MIXER_ENX, PIN_MIXER_ENX); /* active low */
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
gpio_clear(PORT_MIXER_SDATA, PIN_MIXER_SDATA);
gpio_set(PORT_MIXER_RESETX, PIN_MIXER_RESETX); /* active low */
#endif
/* initial setup */
/* put zeros in freq contol registers */
set_RFFC5071_P2N(0);
set_RFFC5071_P2LODIV(0);
set_RFFC5071_P2PRESC(0);
set_RFFC5071_P2VCOSEL(0);
set_RFFC5071_P2N(0);
set_RFFC5071_P2LODIV(0);
set_RFFC5071_P2PRESC(0);
set_RFFC5071_P2VCOSEL(0);
set_RFFC5071_P2N(0);
set_RFFC5071_P2LODIV(0);
set_RFFC5071_P2PRESC(0);
set_RFFC5071_P2VCOSEL(0);
/* set ENBL and MODE to be configured via 3-wire interface,
* not control pins. */
set_RFFC5071_SIPIN(1);
/* GPOs are active at all times */
set_RFFC5071_GATE(1);
rffc5071_regs_commit();
}
void serial_delay(void)
{
uint32_t i;
for (i = 0; i < 2; i++)
__asm__("nop");
}
/* SPI register read.
*
* Send 9 bits:
* first bit is ignored,
* second bit is one for read operation,
* next 7 bits are register address.
* Then receive 16 bits (register value).
*/
uint16_t rffc5071_spi_read(uint8_t r) {
int bits = 9;
int msb = 1 << (bits -1);
uint32_t data = 0x80 | (r & 0x7f);
#if DEBUG
LOG("reg%d = 0\n", r);
return 0;
#else
/* make sure everything is starting in the correct state */
gpio_set(PORT_MIXER_ENX, PIN_MIXER_ENX);
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
gpio_clear(PORT_MIXER_SDATA, PIN_MIXER_SDATA);
/*
* The device requires two clocks while ENX is high before a serial
* transaction. This is not clearly documented.
*/
serial_delay();
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
serial_delay();
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
/* start transaction by bringing ENX low */
gpio_clear(PORT_MIXER_ENX, PIN_MIXER_ENX);
while (bits--) {
if (data & msb)
gpio_set(PORT_MIXER_SDATA, PIN_MIXER_SDATA);
else
gpio_clear(PORT_MIXER_SDATA, PIN_MIXER_SDATA);
data <<= 1;
serial_delay();
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
}
serial_delay();
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
bits = 16;
data = 0;
/* set SDATA line as input */
GPIO_DIR(PORT_MIXER_SDATA) &= ~PIN_MIXER_SDATA;
while (bits--) {
data <<= 1;
serial_delay();
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
if (MIXER_SDATA_STATE)
data |= 1;
}
/* set SDATA line as output */
GPIO_DIR(PORT_MIXER_SDATA) |= PIN_MIXER_SDATA;
serial_delay();
gpio_set(PORT_MIXER_ENX, PIN_MIXER_ENX);
/*
* The device requires a clock while ENX is high after a serial
* transaction. This is not clearly documented.
*/
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
return data;
#endif /* DEBUG */
}
/* SPI register write
*
* Send 25 bits:
* first bit is ignored,
* second bit is zero for write operation,
* next 7 bits are register address,
* next 16 bits are register value.
*/
void rffc5071_spi_write(uint8_t r, uint16_t v) {
#if DEBUG
LOG("0x%04x -> reg%d\n", v, r);
#else
int bits = 25;
int msb = 1 << (bits -1);
uint32_t data = ((r & 0x7f) << 16) | v;
/* make sure everything is starting in the correct state */
gpio_set(PORT_MIXER_ENX, PIN_MIXER_ENX);
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
gpio_clear(PORT_MIXER_SDATA, PIN_MIXER_SDATA);
/*
* The device requires two clocks while ENX is high before a serial
* transaction. This is not clearly documented.
*/
serial_delay();
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
serial_delay();
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
/* start transaction by bringing ENX low */
gpio_clear(PORT_MIXER_ENX, PIN_MIXER_ENX);
while (bits--) {
if (data & msb)
gpio_set(PORT_MIXER_SDATA, PIN_MIXER_SDATA);
else
gpio_clear(PORT_MIXER_SDATA, PIN_MIXER_SDATA);
data <<= 1;
serial_delay();
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
}
gpio_set(PORT_MIXER_ENX, PIN_MIXER_ENX);
/*
* The device requires a clock while ENX is high after a serial
* transaction. This is not clearly documented.
*/
serial_delay();
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
serial_delay();
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
#endif
}
uint16_t rffc5071_reg_read(uint8_t r)
{
/* Readback register is not cached. */
if (r == RFFC5071_READBACK_REG)
return rffc5071_spi_read(r);
/* Discard uncommited write when reading. This shouldn't
* happen, and probably has not been tested. */
if ((rffc5071_regs_dirty >> r) & 0x1) {
rffc5071_regs[r] = rffc5071_spi_read(r);
};
return rffc5071_regs[r];
}
void rffc5071_reg_write(uint8_t r, uint16_t v)
{
rffc5071_regs[r] = v;
rffc5071_spi_write(r, v);
RFFC5071_REG_SET_CLEAN(r);
}
static inline void rffc5071_reg_commit(uint8_t r)
{
rffc5071_reg_write(r,rffc5071_regs[r]);
}
void rffc5071_regs_commit(void)
{
int r;
for(r = 0; r < RFFC5071_NUM_REGS; r++) {
if ((rffc5071_regs_dirty >> r) & 0x1) {
rffc5071_reg_commit(r);
}
}
}
void rffc5071_tx(void) {
LOG("# rffc5071_tx\n");
set_RFFC5071_ENBL(0);
set_RFFC5071_FULLD(0);
set_RFFC5071_MODE(1); /* mixer 2 used for both RX and TX */
rffc5071_regs_commit();
}
void rffc5071_rx(void) {
LOG("# rfc5071_rx\n");
set_RFFC5071_ENBL(0);
set_RFFC5071_FULLD(0);
set_RFFC5071_MODE(1); /* mixer 2 used for both RX and TX */
rffc5071_regs_commit();
}
/*
* This function turns on both mixer (full-duplex) on the RFFC5071, but our
* current hardware designs do not support full-duplex operation.
*/
void rffc5071_rxtx(void) {
LOG("# rfc5071_rxtx\n");
set_RFFC5071_ENBL(0);
set_RFFC5071_FULLD(1); /* mixer 1 and mixer 2 (RXTX) */
rffc5071_regs_commit();
rffc5071_enable();
}
void rffc5071_disable(void) {
LOG("# rfc5071_disable\n");
set_RFFC5071_ENBL(0);
rffc5071_regs_commit();
}
void rffc5071_enable(void) {
LOG("# rfc5071_enable\n");
set_RFFC5071_ENBL(1);
rffc5071_regs_commit();
}
#define LO_MAX 5400
#define REF_FREQ 50
#define FREQ_ONE_MHZ (1000*1000)
/* configure frequency synthesizer in integer mode (lo in MHz) */
uint64_t rffc5071_config_synth_int(uint16_t lo) {
uint8_t lodiv;
uint16_t fvco;
uint8_t fbkdiv;
uint16_t n;
uint64_t tune_freq_hz;
uint16_t p1nmsb;
uint8_t p1nlsb;
LOG("# config_synth_int\n");
/* Calculate n_lo */
uint8_t n_lo = 0;
uint16_t x = LO_MAX / lo;
while ((x > 1) && (n_lo < 5)) {
n_lo++;
x >>= 1;
}
lodiv = 1 << n_lo;
fvco = lodiv * lo;
/* higher divider and charge pump current required above
* 3.2GHz. Programming guide says these values (fbkdiv, n,
* maybe pump?) can be changed back after enable in order to
* improve phase noise, since the VCO will already be stable
* and will be unaffected. */
if (fvco > 3200) {
fbkdiv = 4;
set_RFFC5071_PLLCPL(3);
} else {
fbkdiv = 2;
set_RFFC5071_PLLCPL(2);
}
uint64_t tmp_n = ((uint64_t)fvco << 29ULL) / (fbkdiv*REF_FREQ) ;
n = tmp_n >> 29ULL;
p1nmsb = (tmp_n >> 13ULL) & 0xffff;
p1nlsb = (tmp_n >> 5ULL) & 0xff;
tune_freq_hz = (REF_FREQ * (tmp_n >> 5ULL) * fbkdiv * FREQ_ONE_MHZ)
/ (lodiv * (1 << 24ULL));
LOG("# lo=%d n_lo=%d lodiv=%d fvco=%d fbkdiv=%d n=%d tune_freq_hz=%d\n",
lo, n_lo, lodiv, fvco, fbkdiv, n, tune_freq);
/* Path 1 */
set_RFFC5071_P1LODIV(n_lo);
set_RFFC5071_P1N(n);
set_RFFC5071_P1PRESC(fbkdiv >> 1);
set_RFFC5071_P1NMSB(p1nmsb);
set_RFFC5071_P1NLSB(p1nlsb);
/* Path 2 */
set_RFFC5071_P2LODIV(n_lo);
set_RFFC5071_P2N(n);
set_RFFC5071_P2PRESC(fbkdiv >> 1);
set_RFFC5071_P2NMSB(p1nmsb);
set_RFFC5071_P2NLSB(p1nlsb);
rffc5071_regs_commit();
return tune_freq_hz;
}
/* !!!!!!!!!!! hz is currently ignored !!!!!!!!!!! */
uint64_t rffc5071_set_frequency(uint16_t mhz) {
uint32_t tune_freq;
rffc5071_disable();
tune_freq = rffc5071_config_synth_int(mhz);
rffc5071_enable();
return tune_freq;
}
void rffc5071_set_gpo(uint8_t gpo)
{
/* We set GPO for both paths just in case. */
set_RFFC5071_P1GPO(gpo);
set_RFFC5071_P2GPO(gpo);
rffc5071_regs_commit();
}
#ifdef TEST
int main(int ac, char **av)
{
rffc5071_setup();
rffc5071_tx(0);
rffc5071_set_frequency(500, 0);
rffc5071_set_frequency(525, 0);
rffc5071_set_frequency(550, 0);
rffc5071_set_frequency(1500, 0);
rffc5071_set_frequency(1525, 0);
rffc5071_set_frequency(1550, 0);
rffc5071_disable();
rffc5071_rx(0);
rffc5071_disable();
rffc5071_rxtx();
rffc5071_disable();
}
#endif //TEST

142
SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/sgpio_dma.c
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@ -1,142 +0,0 @@
/*
* Copyright 2013 Jared Boone <jared@sharebrained.com>
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <sgpio_dma.h>
#include <libopencm3/lpc43xx/creg.h>
#include <libopencm3/lpc43xx/gpdma.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/sgpio.h>
#include <sgpio.h>
#include <gpdma.h>
void sgpio_dma_configure_lli(
gpdma_lli_t* const lli,
const size_t lli_count,
const bool direction_transmit,
void* const buffer,
const size_t transfer_bytes
) {
const size_t bytes_per_word = 4;
const size_t transfer_words = (transfer_bytes + bytes_per_word - 1) / bytes_per_word;
gpdma_lli_create_loop(lli, lli_count);
for(size_t i=0; i<lli_count; i++) {
void* const peripheral_address = (void*)&SGPIO_REG_SS(0);
void* const memory_address = buffer + (transfer_words * bytes_per_word * i);
const uint_fast8_t source_master = direction_transmit ? 1 : 0;
const uint_fast8_t destination_master = direction_transmit ? 0 : 1;
const uint_fast8_t lli_fetch_master = direction_transmit ? 0 : 1;
lli[i].csrcaddr = direction_transmit ? memory_address : peripheral_address;
lli[i].cdestaddr = direction_transmit ? peripheral_address : memory_address;
lli[i].clli = (lli[i].clli & ~GPDMA_CLLI_LM_MASK) | GPDMA_CLLI_LM(lli_fetch_master);
lli[i].ccontrol =
GPDMA_CCONTROL_TRANSFERSIZE(transfer_words) |
GPDMA_CCONTROL_SBSIZE(0) |
GPDMA_CCONTROL_DBSIZE(0) |
GPDMA_CCONTROL_SWIDTH(2) |
GPDMA_CCONTROL_DWIDTH(2) |
GPDMA_CCONTROL_S(source_master) |
GPDMA_CCONTROL_D(destination_master) |
GPDMA_CCONTROL_SI(direction_transmit ? 1 : 0) |
GPDMA_CCONTROL_DI(direction_transmit ? 0 : 1) |
GPDMA_CCONTROL_PROT1(0) |
GPDMA_CCONTROL_PROT2(0) |
GPDMA_CCONTROL_PROT3(0) |
GPDMA_CCONTROL_I(0)
;
}
}
static void sgpio_dma_enable(const uint_fast8_t channel, const gpdma_lli_t* const lli, const bool direction_transmit) {
gpdma_channel_disable(channel);
gpdma_channel_interrupt_tc_clear(channel);
gpdma_channel_interrupt_error_clear(channel);
GPDMA_CSRCADDR(channel) = (uint32_t)lli->csrcaddr;
GPDMA_CDESTADDR(channel) = (uint32_t)lli->cdestaddr;
GPDMA_CLLI(channel) = (uint32_t)lli->clli;
GPDMA_CCONTROL(channel) = lli->ccontrol;
/* 1: Memory -> Peripheral
* 2: Peripheral -> Memory */
const uint_fast8_t flowcntrl = direction_transmit ? 1 : 2;
GPDMA_CCONFIG(channel) =
GPDMA_CCONFIG_E(0) |
GPDMA_CCONFIG_SRCPERIPHERAL(0) |
GPDMA_CCONFIG_DESTPERIPHERAL(0) |
GPDMA_CCONFIG_FLOWCNTRL(flowcntrl) |
GPDMA_CCONFIG_IE(1) |
GPDMA_CCONFIG_ITC(1) |
GPDMA_CCONFIG_L(0) |
GPDMA_CCONFIG_H(0)
;
gpdma_channel_enable(channel);
}
void sgpio_dma_init() {
/* DMA peripheral/source 0, option 2 (SGPIO14) -- BREQ */
CREG_DMAMUX &= ~(CREG_DMAMUX_DMAMUXPER0_MASK);
CREG_DMAMUX |= CREG_DMAMUX_DMAMUXPER0(0x2);
// Disable sync, maybe it is causing max speed (10MT/sec) glitches?
//GPDMA_DMACSYNC = (1 << 0);
//GPDMA_SYNC = GPDMA_SYNC_DMACSYNC(0xFFFF); // TODO: Don't do this, I'm just going nuts here.
gpdma_controller_enable();
}
static const uint_fast8_t dma_channel_sgpio = 0;
void sgpio_dma_rx_start(const gpdma_lli_t* const start_lli) {
sgpio_dma_enable(dma_channel_sgpio, start_lli, false);
}
void sgpio_dma_tx_start(const gpdma_lli_t* const start_lli) {
sgpio_dma_enable(dma_channel_sgpio, start_lli, true);
}
void sgpio_dma_irq_tc_acknowledge() {
gpdma_channel_interrupt_tc_clear(dma_channel_sgpio);
}
void sgpio_dma_stop() {
gpdma_channel_disable(dma_channel_sgpio);
}
size_t sgpio_dma_current_transfer_index(
const gpdma_lli_t* const lli,
const size_t lli_count
) {
const uint32_t next_lli = GPDMA_CLLI(dma_channel_sgpio);
for(size_t i=0; i<lli_count; i++) {
if( lli[i].clli == next_lli ) {
return i;
}
}
return 0;
}

314
SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/common/si5351c.c
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@ -1,314 +0,0 @@
/*
* Copyright 2012 Michael Ossmann <mike@ossmann.com>
* Copyright 2012 Jared Boone <jared@sharebrained.com>
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include "si5351c.h"
#include <libopencm3/lpc43xx/i2c.h>
enum pll_sources active_clock_source;
/* FIXME return i2c0 status from each function */
/* write to single register */
void si5351c_write_single(uint8_t reg, uint8_t val)
{
i2c0_tx_start();
i2c0_tx_byte(SI5351C_I2C_ADDR | I2C_WRITE);
i2c0_tx_byte(reg);
i2c0_tx_byte(val);
i2c0_stop();
}
/* read single register */
uint8_t si5351c_read_single(uint8_t reg)
{
uint8_t val;
/* set register address with write */
i2c0_tx_start();
i2c0_tx_byte(SI5351C_I2C_ADDR | I2C_WRITE);
i2c0_tx_byte(reg);
/* read the value */
i2c0_tx_start();
i2c0_tx_byte(SI5351C_I2C_ADDR | I2C_READ);
val = i2c0_rx_byte();
i2c0_stop();
return val;
}
/*
* Write to one or more contiguous registers. data[0] should be the first
* register number, one or more values follow.
*/
void si5351c_write(uint8_t* const data, const uint_fast8_t data_count)
{
uint_fast8_t i;
i2c0_tx_start();
i2c0_tx_byte(SI5351C_I2C_ADDR | I2C_WRITE);
for (i = 0; i < data_count; i++)
i2c0_tx_byte(data[i]);
i2c0_stop();
}
/* Disable all CLKx outputs. */
void si5351c_disable_all_outputs()
{
uint8_t data[] = { 3, 0xFF };
si5351c_write(data, sizeof(data));
}
/* Turn off OEB pin control for all CLKx */
void si5351c_disable_oeb_pin_control()
{
uint8_t data[] = { 9, 0xFF };
si5351c_write(data, sizeof(data));
}
/* Power down all CLKx */
void si5351c_power_down_all_clocks()
{
uint8_t data[] = { 16
, SI5351C_CLK_POWERDOWN
, SI5351C_CLK_POWERDOWN
, SI5351C_CLK_POWERDOWN
, SI5351C_CLK_POWERDOWN
, SI5351C_CLK_POWERDOWN
, SI5351C_CLK_POWERDOWN
, SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE
, SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE
};
si5351c_write(data, sizeof(data));
}
/*
* Register 183: Crystal Internal Load Capacitance
* Reads as 0xE4 on power-up
* Set to 8pF based on crystal specs and HackRF One testing
*/
void si5351c_set_crystal_configuration()
{
uint8_t data[] = { 183, 0x80 };
si5351c_write(data, sizeof(data));
}
/*
* Register 187: Fanout Enable
* Turn on XO and MultiSynth fanout only.
*/
void si5351c_enable_xo_and_ms_fanout()
{
uint8_t data[] = { 187, 0xD0 };
si5351c_write(data, sizeof(data));
}
/*
* Register 15: PLL Input Source
* CLKIN_DIV=0 (Divide by 1)
* PLLA_SRC=0 (XTAL)
* PLLB_SRC=1 (CLKIN)
*/
void si5351c_configure_pll_sources(void)
{
uint8_t data[] = { 15, 0x08 };
si5351c_write(data, sizeof(data));
}
/* MultiSynth NA (PLLA) and NB (PLLB) */
void si5351c_configure_pll_multisynth(void)
{
//init plla to (0x0e00+512)/128*25mhz xtal = 800mhz -> int mode
uint8_t data[] = { 26, 0x00, 0x01, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00 };
si5351c_write(data, sizeof(data));
/* 10 MHz input on CLKIN for PLLB */
data[0] = 34;
data[4] = 0x26;
si5351c_write(data, sizeof(data));
}
void si5351c_reset_pll(void)
{
/* reset PLLA and PLLB */
uint8_t data[] = { 177, 0xA0 };
si5351c_write(data, sizeof(data));
}
void si5351c_configure_multisynth(const uint_fast8_t ms_number,
const uint32_t p1, const uint32_t p2, const uint32_t p3,
const uint_fast8_t r_div)
{
/*
* TODO: Check for p3 > 0? 0 has no meaning in fractional mode?
* And it makes for more jitter in integer mode.
*/
/*
* r is the r divider value encoded:
* 0 means divide by 1
* 1 means divide by 2
* 2 means divide by 4
* ...
* 7 means divide by 128
*/
const uint_fast8_t register_number = 42 + (ms_number * 8);
uint8_t data[] = {
register_number,
(p3 >> 8) & 0xFF,
(p3 >> 0) & 0xFF,
(r_div << 4) | (0 << 2) | ((p1 >> 16) & 0x3),
(p1 >> 8) & 0xFF,
(p1 >> 0) & 0xFF,
(((p3 >> 16) & 0xF) << 4) | (((p2 >> 16) & 0xF) << 0),
(p2 >> 8) & 0xFF,
(p2 >> 0) & 0xFF };
si5351c_write(data, sizeof(data));
}
#ifdef JELLYBEAN
/*
* Registers 16 through 23: CLKx Control
* CLK0:
* CLK0_PDN=0 (powered up)
* MS0_INT=1 (integer mode)
* MS0_SRC=0 (PLLA as source for MultiSynth 0)
* CLK0_INV=0 (not inverted)
* CLK0_SRC=3 (MS0 as input source)
* CLK0_IDRV=3 (8mA)
* CLK1:
* CLK1_PDN=0 (powered up)
* MS1_INT=1 (integer mode)
* MS1_SRC=0 (PLLA as source for MultiSynth 1)
* CLK1_INV=0 (not inverted)
* CLK1_SRC=2 (MS0 as input source)
* CLK1_IDRV=3 (8mA)
* CLK2:
* CLK2_PDN=0 (powered up)
* MS2_INT=1 (integer mode)
* MS2_SRC=0 (PLLA as source for MultiSynth 2)
* CLK2_INV=0 (not inverted)
* CLK2_SRC=2 (MS0 as input source)
* CLK2_IDRV=3 (8mA)
* CLK3:
* CLK3_PDN=0 (powered up)
* MS3_INT=1 (integer mode)
* MS3_SRC=0 (PLLA as source for MultiSynth 3)
* CLK3_INV=0 (inverted)
* CLK3_SRC=2 (MS0 as input source)
* CLK3_IDRV=3 (8mA)
* CLK4:
* CLK4_PDN=0 (powered up)
* MS4_INT=0 (fractional mode -- to support 12MHz to LPC for USB DFU)
* MS4_SRC=0 (PLLA as source for MultiSynth 4)
* CLK4_INV=0 (not inverted)
* CLK4_SRC=3 (MS4 as input source)
* CLK4_IDRV=3 (8mA)
* CLK5:
* CLK5_PDN=0 (powered up)
* MS5_INT=1 (integer mode)
* MS5_SRC=0 (PLLA as source for MultiSynth 5)
* CLK5_INV=0 (not inverted)
* CLK5_SRC=3 (MS5 as input source)
* CLK5_IDRV=3 (8mA)
*/
void si5351c_configure_clock_control()
{
uint8_t data[] = { 16, 0x4F, 0x4B, 0x4B, 0x4B, 0x0F, 0x4F, 0xC0, 0xC0 };
si5351c_write(data, sizeof(data));
}
#endif
#if (defined JAWBREAKER || defined HACKRF_ONE)
void si5351c_configure_clock_control(const enum pll_sources source)
{
uint8_t pll;
if (source == PLL_SOURCE_CLKIN) {
/* PLLB on CLKIN */
pll = SI5351C_CLK_PLL_SRC_B;
} else {
/* PLLA on XTAL */
pll = SI5351C_CLK_PLL_SRC_A;
}
uint8_t data[] = {16
,SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA)
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA)
,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
};
si5351c_write(data, sizeof(data));
}
#endif
/* Enable CLK outputs 0, 1, 2, 3, 4, 5, 7 only. */
void si5351c_enable_clock_outputs()
{
uint8_t data[] = { 3, 0x40 };
si5351c_write(data, sizeof(data));
}
void si5351c_set_int_mode(const uint_fast8_t ms_number, const uint_fast8_t on){
uint8_t data[] = {16, 0};
if(ms_number < 8){
data[0] = 16 + ms_number;
data[1] = si5351c_read_single(data[0]);
if(on)
data[1] |= SI5351C_CLK_INT_MODE;
else
data[1] &= ~(SI5351C_CLK_INT_MODE);
si5351c_write(data, 2);
}
}
void si5351c_set_clock_source(const enum pll_sources source)
{
si5351c_configure_clock_control(source);
active_clock_source = source;
}
void si5351c_activate_best_clock_source(void)
{
uint8_t device_status = si5351c_read_single(0);
if (device_status & SI5351C_LOS) {
/* CLKIN not detected */
if (active_clock_source == PLL_SOURCE_CLKIN) {
si5351c_set_clock_source(PLL_SOURCE_XTAL);
}
} else {
/* CLKIN detected */
if (active_clock_source == PLL_SOURCE_XTAL) {
si5351c_set_clock_source(PLL_SOURCE_CLKIN);
}
}
}

245
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/*
* Copyright 2013 Michael Ossmann
* Copyright 2013 Benjamin Vernoux
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
/*
* This is a rudimentary driver for the W25Q80BV SPI Flash IC using the
* LPC43xx's SSP0 peripheral (not quad SPIFI). The only goal here is to allow
* programming the flash.
*/
#include <stdint.h>
#include "w25q80bv.h"
#include "hackrf_core.h"
#include <libopencm3/lpc43xx/ssp.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/rgu.h>
/*
* Set up pins for GPIO and SPI control, configure SSP0 peripheral for SPI.
* SSP0_SSEL is controlled by GPIO in order to handle various transfer lengths.
*/
void w25q80bv_setup(void)
{
uint8_t device_id;
const uint8_t serial_clock_rate = 2;
const uint8_t clock_prescale_rate = 2;
/* Reset SPIFI peripheral before to Erase/Write SPIFI memory through SPI */
RESET_CTRL1 = RESET_CTRL1_SPIFI_RST;
/* Init SPIFI GPIO to Normal GPIO */
scu_pinmux(P3_3, (SCU_SSP_IO | SCU_CONF_FUNCTION2)); // P3_3 SPIFI_SCK => SSP0_SCK
scu_pinmux(P3_4, (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)); // P3_4 SPIFI SPIFI_SIO3 IO3 => GPIO1[14]
scu_pinmux(P3_5, (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)); // P3_5 SPIFI SPIFI_SIO2 IO2 => GPIO1[15]
scu_pinmux(P3_6, (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)); // P3_6 SPIFI SPIFI_MISO IO1 => GPIO0[6]
scu_pinmux(P3_7, (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)); // P3_7 SPIFI SPIFI_MOSI IO0 => GPIO5[10]
scu_pinmux(P3_8, (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)); // P3_8 SPIFI SPIFI_CS => GPIO5[11]
/* configure SSP pins */
scu_pinmux(SCU_SSP0_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP0_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP0_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION2));
/* configure GPIO pins */
scu_pinmux(SCU_FLASH_HOLD, SCU_GPIO_FAST);
scu_pinmux(SCU_FLASH_WP, SCU_GPIO_FAST);
scu_pinmux(SCU_SSP0_SSEL, (SCU_GPIO_FAST | SCU_CONF_FUNCTION4));
/* drive SSEL, HOLD, and WP pins high */
gpio_set(PORT_FLASH, (PIN_FLASH_HOLD | PIN_FLASH_WP));
gpio_set(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
/* Set GPIO pins as outputs. */
GPIO1_DIR |= (PIN_FLASH_HOLD | PIN_FLASH_WP);
GPIO5_DIR |= PIN_SSP0_SSEL;
/* initialize SSP0 */
ssp_init(SSP0_NUM,
SSP_DATA_8BITS,
SSP_FRAME_SPI,
SSP_CPOL_0_CPHA_0,
serial_clock_rate,
clock_prescale_rate,
SSP_MODE_NORMAL,
SSP_MASTER,
SSP_SLAVE_OUT_ENABLE);
device_id = 0;
while(device_id != W25Q80BV_DEVICE_ID_RES)
{
device_id = w25q80bv_get_device_id();
}
}
uint8_t w25q80bv_get_status(void)
{
uint8_t value;
gpio_clear(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
ssp_transfer(SSP0_NUM, W25Q80BV_READ_STATUS1);
value = ssp_transfer(SSP0_NUM, 0xFF);
gpio_set(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
return value;
}
/* Release power down / Device ID */
uint8_t w25q80bv_get_device_id(void)
{
uint8_t value;
gpio_clear(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
ssp_transfer(SSP0_NUM, W25Q80BV_DEVICE_ID);
/* Read 3 dummy bytes */
value = ssp_transfer(SSP0_NUM, 0xFF);
value = ssp_transfer(SSP0_NUM, 0xFF);
value = ssp_transfer(SSP0_NUM, 0xFF);
/* Read Device ID shall return 0x13 for W25Q80BV */
value = ssp_transfer(SSP0_NUM, 0xFF);
gpio_set(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
return value;
}
void w25q80bv_get_unique_id(w25q80bv_unique_id_t* unique_id)
{
int i;
uint8_t value;
gpio_clear(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
ssp_transfer(SSP0_NUM, W25Q80BV_UNIQUE_ID);
/* Read 4 dummy bytes */
for(i=0; i<4; i++)
value = ssp_transfer(SSP0_NUM, 0xFF);
/* Read Unique ID 64bits (8*8) */
for(i=0; i<8; i++)
{
value = ssp_transfer(SSP0_NUM, 0xFF);
unique_id->id_8b[i] = value;
}
gpio_set(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
}
void w25q80bv_wait_while_busy(void)
{
while (w25q80bv_get_status() & W25Q80BV_STATUS_BUSY);
}
void w25q80bv_write_enable(void)
{
w25q80bv_wait_while_busy();
gpio_clear(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
ssp_transfer(SSP0_NUM, W25Q80BV_WRITE_ENABLE);
gpio_set(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
}
void w25q80bv_chip_erase(void)
{
uint8_t device_id;
device_id = 0;
while(device_id != W25Q80BV_DEVICE_ID_RES)
{
device_id = w25q80bv_get_device_id();
}
w25q80bv_write_enable();
w25q80bv_wait_while_busy();
gpio_clear(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
ssp_transfer(SSP0_NUM, W25Q80BV_CHIP_ERASE);
gpio_set(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
}
/* write up a 256 byte page or partial page */
void w25q80bv_page_program(const uint32_t addr, const uint16_t len, const uint8_t* data)
{
int i;
/* do nothing if asked to write beyond a page boundary */
if (((addr & 0xFF) + len) > W25Q80BV_PAGE_LEN)
return;
/* do nothing if we would overflow the flash */
if (addr > (W25Q80BV_NUM_BYTES - len))
return;
w25q80bv_write_enable();
w25q80bv_wait_while_busy();
gpio_clear(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
ssp_transfer(SSP0_NUM, W25Q80BV_PAGE_PROGRAM);
ssp_transfer(SSP0_NUM, (addr & 0xFF0000) >> 16);
ssp_transfer(SSP0_NUM, (addr & 0xFF00) >> 8);
ssp_transfer(SSP0_NUM, addr & 0xFF);
for (i = 0; i < len; i++)
ssp_transfer(SSP0_NUM, data[i]);
gpio_set(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
}
/* write an arbitrary number of bytes */
void w25q80bv_program(uint32_t addr, uint32_t len, const uint8_t* data)
{
uint16_t first_block_len;
uint8_t device_id;
device_id = 0;
while(device_id != W25Q80BV_DEVICE_ID_RES)
{
device_id = w25q80bv_get_device_id();
}
/* do nothing if we would overflow the flash */
if ((len > W25Q80BV_NUM_BYTES) || (addr > W25Q80BV_NUM_BYTES)
|| ((addr + len) > W25Q80BV_NUM_BYTES))
return;
/* handle start not at page boundary */
first_block_len = W25Q80BV_PAGE_LEN - (addr % W25Q80BV_PAGE_LEN);
if (len < first_block_len)
first_block_len = len;
if (first_block_len) {
w25q80bv_page_program(addr, first_block_len, data);
addr += first_block_len;
data += first_block_len;
len -= first_block_len;
}
/* one page at a time on boundaries */
while (len >= W25Q80BV_PAGE_LEN) {
w25q80bv_page_program(addr, W25Q80BV_PAGE_LEN, data);
addr += W25Q80BV_PAGE_LEN;
data += W25Q80BV_PAGE_LEN;
len -= W25Q80BV_PAGE_LEN;
}
/* handle end not at page boundary */
if (len) {
w25q80bv_page_program(addr, len, data);
}
}

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The primary CPLD image is: sgpio_if/default.xsvf
This is a binary file built from HDL source in sgpio_if. You do not need
Xilinx tools unless you want to make your own modifications.
To update the CPLD, first update the firmware, libhackrf, and hackrf-tools.
Then:
$ hackrf_cpldjtag -x sgpio_if/default.xsvf

BIN
SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/cpld/sgpio_if/default.xsvf
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Binary file not shown.

10
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#!/bin/sh
echo Program Xilinx CoolRunner-II CPLD on Jellybean, using Bus Blaster v2
jtag <<COMMANDSEND
cable jtagkey vid=0x0403 pid=0x6010 interface=0 driver=ftdi-mpsse
bsdl path bsdl/xc2c
detect
svf default.svf progress stop
COMMANDSEND

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#
# Copyright 2012 Jared Boone
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
NET "CODEC_CLK" LOC="23" |IOSTANDARD=LVCMOS33 | TNM=adc_data;
NET "CODEC_X2_CLK" LOC="27" |IOSTANDARD=LVCMOS33;
NET "CODEC_X2_CLK" TNM_NET = CODEC_X2_CLK;
TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 25 ns;
NET "DA<7>" LOC="35" |IOSTANDARD=LVCMOS33 | TNM=adc_data;
NET "DA<6>" LOC="36" |IOSTANDARD=LVCMOS33 | TNM=adc_data;
NET "DA<5>" LOC="37" |IOSTANDARD=LVCMOS33 | TNM=adc_data;
NET "DA<4>" LOC="39" |IOSTANDARD=LVCMOS33 | TNM=adc_data;
NET "DA<3>" LOC="40" |IOSTANDARD=LVCMOS33 | TNM=adc_data;
NET "DA<2>" LOC="41" |IOSTANDARD=LVCMOS33 | TNM=adc_data;
NET "DA<1>" LOC="42" |IOSTANDARD=LVCMOS33 | TNM=adc_data;
NET "DA<0>" LOC="43" |IOSTANDARD=LVCMOS33 | TNM=adc_data;
NET "DD<9>" LOC="17" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data;
NET "DD<8>" LOC="18" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data;
NET "DD<7>" LOC="19" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data;
NET "DD<6>" LOC="24" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data;
NET "DD<5>" LOC="28" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data;
NET "DD<4>" LOC="29" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data;
NET "DD<3>" LOC="30" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data;
NET "DD<2>" LOC="32" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data;
NET "DD<1>" LOC="33" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data;
NET "DD<0>" LOC="34" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=dac_data;
NET "HOST_DIRECTION" LOC="71" |IOSTANDARD=LVCMOS33 | SLEW=SLOW;
NET "HOST_DISABLE" LOC="76" |IOSTANDARD=LVCMOS33 | SLEW=SLOW;
NET "HOST_CAPTURE" LOC="91" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host;
NET "HOST_DATA<7>" LOC="77" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host;
NET "HOST_DATA<6>" LOC="61" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host;
NET "HOST_DATA<5>" LOC="64" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host;
NET "HOST_DATA<4>" LOC="67" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host;
NET "HOST_DATA<3>" LOC="72" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host;
NET "HOST_DATA<2>" LOC="74" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host;
NET "HOST_DATA<1>" LOC="79" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host;
NET "HOST_DATA<0>" LOC="89" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host;
NET "HOST_DECIM_SEL<2>" LOC="78" |IOSTANDARD=LVCMOS33;
NET "HOST_DECIM_SEL<1>" LOC="81" |IOSTANDARD=LVCMOS33;
NET "HOST_DECIM_SEL<0>" LOC="90" |IOSTANDARD=LVCMOS33;
NET "HOST_Q_INVERT" LOC="70" |IOSTANDARD=LVCMOS33;
TIMEGRP "adc_data" OFFSET = IN 16 ns BEFORE "CODEC_X2_CLK";
TIMEGRP "dac_data" OFFSET = OUT 15 ns AFTER "CODEC_X2_CLK";
TIMEGRP "to_host" OFFSET = OUT 20 ns AFTER "CODEC_X2_CLK";

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CPLD interface to expose LPC43xx microcontroller SGPIO peripheral, either
as all inputs or all outputs.
Requirements
============
To build this VHDL project and produce an SVF file for flashing the CPLD:
* Xilinx WebPACK 13.4 for Windows or Linux.
* BSDL model files for Xilinx CoolRunner-II XC264A, available at xilinx.com,
in the "Device Models" Support Resources section of the CoolRunner-II
Product Support & Documentation page. Only one file from the BSDL package is
required, and the "program" script below expects it to be at the relative
path "bsdl/xc2c/xc2c64.bsd".
To program the SVF file into the CPLD:
* Dangerous Prototypes Bus Blaster v2:
* Configured with JTAGKey buffers.
* Connected to CPLD JTAG signals on Jellybean.
* urJTAG built with libftdi support.
To Program
==========
./program
...which connects to the Bus Blaster interface 0, sets the BSDL directory,
detects devices on the JTAG chain, and writes the sgpio_if_passthrough.svf
file to the CPLD.
Usage:
B1AUX9=0 control SGPIO0 to 15 as Input. B2AUX[1-16] => SGPIO[0-15]
B1AUX9=1 control SGPIO0 to 15 as Output. SGPIO[0-15] => B2AUX[1-16]

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#!/bin/sh
echo Program Xilinx CoolRunner-II CPLD on Jellybean, using Bus Blaster v2
jtag <<COMMANDSEND
cable jtagkey vid=0x0403 pid=0x6010 interface=0 driver=ftdi-mpsse
bsdl path bsdl/xc2c
detect
svf sgpio_if_passthrough.svf progress stop
COMMANDSEND

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#
# Copyright 2012 Jared Boone
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
NET "CODEC_CLK" LOC="23" |FAST |IOSTANDARD=LVCMOS18;
NET "CODEC_X2_CLK" LOC="27" |FAST |IOSTANDARD=LVCMOS18;
#NET "GCLK0" LOC="22" |FAST |IOSTANDARD=LVCMOS18;
NET "CODEC_X2_CLK" TNM_NET = CODEC_X2_CLK;
TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 50 ns;
NET "DA<7>" LOC="35" |FAST |IOSTANDARD=LVCMOS18;
NET "DA<6>" LOC="36" |FAST |IOSTANDARD=LVCMOS18;
NET "DA<5>" LOC="37" |FAST |IOSTANDARD=LVCMOS18;
NET "DA<4>" LOC="39" |FAST |IOSTANDARD=LVCMOS18;
NET "DA<3>" LOC="40" |FAST |IOSTANDARD=LVCMOS18;
NET "DA<2>" LOC="41" |FAST |IOSTANDARD=LVCMOS18;
NET "DA<1>" LOC="42" |FAST |IOSTANDARD=LVCMOS18;
NET "DA<0>" LOC="43" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<9>" LOC="17" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<8>" LOC="18" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<7>" LOC="19" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<6>" LOC="24" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<5>" LOC="28" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<4>" LOC="29" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<3>" LOC="30" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<2>" LOC="32" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<1>" LOC="33" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<0>" LOC="34" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<16>" LOC="60" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<15>" LOC="58" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<14>" LOC="56" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<13>" LOC="55" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<12>" LOC="53" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<11>" LOC="52" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<10>" LOC="50" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<9>" LOC="49" |FAST |IOSTANDARD=LVCMOS18;
NET "SGPIO<15>" LOC="78" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<14>" LOC="81" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<13>" LOC="90" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<12>" LOC="70" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<11>" LOC="71" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<10>" LOC="76" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<9>" LOC="91" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<8>" LOC="68" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<7>" LOC="77" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<6>" LOC="61" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<5>" LOC="64" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<4>" LOC="67" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<3>" LOC="72" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<2>" LOC="74" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<1>" LOC="79" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<0>" LOC="89" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<16>" LOC="92" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<15>" LOC="94" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<14>" LOC="97" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<13>" LOC="99" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<12>" LOC="1" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<11>" LOC="2" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<10>" LOC="3" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<9>" LOC="4" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<8>" LOC="6" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<7>" LOC="7" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<6>" LOC="8" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<5>" LOC="9" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<4>" LOC="10" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<3>" LOC="11" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<2>" LOC="12" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<1>" LOC="13" |FAST |IOSTANDARD=LVCMOS33;

60
SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/cpld/sgpio_if_passthrough/top.vhd
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--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
SGPIO : inout std_logic_vector(15 downto 0);
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic;
B1AUX : in std_logic_vector(16 downto 9);
B2AUX : inout std_logic_vector(16 downto 1)
);
end top;
architecture Behavioral of top is
type transfer_direction is (to_sgpio, from_sgpio);
signal transfer_direction_i : transfer_direction;
begin
transfer_direction_i <= to_sgpio when B1AUX(9) = '0'
else from_sgpio;
DD <= (DD'high => '1', others => '0');
B2AUX <= SGPIO when transfer_direction_i = from_sgpio
else (others => 'Z');
SGPIO <= B2AUX when transfer_direction_i = to_sgpio
else (others => 'Z');
end Behavioral;

178
SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/hackrf-common.cmake
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# Copyright 2009 Uwe Hermann <uwe@hermann-uwe.de>
# Copyright 2010 Piotr Esden-Tempski <piotr@esden.net>
# Copyright 2012 Michael Ossmann <mike@ossmann.com>
# Copyright 2012 Benjamin Vernoux <titanmkd@gmail.com>
# Copyright 2012 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
# derived primarily from Makefiles in libopencm3
enable_language(C CXX ASM)
SET(PATH_HACKRF ../..)
SET(PATH_HACKRF_FIRMWARE ${PATH_HACKRF}/firmware)
SET(PATH_HACKRF_FIRMWARE_COMMON ${PATH_HACKRF_FIRMWARE}/common)
SET(LIBOPENCM3 ${PATH_HACKRF_FIRMWARE}/libopencm3)
execute_process(
COMMAND git log -n 1 --format=%h
WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}
RESULT_VARIABLE GIT_VERSION_FOUND
ERROR_QUIET
OUTPUT_VARIABLE GIT_VERSION
OUTPUT_STRIP_TRAILING_WHITESPACE
)
if (GIT_VERSION_FOUND)
set(VERSION "unknown")
else (GIT_VERSION_FOUND)
set(VERSION ${GIT_VERSION})
endif (GIT_VERSION_FOUND)
if(NOT DEFINED BOARD)
set(BOARD HACKRF_ONE)
endif()
if(NOT DEFINED RUN_FROM)
set(RUN_FROM SPIFI)
endif()
if(BOARD STREQUAL "HACKRF_ONE")
set(MCU_PARTNO LPC4320)
else()
set(MCU_PARTNO LPC4330)
endif()
if(NOT DEFINED SRC_M0)
set(SRC_M0 "${PATH_HACKRF_FIRMWARE_COMMON}/m0_sleep.c")
endif()
SET(HACKRF_OPTS "-D${BOARD} -DLPC43XX -D${MCU_PARTNO} -DTX_ENABLE -D'VERSION_STRING=\"git-${VERSION}\"' -DRUN_FROM=${RUN_FROM}")
SET(LDSCRIPT_M4 "-T${PATH_HACKRF_FIRMWARE_COMMON}/${MCU_PARTNO}_M4_memory.ld")
if( RUN_FROM STREQUAL "RAM")
SET(LDSCRIPT_M4 "${LDSCRIPT_M4} -Tlibopencm3_lpc43xx.ld")
else()
SET(LDSCRIPT_M4 "${LDSCRIPT_M4} -Tlibopencm3_lpc43xx_rom_to_ram.ld")
endif()
SET(LDSCRIPT_M4 "${LDSCRIPT_M4} -T${PATH_HACKRF_FIRMWARE_COMMON}/LPC43xx_M4_M0_image_from_text.ld")
SET(LDSCRIPT_M0 "-T${PATH_HACKRF_FIRMWARE_COMMON}/LPC43xx_M0_memory.ld -Tlibopencm3_lpc43xx_m0.ld")
SET(CFLAGS_COMMON "-Os -g3 -Wall -Wextra ${HACKRF_OPTS} ${COMMON_FLAGS} -fno-common -MD")
SET(LDFLAGS_COMMON "-nostartfiles -Wl,--gc-sections")
if(V STREQUAL "1")
SET(LDFLAGS_COMMON "${LDFLAGS_COMMON} -Wl,--print-gc-sections")
endif()
SET(CPUFLAGS_M0 "-mthumb -mcpu=cortex-m0 -mfloat-abi=soft")
SET(CFLAGS_M0 "-std=gnu99 ${CFLAGS_COMMON} ${CPUFLAGS_M0} -DLPC43XX_M0")
SET(CXXFLAGS_M0 "-std=gnu++0x ${CFLAGS_COMMON} ${CPUFLAGS_M0} -DLPC43XX_M0")
SET(LDFLAGS_M0 "${LDFLAGS_COMMON} ${CPUFLAGS_M0} ${LDSCRIPT_M0} -Xlinker -Map=m0.map --specs=nano.specs")
SET(CPUFLAGS_M4 "-mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16")
SET(CFLAGS_M4 "-std=gnu99 ${CFLAGS_COMMON} ${CPUFLAGS_M4} -DLPC43XX_M4")
SET(CXXFLAGS_M4 "-std=gnu++0x ${CFLAGS_COMMON} ${CPUFLAGS_M4} -DLPC43XX_M4")
SET(LDFLAGS_M4 "${LDFLAGS_COMMON} ${CPUFLAGS_M4} ${LDSCRIPT_M4} -Xlinker -Map=m4.map")
set(BUILD_SHARED_LIBS OFF)
include_directories("${LIBOPENCM3}/include/")
include_directories("${PATH_HACKRF_FIRMWARE_COMMON}")
macro(DeclareTargets)
configure_file(
${PATH_HACKRF_FIRMWARE_COMMON}/m0_bin.s.cmake
m0_bin.s
)
link_directories(
"${PATH_HACKRF_FIRMWARE_COMMON}"
"${LIBOPENCM3}/lib"
"${LIBOPENCM3}/lib/lpc43xx"
"${CMAKE_INSTALL_PREFIX}/lib/armv7e-m/fpu"
)
add_executable(${PROJECT_NAME}_m0.elf ${SRC_M0})
target_link_libraries(
${PROJECT_NAME}_m0.elf
c
nosys
opencm3_lpc43xx_m0
)
set_target_properties(${PROJECT_NAME}_m0.elf PROPERTIES COMPILE_FLAGS "${CFLAGS_M0}")
set_target_properties(${PROJECT_NAME}_m0.elf PROPERTIES LINK_FLAGS "${LDFLAGS_M0}")
add_custom_target(
${PROJECT_NAME}_m0.bin
DEPENDS ${PROJECT_NAME}_m0.elf
COMMAND ${CMAKE_OBJCOPY} -Obinary ${PROJECT_NAME}_m0.elf ${PROJECT_NAME}_m0.bin
)
add_executable(${PROJECT_NAME}.elf
${SRC_M4}
${PATH_HACKRF_FIRMWARE_COMMON}/hackrf_core.c
${PATH_HACKRF_FIRMWARE_COMMON}/sgpio.c
${PATH_HACKRF_FIRMWARE_COMMON}/rf_path.c
${PATH_HACKRF_FIRMWARE_COMMON}/si5351c.c
${PATH_HACKRF_FIRMWARE_COMMON}/max2837.c
${PATH_HACKRF_FIRMWARE_COMMON}/max5864.c
${PATH_HACKRF_FIRMWARE_COMMON}/rffc5071.c
m0_bin.s
)
add_dependencies(${PROJECT_NAME}.elf ${PROJECT_NAME}_m0.bin)
target_link_libraries(
${PROJECT_NAME}.elf
c
nosys
opencm3_lpc43xx
m
)
set_target_properties(${PROJECT_NAME}.elf PROPERTIES COMPILE_FLAGS "${CFLAGS_M4}")
set_target_properties(${PROJECT_NAME}.elf PROPERTIES LINK_FLAGS "${LDFLAGS_M4}")
add_custom_target(
${PROJECT_NAME}.bin
DEPENDS ${PROJECT_NAME}.elf
COMMAND ${CMAKE_OBJCOPY} -Obinary ${PROJECT_NAME}.elf ${PROJECT_NAME}.bin
)
add_custom_target(
${PROJECT_NAME}.dfu ALL
DEPENDS ${PROJECT_NAME}.bin
COMMAND rm -f _tmp.dfu _header.bin
COMMAND cp ${PROJECT_NAME}.bin _tmp.dfu
COMMAND dfu-suffix --vid=0x1fc9 --pid=0x000c --did=0x0 -s 0 -a _tmp.dfu
COMMAND python -c \"import os.path\; import struct\; print\('0000000: da ff ' + ' '.join\(map\(lambda s: '%02x' % ord\(s\), struct.pack\('<H', os.path.getsize\('${PROJECT_NAME}.bin'\) / 512 + 1\)\)\) + ' ff ff ff ff'\)\" | xxd -g1 -r > _header.bin
COMMAND cat _header.bin _tmp.dfu >${PROJECT_NAME}.dfu
COMMAND rm -f _tmp.dfu _header.bin
)
add_custom_target(
${PROJECT_NAME}-program
DEPENDS ${PROJECT_NAME}.dfu
COMMAND dfu-util --device 1fc9:000c --alt 0 --download ${PROJECT_NAME}.dfu
)
endmacro()

85
SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/hackrf_usb/sgpio_isr.c
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/*
* Copyright 2012 Jared Boone
* Copyright 2013 Benjamin Vernoux
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include "sgpio_isr.h"
#include <libopencm3/lpc43xx/sgpio.h>
#include "usb_bulk_buffer.h"
void sgpio_isr_rx() {
SGPIO_CLR_STATUS_1 = (1 << SGPIO_SLICE_A);
uint32_t* const p = (uint32_t*)&usb_bulk_buffer[usb_bulk_buffer_offset];
__asm__(
"ldr r0, [%[SGPIO_REG_SS], #44]\n\t"
"str r0, [%[p], #0]\n\t"
"ldr r0, [%[SGPIO_REG_SS], #20]\n\t"
"str r0, [%[p], #4]\n\t"
"ldr r0, [%[SGPIO_REG_SS], #40]\n\t"
"str r0, [%[p], #8]\n\t"
"ldr r0, [%[SGPIO_REG_SS], #8]\n\t"
"str r0, [%[p], #12]\n\t"
"ldr r0, [%[SGPIO_REG_SS], #36]\n\t"
"str r0, [%[p], #16]\n\t"
"ldr r0, [%[SGPIO_REG_SS], #16]\n\t"
"str r0, [%[p], #20]\n\t"
"ldr r0, [%[SGPIO_REG_SS], #32]\n\t"
"str r0, [%[p], #24]\n\t"
"ldr r0, [%[SGPIO_REG_SS], #0]\n\t"
"str r0, [%[p], #28]\n\t"
:
: [SGPIO_REG_SS] "l" (SGPIO_PORT_BASE + 0x100),
[p] "l" (p)
: "r0"
);
usb_bulk_buffer_offset = (usb_bulk_buffer_offset + 32) & usb_bulk_buffer_mask;
}
void sgpio_isr_tx() {
SGPIO_CLR_STATUS_1 = (1 << SGPIO_SLICE_A);
uint32_t* const p = (uint32_t*)&usb_bulk_buffer[usb_bulk_buffer_offset];
__asm__(
"ldr r0, [%[p], #0]\n\t"
"str r0, [%[SGPIO_REG_SS], #44]\n\t"
"ldr r0, [%[p], #4]\n\t"
"str r0, [%[SGPIO_REG_SS], #20]\n\t"
"ldr r0, [%[p], #8]\n\t"
"str r0, [%[SGPIO_REG_SS], #40]\n\t"
"ldr r0, [%[p], #12]\n\t"
"str r0, [%[SGPIO_REG_SS], #8]\n\t"
"ldr r0, [%[p], #16]\n\t"
"str r0, [%[SGPIO_REG_SS], #36]\n\t"
"ldr r0, [%[p], #20]\n\t"
"str r0, [%[SGPIO_REG_SS], #16]\n\t"
"ldr r0, [%[p], #24]\n\t"
"str r0, [%[SGPIO_REG_SS], #32]\n\t"
"ldr r0, [%[p], #28]\n\t"
"str r0, [%[SGPIO_REG_SS], #0]\n\t"
:
: [SGPIO_REG_SS] "l" (SGPIO_PORT_BASE + 0x100),
[p] "l" (p)
: "r0"
);
usb_bulk_buffer_offset = (usb_bulk_buffer_offset + 32) & usb_bulk_buffer_mask;
}

26
SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/mixertx/README
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@ -1,26 +0,0 @@
This program activates the MAX2837 transceiver to transmit an unmodulated
carrier. It also configures the RFFC5071 to downconvert the carrier to a lower
frequency.
Required Lemondrop -> Jellybean connections:
SCK: Lemondrop P3 pin 2 -> Jellybean P9 2
MOSI: Lemondrop P3 pin 4 -> Jellybean P9 4
MISO: Lemondrop P3 pin 6 -> Jellybean P9 6
SSEL: Lemondrop P3 pin 3 -> Jellybean P9 3
SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3
SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5
SDA: Lemondrop P7 pin 6 -> Jellybean P6 pin 6
VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
1V8: Lemondrop P11 pin 2, 4, or 6 -> Jellybean P16 pin 2, 4, or 6
GND: Lemondrop P5 -> Jellybean P13
Required Lollipop -> Jellybean connections:
GND: Lollipop P8 pin 1, 3, or 5 -> Jellybean P17 pin 1, 3, or 5
VCC: Lollipop P8 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
ENX: Lollipop P4 pin 5 -> Jellybean P5 pin 2
SCLK: Lollipop P4 pin 3 -> Jellybean P5 pin 4
SDATA: Lollipop P4 pin 1 -> Jellybean P5 pin 6
Also RF connectors, and you're on your own to get the RF switches configured
properly.

33
SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/sgpio-rx/CMakeLists.txt
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@ -1,33 +0,0 @@
# Copyright 2012 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(sgpio-rx)
include(../hackrf-common.cmake)
set(SRC_M4
sgpio-rx.c
${PATH_HACKRF_FIRMWARE_COMMON}/tuning.c
)
DeclareTargets()

1
SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/sgpio-rx/README
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@ -1 +0,0 @@
This is a variation of sgpio.c for testing RX.

113
SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/sgpio-rx/sgpio-rx.c
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@ -1,113 +0,0 @@
/*
* Copyright 2012 Michael Ossmann
* Copyright (C) 2012 Jared Boone
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/sgpio.h>
#include <hackrf_core.h>
#include <rf_path.h>
#include <sgpio.h>
#include <tuning.h>
void tx_test() {
sgpio_set_slice_mode(false);
sgpio_configure(TRANSCEIVER_MODE_TX);
// LSB goes out first, samples are 0x<Q1><I1><Q0><I0>
volatile uint32_t buffer[] = {
0xda808080,
0xda80ff80,
0x26808080,
0x26800180,
};
uint32_t i = 0;
sgpio_cpld_stream_enable();
while(true) {
while(SGPIO_STATUS_1 == 0);
SGPIO_REG_SS(SGPIO_SLICE_A) = buffer[(i++) & 3];
SGPIO_CLR_STATUS_1 = 1;
}
}
void rx_test() {
sgpio_set_slice_mode(false);
sgpio_configure(TRANSCEIVER_MODE_RX);
volatile uint32_t buffer[4096];
uint32_t i = 0;
int16_t magsq;
int8_t sigi, sigq;
sgpio_cpld_stream_enable();
gpio_set(PORT_LED1_3, (PIN_LED2)); /* LED2 on */
while(true) {
while(SGPIO_STATUS_1 == 0);
gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */
SGPIO_CLR_STATUS_1 = 1;
buffer[i & 4095] = SGPIO_REG_SS(SGPIO_SLICE_A);
/* find the magnitude squared */
sigi = (buffer[i & 4095] & 0xff) - 0x80;
sigq = ((buffer[i & 4095] >> 8) & 0xff) - 0x80;
magsq = sigi * sigq;
if ((uint16_t)magsq & 0x8000) {
magsq ^= 0xffff;
magsq++;
}
/* illuminate LED3 only when magsq exceeds threshold */
if (magsq > 0x3c00)
gpio_set(PORT_LED1_3, (PIN_LED3)); /* LED3 on */
else
gpio_clear(PORT_LED1_3, (PIN_LED3)); /* LED3 off */
i++;
}
}
int main(void) {
const uint64_t freq = 2700000000U;
pin_setup();
enable_1v8_power();
#ifdef HACKRF_ONE
enable_rf_power();
#endif
cpu_clock_init();
ssp1_init();
rf_path_init();
rf_path_set_direction(RF_PATH_DIRECTION_RX);
set_freq(freq);
rx_test();
gpio_set(PORT_LED1_3, (PIN_LED2)); /* LED2 on */
while (1) {
}
return 0;
}

57
SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/sgpio-rx/table.py
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@ -1,57 +0,0 @@
mossmann@grumio ~/github/hackrf/firmware/simpletx $ python
Python 2.7.3 (default, Jun 22 2012, 11:10:47)
[GCC 4.5.3] on linux2
Type "help", "copyright", "credits" or "license" for more information.
>>> import math
>>> def y(i,max):
... return int(127.5*(math.sin(tau*i/max)+1))
...
>>> tau=math.pi*2
>>> def x(i,max):
... return int(127.5*(math.cos(tau*i/max)+1))
...
>>> def table(max):
... for i in range(0, max, 2):
... print "%02x%02x%02x%02x," % (y(i+1,max), x(i+1,max), y(i,max), x(i,max))
...
>>> table(32)
98fc7fff,
c6e9b0f5,
e9c6d9d9,
fc98f5b0,
fc66ff7f,
e938f54e,
c615d925,
9802b009,
66027f00,
38154e09,
15382525,
0266094e,
0298007f,
15c609b0,
38e925d9,
66fc4ef5,
>>> def table(max):
... for i in range(0, max, 2):
... print "0x%02x%02x%02x%02x," % (y(i+1,max), x(i+1,max), y(i,max), x(i,max))
...
>>> table(32)
0x98fc7fff,
0xc6e9b0f5,
0xe9c6d9d9,
0xfc98f5b0,
0xfc66ff7f,
0xe938f54e,
0xc615d925,
0x9802b009,
0x66027f00,
0x38154e09,
0x15382525,
0x0266094e,
0x0298007f,
0x15c609b0,
0x38e925d9,
0x66fc4ef5,

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# Copyright 2012 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(sgpio_test)
include(../hackrf-common.cmake)
set(SRC_M4
sgpio_test.c
)
DeclareTargets()

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A program to demonstrate TX control of the MAX5864 DAC, via the
SGPIO CPLD interface.

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/*
* Copyright 2012 Michael Ossmann
* Copyright (C) 2012 Jared Boone
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/sgpio.h>
#include <libopencm3/lpc43xx/cgu.h>
#include <libopencm3/cm3/scs.h>
#include <hackrf_core.h>
#include <max5864.h>
#include <sgpio.h>
volatile uint32_t buffer[4096];
void tx_test() {
sgpio_set_slice_mode(false);
sgpio_configure(TRANSCEIVER_MODE_TX);
// LSB goes out first, samples are 0x<Q1><I1><Q0><I0>
buffer[0] = 0xda808080;
buffer[1] = 0xda80ff80;
buffer[2] = 0x26808080;
buffer[3] = 0x26800180;
uint32_t i = 0;
sgpio_cpld_stream_enable();
while(true) {
while(SGPIO_STATUS_1 == 0);
SGPIO_REG_SS(SGPIO_SLICE_A) = buffer[(i++) & 3];
SGPIO_CLR_STATUS_1 = 1;
}
}
void rx_test() {
sgpio_set_slice_mode(false);
sgpio_configure(TRANSCEIVER_MODE_RX);
uint32_t i = 0;
sgpio_cpld_stream_enable();
while(true) {
while(SGPIO_STATUS_1 == 0);
SGPIO_CLR_STATUS_1 = 1;
buffer[i++ & 4095] = SGPIO_REG_SS(SGPIO_SLICE_A);
}
}
int main(void) {
pin_setup();
enable_1v8_power();
cpu_clock_init();
ssp1_init();
gpio_set(PORT_LED1_3, PIN_LED1);
ssp1_set_mode_max5864();
max5864_xcvr();
while (1) {
}
return 0;
}

33
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# Copyright 2012 Jared Boone <jared@sharebrained.com>
# Copyright 2012 Benjamin Vernoux <titanmkd@gmail.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(sgpio_passthrough)
include(../hackrf-common.cmake)
set(SRC_M4
sgpio_passthrough.c
)
DeclareTargets()

5
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A program to test SGPIO with CPLD passthrough Input & Output via the SGPIO CPLD interface (P8 BANK2_AUX).
For this test connect P10 BANK1_AUX AUX9 pin to +1V8 (in order to have P8 BANK2_AUX AUX1 to 16 as Output).
This test requires:
* JellyBean+Lemondrop(to set clock at 204MHz).
* CPLD X2C64A hardware\jellybean\sgpio_if_passthrough\sgpio_if_passthrough.svf to be loaded first.

BIN
SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/sgpio_passthrough/Test_SGPIO0_to15.ods
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Binary file not shown.

BIN
SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/sgpio_passthrough/Test_SGPIO0_to15.pdf
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Binary file not shown.

68
SoftwareDefined/HackRF/hackrf-2015.07.2/firmware/sgpio_passthrough/Test_SGPIO_GPIO_mode_test_sgpio_interface.txt
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Test SGPIO GPIO mode, with LPC4330@204MHz (JellyBean+Lemondrop) and code executed in RAM.
Test1:
------
while(1)
{
for (uint_fast8_t i = 0; i < 8; i++)
{
SGPIO_GPIO_OUTREG ^= (1L << i);
}
}
Oscilloscope result (on SGPIO0): Frequency 750KHz => 272 cycles
Test2:
------
while(1)
{
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
SGPIO_GPIO_OUTREG ^= 0x5555;
}
Oscilloscope result (on SGPIO0): 3.923 MHz => 52 cycles
Test3:
------
while(1)
{
SGPIO_GPIO_OUTREG ^= 0x5555;
}
Oscilloscope result (on SGPIO0): Frequency 7.28MHz => 28 cycles
Test4:
------
while(1)
{
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
SGPIO_GPIO_OUTREG = 0x5555;
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
SGPIO_GPIO_OUTREG = 0xAAAA;
}
Oscilloscope result (on SGPIO0): Frequency 17MHz => 12 cycles
Test5:
------
while(1)
{
SGPIO_GPIO_OUTREG = 0x5555;
SGPIO_GPIO_OUTREG = 0xAAAA;
}
Oscilloscope result (on SGPIO0): Frequency 25.5MHz => 8 cycles

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/*
* Copyright 2012 Michael Ossmann
* Copyright (C) 2012 Jared Boone
* Copyright (C) 2012 Benjamin Vernoux
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/sgpio.h>
#include <libopencm3/lpc43xx/cgu.h>
#include <libopencm3/cm3/scs.h>
#include <hackrf_core.h>
void configure_sgpio_pin_functions() {
scu_pinmux(SCU_PINMUX_SGPIO0, SCU_GPIO_FAST | SCU_CONF_FUNCTION3);
scu_pinmux(SCU_PINMUX_SGPIO1, SCU_GPIO_FAST | SCU_CONF_FUNCTION3);
scu_pinmux(SCU_PINMUX_SGPIO2, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
scu_pinmux(SCU_PINMUX_SGPIO3, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
scu_pinmux(SCU_PINMUX_SGPIO4, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
scu_pinmux(SCU_PINMUX_SGPIO5, SCU_GPIO_FAST | SCU_CONF_FUNCTION2);
scu_pinmux(SCU_PINMUX_SGPIO6, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_SGPIO7, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
scu_pinmux(SCU_PINMUX_SGPIO8, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
scu_pinmux(SCU_PINMUX_SGPIO9, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
scu_pinmux(SCU_PINMUX_SGPIO10, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
scu_pinmux(SCU_PINMUX_SGPIO11, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
scu_pinmux(SCU_PINMUX_SGPIO12, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
scu_pinmux(SCU_PINMUX_SGPIO13, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
scu_pinmux(SCU_PINMUX_SGPIO14, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
scu_pinmux(SCU_PINMUX_SGPIO15, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
}
void test_sgpio_sliceA_D(void)
{
SGPIO_GPIO_OENREG = 0; // All inputs for the moment.
// Disable all counters during configuration
SGPIO_CTRL_ENABLE = 0;
// Configure pin functions.
configure_sgpio_pin_functions();
/****************************************************/
/* Enable SGPIO pin outputs. */
/****************************************************/
SGPIO_GPIO_OENREG =
0xFFFF; // data: output for SGPIO0 to SGPIO15
/*******************************************************************************/
/* SGPIO pin 0 outputs slice A bit 0. (see Table 212. Output pin multiplexing) */
/*******************************************************************************/
SGPIO_OUT_MUX_CFG(0) =
(0L << 4) | // P_OE_CFG = X
(0L << 0); // P_OUT_CFG = 0, dout_doutm1 (1-bit mode)
// SGPIO pin 12 outputs slice D bit 0. (see Table 212. Output pin multiplexing)
SGPIO_OUT_MUX_CFG(12) =
(0L << 4) | // P_OE_CFG = X
(0L << 0); // P_OUT_CFG = 0, dout_doutm1 (1-bit mode)
/****************************************************/
/* Slice A */
/****************************************************/
SGPIO_MUX_CFG(SGPIO_SLICE_A) =
(0L << 12) | // CONCAT_ORDER = 0 (self-loop)
(1L << 11) | // CONCAT_ENABLE = 1 (concatenate data)
(0L << 9) | // QUALIFIER_SLICE_MODE = X
(0L << 7) | // QUALIFIER_PIN_MODE = X
(0L << 5) | // QUALIFIER_MODE = 0 (enable)
(0L << 3) | // CLK_SOURCE_SLICE_MODE = 0, slice D
(0L << 1) | // CLK_SOURCE_PIN_MODE = X
(0L << 0); // EXT_CLK_ENABLE = 0, internal clock signal (slice)
SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_A) =
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
(0L << 6) | // PARALLEL_MODE = 0 (shift 1 bit per clock)
(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
(0L << 3) | // INV_OUT_CLK = 0 (normal clock)
(0L << 2) | // CLKGEN_MODE = 0 (use clock from COUNTER)
(0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge)
(0L << 0); // MATCH_MODE = 0 (do not match data)
SGPIO_PRESET(SGPIO_SLICE_A) = 1;
SGPIO_COUNT(SGPIO_SLICE_A) = 0;
SGPIO_POS(SGPIO_SLICE_A) = (0x1FL << 8) | (0x1FL << 0);
SGPIO_REG(SGPIO_SLICE_A) = 0xAAAAAAAA; // Primary output data register
SGPIO_REG_SS(SGPIO_SLICE_A) = 0xAAAAAAAA; // Shadow output data register
/****************************************************/
/* Slice D (clock for Slice A) */
/****************************************************/
SGPIO_MUX_CFG(SGPIO_SLICE_D) =
(0L << 12) | // CONCAT_ORDER = 0 (self-loop)
(1L << 11) | // CONCAT_ENABLE = 1 (concatenate data)
(0L << 9) | // QUALIFIER_SLICE_MODE = X
(0L << 7) | // QUALIFIER_PIN_MODE = X
(0L << 5) | // QUALIFIER_MODE = 0 (enable)
(0L << 3) | // CLK_SOURCE_SLICE_MODE = 0, slice D
(0L << 1) | // CLK_SOURCE_PIN_MODE = X
(0L << 0); // EXT_CLK_ENABLE = 0, internal clock signal (slice)
SGPIO_SLICE_MUX_CFG(SGPIO_SLICE_D) =
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
(0L << 6) | // PARALLEL_MODE = 0 (shift 1 bit per clock)
(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
(0L << 3) | // INV_OUT_CLK = 0 (normal clock)
(0L << 2) | // CLKGEN_MODE = 0 (use clock from COUNTER)
(0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge)
(0L << 0); // MATCH_MODE = 0 (do not match data)
SGPIO_PRESET(SGPIO_SLICE_D) = 0;
SGPIO_COUNT(SGPIO_SLICE_D) = 0;
SGPIO_POS(SGPIO_SLICE_D) = (0x1FL << 8) | (0x1FL << 0);
SGPIO_REG(SGPIO_SLICE_D) = 0xAAAAAAAA; // Primary output data register
SGPIO_REG_SS(SGPIO_SLICE_D) = 0xAAAAAAAA; // Shadow output data register
/****************************************************/
/* Start SGPIO operation by enabling slice clocks. */
/****************************************************/
SGPIO_CTRL_ENABLE =
(1L << SGPIO_SLICE_D) | // Slice D
(1L << SGPIO_SLICE_A); // Slice A
// Start SGPIO operation by enabling slice clocks.
/*
Expected:
SGPIO12 = MCU Freq/2
SGPIO0 = SGPIO12/2 MHz= 51MHz (SliceD/2)
*/
}
/*******************************************************************************/
/* Output 1bit table (see Table 212. Output pin multiplexing) */
/* SGPIO pin 00 outputs slice A bit 0. */
/* SGPIO pin 01 outputs slice I bit 0. */
/* SGPIO pin 02 outputs slice E bit 0. */
/* SGPIO pin 03 outputs slice J bit 0. */
/* SGPIO pin 04 outputs slice C bit 0. */
/* SGPIO pin 05 outputs slice K bit 0. */
/* SGPIO pin 06 outputs slice F bit 0. */
/* SGPIO pin 07 outputs slice L bit 0. */
/* SGPIO pin 08 outputs slice B bit 0. */
/* SGPIO pin 09 outputs slice M bit 0. */
/* SGPIO pin 10 outputs slice G bit 0. */
/* SGPIO pin 11 outputs slice N bit 0. */
/* SGPIO pin 12 outputs slice D bit 0. */
/* SGPIO pin 13 outputs slice O bit 0. */
/* SGPIO pin 14 outputs slice H bit 0. */
/* SGPIO pin 15 outputs slice P bit 0. */
/*******************************************************************************/
const uint8_t slice_preset_tab[16] =
{
0, /* Idx00 = Slice A => SGPIO0 Freq Div by 1=0 */
8, /* Idx01 = Slice B => SGPIO8 Freq Div by 9=8 */
4, /* Idx02 = Slice C => SGPIO4 Freq Div by 5=4 */
12, /* Idx03 = Slice D => SGPIO12 Freq Div by 13=12 */
2, /* Idx04 = Slice E => SGPIO2 Freq Div by 3=2 */
6, /* Idx05 = Slice F => SGPIO6 Freq Div by 7=6 */
10, /* Idx06 = Slice G => SGPIO10 Freq Div by 11=10 */
14, /* Idx07 = Slice H => SGPIO14 Freq Div by 15=14 */
1, /* Idx08 = Slice I => SGPIO1 Freq Div by 2=1 */
3, /* Idx09 = Slice J => SGPIO3 Freq Div by 4=3 */
5, /* Idx10 = Slice K => SGPIO5 Freq Div by 6=5 */
7, /* Idx11 = Slice L => SGPIO7 Freq Div by 8=7 */
9, /* Idx12 = Slice M => SGPIO9 Freq Div by 10=9 */
11, /* Idx13 = Slice N => SGPIO11 Freq Div by 12=11 */
13, /* Idx14 = Slice O => SGPIO13 Freq Div by 14=13 */
15 /* Idx15 = Slice P => SGPIO15 Freq Div by 16=15 */
};
void test_sgpio_all_slices(void)
{
SGPIO_GPIO_OENREG = 0; // All inputs for the moment.
// Disable all counters during configuration
SGPIO_CTRL_ENABLE = 0;
// Configure pin functions.
configure_sgpio_pin_functions();
/****************************************************/
/* Enable SGPIO pin outputs. */
/****************************************************/
SGPIO_GPIO_OENREG =
0xFFFF; // data: output for SGPIO0 to SGPIO15
for(uint_fast8_t i=0; i<16; i++)
{
SGPIO_OUT_MUX_CFG(i) =
(0L << 4) | // P_OE_CFG = X
(0L << 0); // P_OUT_CFG = 0, dout_doutm1 (1-bit mode)
}
/****************************************************/
/* Slice A to P */
/****************************************************/
for(uint_fast8_t i=0; i<16; i++)
{
SGPIO_MUX_CFG(i) =
(0L << 12) | // CONCAT_ORDER = 0 (self-loop)
(1L << 11) | // CONCAT_ENABLE = 1 (concatenate data)
(0L << 9) | // QUALIFIER_SLICE_MODE = X
(0L << 7) | // QUALIFIER_PIN_MODE = X
(0L << 5) | // QUALIFIER_MODE = 0 (enable)
(0L << 3) | // CLK_SOURCE_SLICE_MODE = 0, slice D
(0L << 1) | // CLK_SOURCE_PIN_MODE = X
(0L << 0); // EXT_CLK_ENABLE = 0, internal clock signal (slice)
SGPIO_SLICE_MUX_CFG(i) =
(0L << 8) | // INV_QUALIFIER = 0 (use normal qualifier)
(0L << 6) | // PARALLEL_MODE = 0 (shift 1 bit per clock)
(0L << 4) | // DATA_CAPTURE_MODE = 0 (detect rising edge)
(0L << 3) | // INV_OUT_CLK = 0 (normal clock)
(0L << 2) | // CLKGEN_MODE = 0 (use clock from COUNTER)
(0L << 1) | // CLK_CAPTURE_MODE = 0 (use rising clock edge)
(0L << 0); // MATCH_MODE = 0 (do not match data)
SGPIO_PRESET(i) = slice_preset_tab[i];
SGPIO_COUNT(i) = 0;
SGPIO_POS(i) = (0x1FL << 8) | (0x1FL << 0);
SGPIO_REG(i) = 0xAAAAAAAA; // Primary output data register
SGPIO_REG_SS(i) = 0xAAAAAAAA; // Shadow output data register
}
/****************************************************/
/* Start SGPIO operation by enabling slice clocks. */
/****************************************************/
SGPIO_CTRL_ENABLE = 0xFFFF; /* Start all slices A to P */
/*
(1L << SGPIO_SLICE_D) | // Slice D
(1L << SGPIO_SLICE_A); // Slice A
// Start SGPIO operation by enabling slice clocks.
*/
/*
Expected:
MCU Freq MHz = 204
SGPIO Theorical Freq MHz
SGPIO00 = 102,00000
SGPIO01 = 51,00000
SGPIO02 = 34,00000
SGPIO03 = 25,50000
SGPIO04 = 20,40000
SGPIO05 = 17,00000
SGPIO06 = 14,57143
SGPIO07 = 12,75000
SGPIO08 = 11,33333
SGPIO09 = 10,20000
SGPIO10 = 9,27273
SGPIO11 = 8,50000
SGPIO12 = 7,84615
SGPIO13 = 7,28571
SGPIO14 = 6,80000
SGPIO15 = 6,37500
TitanMKD: I have problems with my boards and this test see document Test_SGPIO0_to15.ods / Test_SGPIO0_to15.pdf
*/
}
void test_sgpio_interface(void)
{
SGPIO_GPIO_OENREG = 0; // All inputs for the moment.
// Disable all counters during configuration
SGPIO_CTRL_ENABLE = 0;
configure_sgpio_pin_functions();
// Make all SGPIO controlled by SGPIO's "GPIO" registers
for (uint_fast8_t i = 0; i < 16; i++) {
SGPIO_OUT_MUX_CFG(i) = (0L << 4) | (4L << 0);
}
// Enable SGPIO pin outputs (SGPIO0 to 15).
SGPIO_GPIO_OENREG = 0xFFFF;
/* Set values for SGPIO0 to 15 */
while (1)
{
// 750KHz => 272 cycles
/*
for (uint_fast8_t i = 0; i < 8; i++) {
SGPIO_GPIO_OUTREG ^= (1L << i);
}
*/
// 3.923 MHz => 52 cycles
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
SGPIO_GPIO_OUTREG ^= 0x5555;
// 7.28 MHz => 28 cycles
/*
SGPIO_GPIO_OUTREG ^= 0x5555;
*/
// 17 MHz => 12 cycles
/*
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
SGPIO_GPIO_OUTREG = 0x5555;
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
__asm__(" nop");
SGPIO_GPIO_OUTREG = 0xAAAA;
*/
// 25.50 MHz => 8 cycles
/*
SGPIO_GPIO_OUTREG = 0x5555;
SGPIO_GPIO_OUTREG = 0xAAAA;
*/
}
/* TitanMKD: I have problems with my board with this test (see test_sgpio_all_slices()) */
}
int main(void)
{
pin_setup();
enable_1v8_power();
cpu_clock_init();
ssp1_init();
gpio_set(PORT_LED1_3, PIN_LED1);
//test_sgpio_sliceA_D();
test_sgpio_interface();
//test_sgpio_all_slices();
while(1);
return 0;
}

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@ -1,32 +0,0 @@
# Copyright 2014 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(simpletx)
include(../hackrf-common.cmake)
set(SRC_M4
simpletx.c
)
DeclareTargets()

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This program activates the MAX2837 transceiver to transmit an unmodulated
carrier.
Required Lemondrop -> Jellybean connections:
SCK: Lemondrop P3 pin 2 -> Jellybean P9 2
CS_XCVR: Lemondrop P3 pin 3 -> Jellybean P9 3
MOSI: Lemondrop P3 pin 4 -> Jellybean P9 4
CS_AD: Lemondrop P3 pin 5 -> Jellybean P9 5
MISO: Lemondrop P3 pin 6 -> Jellybean P9 6
ENABLE: Lemondrop P6 pin 12 -> Jellybean P7 pin 12
RXENABLE: Lemondrop P6 pin 13 -> Jellybean P7 pin 13
TXENABLE: Lemondrop P6 pin 15 -> Jellybean P7 pin 15
SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3
SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5
SDA: Lemondrop P7 pin 6 -> Jellybean P6 pin 6
VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
GND: Lemondrop P5 -> Jellybean P13
For now we are running everything at 3.3 V, but in the future we may also
require:
1V8: Lemondrop P11 pin 2, 4, or 6 -> Jellybean P16 pin 2, 4, or 6

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# Copyright 2012 Michael Ossmann <mike@ossmann.com>
# Copyright 2012 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(spiflash)
include(../hackrf-common.cmake)
set(SRC_M4
spiflash.c
"${PATH_HACKRF_FIRMWARE_COMMON}/w25q80bv.c"
)
DeclareTargets()

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This is a test program for SPI flash programming.

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/*
* Copyright 2010 - 2012 Michael Ossmann
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h>
#include "hackrf_core.h"
#include "w25q80bv.h"
int main(void)
{
int i;
uint8_t buf[515];
pin_setup();
enable_1v8_power();
cpu_clock_init();
/* program test data to SPI flash */
for (i = 0; i < 515; i++)
buf[i] = (i * 3) & 0xFF;
w25q80bv_setup();
w25q80bv_chip_erase();
w25q80bv_program(790, 515, &buf[0]);
/* blink LED1 and LED3 */
while (1)
{
gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED3)); /* LEDs on */
for (i = 0; i < 8000000; i++) /* Wait a bit. */
__asm__("nop");
gpio_clear(PORT_LED1_3, (PIN_LED1|PIN_LED3)); /* LED off */
for (i = 0; i < 8000000; i++) /* Wait a bit. */
__asm__("nop");
}
return 0;
}

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# Copyright 2014 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(startup)
include(../hackrf-common.cmake)
set(SRC_M4
startup.c
)
DeclareTargets()

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This program is an example of the startup sequence for HackRF (Jellybean with
Lemondrop attached). LED1, LED2, and LED3 are illuminated upon success.
Required Lemondrop -> Jellybean connections:
SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3
SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5
SDA: Lemondrop P7 pin 6 -> Jellybean P6 pin 6
VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
1V8: Lemondrop P11 pin 2, 4, or 6 -> Jellybean P16 pin 2, 4, or 6
GND: Lemondrop P5 -> Jellybean P13

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/*
* Copyright 2010 - 2012 Michael Ossmann
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/i2c.h>
#include "hackrf_core.h"
int main(void)
{
uint32_t i;
pin_setup();
enable_1v8_power();
cpu_clock_init();
gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */
while (1)
{
gpio_set(PORT_LED1_3, (PIN_LED1)); /* LEDs on */
for (i = 0; i < 2000000; i++) /* Wait a bit. */
__asm__("nop");
gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2)); /* LEDs on */
for (i = 0; i < 2000000; i++) /* Wait a bit. */
__asm__("nop");
gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LED off */
for (i = 0; i < 2000000; i++) /* Wait a bit. */
__asm__("nop");
gpio_clear(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LED off */
for (i = 0; i < 2000000; i++) /* Wait a bit. */
__asm__("nop");
}
return 0;
}

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# Copyright 2014 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(startup_systick)
include(../hackrf-common.cmake)
set(SRC_M4
startup_systick.c
)
DeclareTargets()

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This program is an example of the startup sequence for HackRF (Jellybean with
Lemondrop attached).
LED1, LED2, and LED3 are blinking at exactly a frequency of 1Hz upon success.
Required Lemondrop -> Jellybean connections:
SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3
SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5
SDA: Lemondrop P7 pin 6 -> Jellybean P6 pin 6
VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
1V8: Lemondrop P11 pin 2, 4, or 6 -> Jellybean P16 pin 2, 4, or 6
GND: Lemondrop P5 -> Jellybean P13

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/*
* Copyright 2012 Benjamin Vernoux
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/i2c.h>
#include <libopencm3/lpc43xx/m4/nvic.h>
#include <libopencm3/cm3/systick.h>
#include <libopencm3/cm3/scs.h>
#include "hackrf_core.h"
/* Global counter incremented by SysTick Interrupt each millisecond */
volatile uint32_t g_ulSysTickCount;
uint32_t g_NbCyclePerSecond;
void systick_setup(void)
{
uint32_t systick_reload_val;
g_ulSysTickCount = 0;
/* Disable IRQ globally */
__asm__("cpsid i");
/* Set processor Clock as Source Clock */
systick_set_clocksource(STK_CTRL_CLKSOURCE);
/* Get SysTick calibration value to obtain by default 1 tick = 10ms */
systick_reload_val = systick_get_calib();
/*
* Calibration seems wrong on LPC43xx(TBC) for default Freq it assume System Clock is 12MHz but it is 12*17=204MHz
* Fix the Calibration value bu multiplication by 17
*/
systick_reload_val = (systick_reload_val*17);
/* To obtain 1ms per tick just divide by 10 the 10ms base tick and set the reload */
systick_reload_val = systick_reload_val/10;
systick_set_reload(systick_reload_val);
systick_interrupt_enable();
/* Start counting. */
systick_counter_enable();
/* Set SysTick Priority to maximum */
nvic_set_priority(NVIC_SYSTICK_IRQ, 0xFF);
/* Enable IRQ globally */
__asm__("cpsie i");
}
void scs_dwt_cycle_counter_enabled(void)
{
SCS_DEMCR |= SCS_DEMCR_TRCENA;
SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA;
}
uint32_t sys_tick_get_time_ms(void)
{
return g_ulSysTickCount;
}
uint32_t sys_tick_delta_time_ms(uint32_t start, uint32_t end)
{
#define MAX_T_U32 ((2^32)-1)
uint32_t diff;
if(end > start)
{
diff=end-start;
}else
{
diff=MAX_T_U32-(start-end)+1;
}
return diff;
}
void sys_tick_wait_time_ms(uint32_t wait_ms)
{
uint32_t start, end;
uint32_t tickms;
start = sys_tick_get_time_ms();
do
{
end = sys_tick_get_time_ms();
tickms = sys_tick_delta_time_ms(start, end);
}while(tickms < wait_ms);
}
/* Called each 1ms/1000Hz by interrupt
1) Count the number of cycle per second.
2) Increment g_ulSysTickCount counter.
*/
void sys_tick_handler(void)
{
if(g_ulSysTickCount==0)
{
/* Clear Cycle Counter*/
SCS_DWT_CYCCNT = 0;
}else if(g_ulSysTickCount==1000)
{
/* Capture number of cycle elapsed during 1 second */
g_NbCyclePerSecond = SCS_DWT_CYCCNT;
}
g_ulSysTickCount++;
}
int main(void)
{
pin_setup();
enable_1v8_power();
cpu_clock_init();
scs_dwt_cycle_counter_enabled();
systick_setup();
gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */
while (1)
{
gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */
gpio_set(PORT_LED1_3, (PIN_LED2)); /* LED2 on */
gpio_set(PORT_LED1_3, (PIN_LED3)); /* LED3 on */
sys_tick_wait_time_ms(500);
gpio_clear(PORT_LED1_3, (PIN_LED3)); /* LED3 off */
gpio_clear(PORT_LED1_3, (PIN_LED2)); /* LED2 off */
gpio_clear(PORT_LED1_3, (PIN_LED1)); /* LED1 off */
sys_tick_wait_time_ms(500);
}
return 0;
}

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# Copyright 2014 Jared Boone <jared@sharebrained.com>
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
cmake_minimum_required(VERSION 2.8.9)
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
project(startup_systick_perfo_SPIFI)
include(../hackrf-common.cmake)
set(SRC_M4
startup_systick.c
perf_mips.c
)
DeclareTargets()

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This program is an example of the startup sequence for HackRF (Jellybean with
Lemondrop attached).
Test number of instruction per second (MIPS) slow blink ON 1s, OFF 1s
Then after 16s (the 16tests) it blink LED1/2/3 ON/OFF each 250ms.
This example compute the number of instructions per second executed called also MIPS (Millions of Instructions Per Second)
This example code run from SRAM so maximum performance expected is 204MIPS.
See result details in result_exec_from_SRAM.txt
This example code run from SPIFI (SPI Quad mode) and the tests check different loop size to compute the cache size used with SPIFI and estimated to less than 256Bytes (about 128 instructions in best case and in Thumb2).
See result_exec_from_SPIFI.txt for more details.
Required Lemondrop -> Jellybean connections:
SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3
SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5
SDA: Lemondrop P7 pin 6 -> Jellybean P6 pin 6
VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6
1V8: Lemondrop P11 pin 2, 4, or 6 -> Jellybean P16 pin 2, 4, or 6
GND: Lemondrop P5 -> Jellybean P13

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Frequency MCU Core M4 = 204MHz
"nb_inst_per_sec" 0x10000008
nb_inst_per_sec[0] 195609816 test_nb_instruction_per_sec_100_nop_asm();
nb_inst_per_sec[1] 195577462 test_nb_instruction_per_sec_105_nop_asm();
nb_inst_per_sec[2] 195525410 test_nb_instruction_per_sec_110_nop_asm();
nb_inst_per_sec[3] 35423508 test_nb_instruction_per_sec_115_nop_asm();
nb_inst_per_sec[4] 5058688 test_nb_instruction_per_sec_120_nop_asm();
nb_inst_per_sec[5] 5094868 test_nb_instruction_per_sec_150_nop_asm();
nb_inst_per_sec[6] 5162144 test_nb_instruction_per_sec_200_nop_asm();
nb_inst_per_sec[7] 5505696 test_nb_instruction_per_sec_1000_nop_asm();
nb_inst_per_sec[8] 195600420 test_nb_instruction_per_sec_100_nop_asm();
nb_inst_per_sec[9] 195578027 test_nb_instruction_per_sec_105_nop_asm();
nb_inst_per_sec[10] 195525882 test_nb_instruction_per_sec_110_nop_asm();
nb_inst_per_sec[11] 35422647 test_nb_instruction_per_sec_115_nop_asm();
nb_inst_per_sec[12] 5058688 test_nb_instruction_per_sec_120_nop_asm();
nb_inst_per_sec[13] 5094868 test_nb_instruction_per_sec_150_nop_asm();
nb_inst_per_sec[14] 5162144 test_nb_instruction_per_sec_200_nop_asm();
nb_inst_per_sec[15] 5505696 test_nb_instruction_per_sec_1000_nop_asm();
Real speed expected from SPIFI without cache (with lot of nop)
Oscilloscope Freq SPIFI SCK = 22.50MHz to 22.83MHz (in reality 22.67MHz => 204/9 => SPIFI_CLK connected to IDIVB & IDIVB default=9)
So worst case 22.50Mbits*4 = 90Mbits/s => 11.25MBytes/s with an overhead of about 50% due to SPIFI protocol addr ... => 5.625MB
1 nop = 2 bytes (THUMB 0x00 0xBF) => Max 5.625 Millions instruction per second
110 NOP is in fact 110 + 9 (including loop overhead)
119*2 = 238 bytes
115NOP + 9 => does not enter in cache !! (248bytes)
Internal Cache size is about 256Bytes maybe shared Code/Data.
SPIFI obtained min=5.05 MIPS, max=195.6 MIPS

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Frequency MCU Core M4 = 204MHz
"nb_inst_per_sec" 0x10080008
nb_inst_per_sec[0] 202091544 test_nb_instruction_per_sec_100_nop_asm();
nb_inst_per_sec[1] 202172820 test_nb_instruction_per_sec_105_nop_asm();
nb_inst_per_sec[2] 202247988 test_nb_instruction_per_sec_110_nop_asm();
nb_inst_per_sec[3] 202317165 test_nb_instruction_per_sec_115_nop_asm();
nb_inst_per_sec[4] 202381696 test_nb_instruction_per_sec_120_nop_asm();
nb_inst_per_sec[5] 202680030 test_nb_instruction_per_sec_150_nop_asm();
nb_inst_per_sec[6] 202986160 test_nb_instruction_per_sec_200_nop_asm();
nb_inst_per_sec[7] 203760144 test_nb_instruction_per_sec_1000_nop_asm();
nb_inst_per_sec[8] 202091220 test_nb_instruction_per_sec_100_nop_asm();
nb_inst_per_sec[9] 202172820 test_nb_instruction_per_sec_105_nop_asm();
nb_inst_per_sec[10] 202247988 test_nb_instruction_per_sec_110_nop_asm();
nb_inst_per_sec[11] 202317165 test_nb_instruction_per_sec_115_nop_asm();
nb_inst_per_sec[12] 202381696 test_nb_instruction_per_sec_120_nop_asm();
nb_inst_per_sec[13] 202680030 test_nb_instruction_per_sec_150_nop_asm();
nb_inst_per_sec[14] 202986160 test_nb_instruction_per_sec_200_nop_asm();
nb_inst_per_sec[15] 203760144 test_nb_instruction_per_sec_1000_nop_asm();
SRAM execution, expected 204 MIPS best case obtained min=202 MIPS, max=203.7 MIPS

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/*
* Copyright 2010 - 2012 Michael Ossmann
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/i2c.h>
#include <libopencm3/lpc43xx/m4/nvic.h>
#include <libopencm3/cm3/systick.h>
#include <libopencm3/cm3/scs.h>
#include "hackrf_core.h"
/* Global counter incremented by SysTick Interrupt each millisecond */
volatile uint32_t g_ulSysTickCount;
uint32_t g_NbCyclePerSecond;
void systick_setup(void)
{
uint32_t systick_reload_val;
g_ulSysTickCount = 0;
/* Disable IRQ globally */
__asm__("cpsid i");
/* Set processor Clock as Source Clock */
systick_set_clocksource(STK_CTRL_CLKSOURCE);
/* Get SysTick calibration value to obtain by default 1 tick = 10ms */
systick_reload_val = systick_get_calib();
/*
* Calibration seems wrong on LPC43xx(TBC) for default Freq it assume System Clock is 12MHz but it is 12*17=204MHz
* Fix the Calibration value bu multiplication by 17
*/
systick_reload_val = (systick_reload_val*17);
/* To obtain 1ms per tick just divide by 10 the 10ms base tick and set the reload */
systick_reload_val = systick_reload_val/10;
systick_set_reload(systick_reload_val);
systick_interrupt_enable();
/* Start counting. */
systick_counter_enable();
/* Set SysTick Priority to maximum */
nvic_set_priority(NVIC_SYSTICK_IRQ, 0xFF);
/* Enable IRQ globally */
__asm__("cpsie i");
}
void scs_dwt_cycle_counter_enabled(void)
{
SCS_DEMCR |= SCS_DEMCR_TRCENA;
SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA;
}
uint32_t sys_tick_get_time_ms(void)
{
return g_ulSysTickCount;
}
uint32_t sys_tick_delta_time_ms(uint32_t start, uint32_t end)
{
#define MAX_T_U32 ((2^32)-1)
uint32_t diff;
if(end > start)
{
diff=end-start;
}else
{
diff=MAX_T_U32-(start-end)+1;
}
return diff;
}
void sys_tick_wait_time_ms(uint32_t wait_ms)
{
uint32_t start, end;
uint32_t tickms;
start = sys_tick_get_time_ms();
do
{
end = sys_tick_get_time_ms();
tickms = sys_tick_delta_time_ms(start, end);
}while(tickms < wait_ms);
}
/* Called each 1ms/1000Hz by interrupt
1) Count the number of cycle per second.
2) Increment g_ulSysTickCount counter.
*/
void sys_tick_handler(void)
{
if(g_ulSysTickCount==0)
{
/* Clear Cycle Counter*/
SCS_DWT_CYCCNT = 0;
}else if(g_ulSysTickCount==1000)
{
/* Capture number of cycle elapsed during 1 second */
g_NbCyclePerSecond = SCS_DWT_CYCCNT;
}
g_ulSysTickCount++;
}
uint32_t nb_inst_per_sec[16];
extern uint32_t test_nb_instruction_per_sec_100_nop_asm();
extern uint32_t test_nb_instruction_per_sec_105_nop_asm();
extern uint32_t test_nb_instruction_per_sec_110_nop_asm();
extern uint32_t test_nb_instruction_per_sec_115_nop_asm();
extern uint32_t test_nb_instruction_per_sec_120_nop_asm();
extern uint32_t test_nb_instruction_per_sec_150_nop_asm();
extern uint32_t test_nb_instruction_per_sec_200_nop_asm();
extern uint32_t test_nb_instruction_per_sec_1000_nop_asm();
#define LED1_TOGGLE() (gpio_toggle(PORT_LED1_3, (PIN_LED1)))
int main(void)
{
pin_setup();
enable_1v8_power();
cpu_clock_init();
scs_dwt_cycle_counter_enabled();
systick_setup();
gpio_clear(PORT_LED1_3, (PIN_LED1)); /* LED1 off */
/* Test number of instruction per second (MIPS) slow blink ON 1s, OFF 1s */
LED1_TOGGLE();
nb_inst_per_sec[0] = test_nb_instruction_per_sec_100_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[1]= test_nb_instruction_per_sec_105_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[2]= test_nb_instruction_per_sec_110_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[3]= test_nb_instruction_per_sec_115_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[4] = test_nb_instruction_per_sec_120_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[5] = test_nb_instruction_per_sec_150_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[6] = test_nb_instruction_per_sec_200_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[7] = test_nb_instruction_per_sec_1000_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[8] = test_nb_instruction_per_sec_100_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[9]= test_nb_instruction_per_sec_105_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[10]= test_nb_instruction_per_sec_110_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[11]= test_nb_instruction_per_sec_115_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[12] = test_nb_instruction_per_sec_120_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[13] = test_nb_instruction_per_sec_150_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[14] = test_nb_instruction_per_sec_200_nop_asm();
LED1_TOGGLE();
nb_inst_per_sec[15] = test_nb_instruction_per_sec_1000_nop_asm();
LED1_TOGGLE();
/* Test finished fast blink */
while (1)
{
gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */
gpio_set(PORT_LED1_3, (PIN_LED2)); /* LED2 on */
gpio_set(PORT_LED1_3, (PIN_LED3)); /* LED3 on */
sys_tick_wait_time_ms(250);
gpio_clear(PORT_LED1_3, (PIN_LED3)); /* LED3 off */
gpio_clear(PORT_LED1_3, (PIN_LED2)); /* LED2 off */
gpio_clear(PORT_LED1_3, (PIN_LED1)); /* LED1 off */
sys_tick_wait_time_ms(250);
}
return 0;
}

23
SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/.gitignore vendored
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@ -1,23 +0,0 @@
# kicad backup files
*.000
*.bak
*.bck
$savepcb.*
# gerber and drill files
*.gbl
*.gtl
*.gbr
*.gbr
*.gbs
*.gts
*.gbr
*.gbo
*.gto
*.gtp
*.drl
# other kicad generated files
*.csv
*.svg
*.pdf

219
SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/LNA915/LNA915-cache.lib
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@ -1,219 +0,0 @@
EESchema-LIBRARY Version 2.3 Date: Sun 13 Apr 2014 05:31:29 PM MDT
#encoding utf-8
#
# BF1118
#
DEF BF1118 U 0 40 Y Y 1 F N
F0 "U" 0 150 60 H V C CNN
F1 "BF1118" 0 -150 60 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
S -200 200 200 -200 0 1 0 N
X G 1 -500 50 300 R 50 50 1 1 I
X K 2 -500 -50 300 R 50 50 1 1 W
X S 3 500 -50 300 L 50 50 1 1 B
X D 4 500 50 300 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# BGB741L7ESD
#
DEF BGB741L7ESD U 0 40 Y Y 1 F N
F0 "U" 0 -100 60 V V C CNN
F1 "BGB741L7ESD" 0 -250 60 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
S -350 300 350 -300 0 1 0 N
X VCC 1 -650 100 300 R 50 50 1 1 W
X BIAS 2 -650 0 300 R 50 50 1 1 O
X RFIN 3 -650 -100 300 R 50 50 1 1 I
X RFOUT 4 650 -100 300 L 50 50 1 1 O
X VCTRL 5 650 0 300 L 50 50 1 1 I
X ADJ 6 650 100 300 L 50 50 1 1 I
X GND 7 0 600 300 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
# C
#
DEF C C 0 10 N Y 1 F N
F0 "C" 50 100 50 H V L CNN
F1 "C" 50 -100 50 H V L CNN
$FPLIST
SM*
C?
C1-1
$ENDFPLIST
DRAW
P 2 0 1 20 -100 -30 100 -30 N
P 2 0 1 20 -100 30 100 30 N
X ~ 1 0 200 170 D 40 40 1 1 P
X ~ 2 0 -200 170 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CONN_1
#
DEF ~CONN_1 P 0 30 N N 1 F N
F0 "P" 80 0 40 H V L CNN
F1 "CONN_1" 0 55 30 H I C CNN
DRAW
C 0 0 31 0 1 0 N
P 2 0 1 0 -30 0 -50 0 N
X 1 1 -150 0 100 R 60 60 1 1 P
ENDDRAW
ENDDEF
#
# DIODE
#
DEF DIODE D 0 40 N N 1 F N
F0 "D" 0 100 40 H V C CNN
F1 "DIODE" 0 -100 40 H V C CNN
$FPLIST
D?
S*
$ENDFPLIST
DRAW
P 2 0 1 6 50 50 50 -50 N
P 3 0 1 0 -50 50 50 0 -50 -50 F
X A 1 -200 0 150 R 40 40 1 1 P
X K 2 200 0 150 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# FAR-F5QA
#
DEF FAR-F5QA U 0 40 Y Y 1 F N
F0 "U" 0 0 60 V V C CNN
F1 "FAR-F5QA" 250 0 60 V V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
S -300 250 300 -250 0 1 0 N
X IN 1 -600 0 300 R 50 50 1 1 B
X GND 2 -100 -550 300 U 50 50 1 1 W
X GND 3 100 -550 300 U 50 50 1 1 W
X OUT 4 100 550 300 D 50 50 1 1 B
X GND 5 -100 550 300 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GND
#
DEF ~GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 0 30 H I C CNN
F1 "GND" 0 -70 30 H I C CNN
DRAW
P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
X GND 1 0 0 0 U 30 30 1 1 W N
ENDDRAW
ENDDEF
#
# GSG-DIODE-TVS-BI
#
DEF GSG-DIODE-TVS-BI D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "GSG-DIODE-TVS-BI" 0 -100 40 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
$FPLIST
D?
SO*
SM*
$ENDFPLIST
DRAW
P 5 0 1 8 -20 50 0 30 0 -30 20 -50 20 -50 N
P 5 0 1 0 0 0 -100 50 -100 -50 0 0 0 0 F
P 5 0 1 0 0 0 100 50 100 -50 0 0 0 0 F
X A 1 -250 0 150 R 40 40 1 1 P
X K 2 250 0 150 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# GSG-RF-CONN
#
DEF GSG-RF-CONN P 0 0 Y N 1 F N
F0 "P" 0 150 60 H V C CNN
F1 "GSG-RF-CONN" 0 -150 60 H V C CNN
F2 "~" 0 0 60 H V C CNN
F3 "~" 0 0 60 H V C CNN
DRAW
C 0 0 100 0 1 0 N
X RF 1 300 0 300 L 50 50 1 1 B
X GND 2 0 -400 300 U 50 50 1 1 W
ENDDRAW
ENDDEF
#
# INDUCTOR
#
DEF INDUCTOR L 0 40 N N 1 F N
F0 "L" -50 0 40 V V C CNN
F1 "INDUCTOR" 100 0 40 V V C CNN
DRAW
A 0 -150 50 -889 889 0 1 0 N 1 -199 1 -100
A 0 -49 51 -889 889 0 1 0 N 1 -99 1 2
A 0 51 51 -889 889 0 1 0 N 1 1 1 102
A 0 148 48 -889 889 0 1 0 N 1 101 1 196
X 1 1 0 300 100 D 70 70 1 1 P
X 2 2 0 -300 100 U 70 70 1 1 P
ENDDRAW
ENDDEF
#
# LED
#
DEF LED D 0 40 Y N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "LED" 0 -100 50 H V C CNN
$FPLIST
LED-3MM
LED-5MM
LED-10MM
LED-0603
LED-0805
LED-1206
LEDV
$ENDFPLIST
DRAW
P 2 0 1 0 50 50 50 -50 N
P 3 0 1 0 -50 50 50 0 -50 -50 F
P 3 0 1 0 65 -40 110 -80 105 -55 N
P 3 0 1 0 80 -25 125 -65 120 -40 N
X A 1 -200 0 150 R 40 40 1 1 P
X K 2 200 0 150 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# R
#
DEF R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "R" 0 0 50 V V C CNN
$FPLIST
R?
SM0603
SM0805
R?-*
SM1206
$ENDFPLIST
DRAW
S -40 150 40 -150 0 1 12 N
X ~ 1 0 250 100 D 60 60 1 1 P
X ~ 2 0 -250 100 U 60 60 1 1 P
ENDDRAW
ENDDEF
#
# VCC
#
DEF VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 100 30 H I C CNN
F1 "VCC" 0 100 30 H V C CNN
DRAW
X VCC 1 0 0 0 U 20 20 0 0 W N
C 0 50 20 0 1 0 N
P 3 0 1 0 0 0 0 30 0 30 N
ENDDRAW
ENDDEF
#
#End Library

1335
SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/LNA915/LNA915.kicad_pcb
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File diff suppressed because it is too large Load Diff

532
SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/LNA915/LNA915.net
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@ -1,532 +0,0 @@
(export (version D)
(design
(source /home/mossmann/src/hackrf/hardware/LNA915/LNA915.sch)
(date "Sun Feb 9 14:18:41 2014")
(tool "eeschema (2013-07-24 BZR 4024)-stable"))
(components
(comp (ref D3)
(value PIN)
(fields
(field (name Manufacturer) NXP)
(field (name "Part Number") BAP50-03)
(field (name Description) "DIODE PIN GP 50V 100MA SOD323"))
(libsource (lib device) (part DIODE))
(sheetpath (names /) (tstamps /))
(tstamp 52F440C5))
(comp (ref P1)
(value HACKRF)
(fields
(field (name Manufacturer) "Linx Technology")
(field (name "Part Number") CONSMA003.062)
(field (name Description) "CONN SMA JACK 50 OHM EDGE MNT"))
(libsource (lib hackrf) (part GSG-RF-CONN))
(sheetpath (names /) (tstamps /))
(tstamp 52F440F7))
(comp (ref D1)
(value GSG-DIODE-TVS-BI)
(fields
(field (name Manufacturer) Murata)
(field (name "Part Number") LXES15AAA1-100)
(field (name Description) "TVS DIODE ESD .05PF 15KV 0402"))
(libsource (lib hackrf) (part GSG-DIODE-TVS-BI))
(sheetpath (names /) (tstamps /))
(tstamp 52F44107))
(comp (ref C5)
(value 100pF)
(fields
(field (name Manufacturer) Murata)
(field (name "Part Number") GRM1555C1H101JA01D)
(field (name Description) "CAP CER 100PF 50V 5% NP0 0402"))
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 52F44170))
(comp (ref U2)
(value SAW)
(fields
(field (name Manufacturer) "Taiyo Yuden")
(field (name "Part Number") FAR-F5QA-915M00-M2AK-J)
(field (name Description) "FILTER SAW 915MHZ ISM900 SMD"))
(libsource (lib hackrf) (part FAR-F5QA))
(sheetpath (names /) (tstamps /))
(tstamp 52F44412))
(comp (ref D4)
(value LNALED)
(fields
(field (name Manufacturer) Everlight)
(field (name "Part Number") QTLP601C4TR)
(field (name Description) "LED GREEN STD BRIGHT 0603 SMD"))
(libsource (lib device) (part LED))
(sheetpath (names /) (tstamps /))
(tstamp 52F51772))
(comp (ref U3)
(value LNA)
(fields
(field (name Manufacturer) Infineon)
(field (name "Part Number") "BGB 741L7ESD E6327")
(field (name Description) "IC AMP MMIC LNA TSLP7-1"))
(libsource (lib hackrf) (part BGB741L7ESD))
(sheetpath (names /) (tstamps /))
(tstamp 52F68792))
(comp (ref R6)
(value 3k)
(fields
(field (name Manufacturer) Stackpole)
(field (name "Part Number") RMCF0402FT3K00)
(field (name Description) "RES 3K OHM 1/16W 1% 0402"))
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 52F68800))
(comp (ref L5)
(value 39nH)
(fields
(field (name Manufacturer) "Taiyo Yuden")
(field (name "Part Number") HK100539NJ-T)
(field (name Description) "INDUCTOR HI FREQ 39NH 5% 0402"))
(libsource (lib device) (part INDUCTOR))
(sheetpath (names /) (tstamps /))
(tstamp 52F688CD))
(comp (ref C10)
(value 1uF)
(fields
(field (name Manufacturer) "Taiyo Yuden")
(field (name "Part Number") LMK105BJ105KV-F)
(field (name Description) "CAP CER 1UF 10V 10% X5R 0402"))
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 52F68A00))
(comp (ref L3)
(value 39nH)
(fields
(field (name Manufacturer) "Taiyo Yuden")
(field (name "Part Number") HK100539NJ-T)
(field (name Description) "INDUCTOR HI FREQ 39NH 5% 0402"))
(libsource (lib device) (part INDUCTOR))
(sheetpath (names /) (tstamps /))
(tstamp 52F68C24))
(comp (ref L1)
(value 39nH)
(fields
(field (name Manufacturer) "Taiyo Yuden")
(field (name "Part Number") HK100539NJ-T)
(field (name Description) "INDUCTOR HI FREQ 39NH 5% 0402"))
(libsource (lib device) (part INDUCTOR))
(sheetpath (names /) (tstamps /))
(tstamp 52F68C64))
(comp (ref R7)
(value 470)
(fields
(field (name Manufacturer) Stackpole)
(field (name "Part Number") RMCF0402JT470R)
(field (name Description) "RES TF 1/16W 470 OHM 5% 0402"))
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 52F68CBB))
(comp (ref U1)
(value SWITCH)
(fields
(field (name Manufacturer) NXP)
(field (name "Part Number") BF1118,215)
(field (name Description) "IC RF SWITCH SOT143B"))
(libsource (lib hackrf) (part BF1118))
(sheetpath (names /) (tstamps /))
(tstamp 52F68FC4))
(comp (ref R1)
(value 47k)
(fields
(field (name Manufacturer) Stackpole)
(field (name "Part Number") RMCF0402JT47K0)
(field (name Description) "RES 47K OHM 1/16W 5% 0402"))
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 52F6905B))
(comp (ref R3)
(value 4k7)
(fields
(field (name Manufacturer) Stackpole)
(field (name "Part Number") RMCF0402JT4K70)
(field (name Description) "RES 4.7K OHM 1/16W 5% 0402 SMD"))
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 52F6921D))
(comp (ref R4)
(value 100k)
(fields
(field (name Manufacturer) Stackpole)
(field (name "Part Number") RMCF0402JT100K)
(field (name Description) "RES 100K OHM 1/16W 5% 0402"))
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 52F69223))
(comp (ref L4)
(value 39nH)
(fields
(field (name Manufacturer) "Taiyo Yuden")
(field (name "Part Number") HK100539NJ-T)
(field (name Description) "INDUCTOR HI FREQ 39NH 5% 0402"))
(libsource (lib device) (part INDUCTOR))
(sheetpath (names /) (tstamps /))
(tstamp 52F6975B))
(comp (ref L2)
(value 39nH)
(fields
(field (name Manufacturer) "Taiyo Yuden")
(field (name "Part Number") HK100539NJ-T)
(field (name Description) "INDUCTOR HI FREQ 39NH 5% 0402"))
(libsource (lib device) (part INDUCTOR))
(sheetpath (names /) (tstamps /))
(tstamp 52F69884))
(comp (ref C6)
(value 1nF)
(fields
(field (name Manufacturer) Murata)
(field (name "Part Number") GRM155R71H102KA01D)
(field (name Description) "CAP CER 1000PF 50V 10% X7R 0402"))
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 52F69BA3))
(comp (ref C7)
(value 100pF)
(fields
(field (name Manufacturer) Murata)
(field (name "Part Number") GRM1555C1H101JA01D)
(field (name Description) "CAP CER 100PF 50V 5% NP0 0402"))
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 52F69E98))
(comp (ref C8)
(value 100pF)
(fields
(field (name Manufacturer) Murata)
(field (name "Part Number") GRM1555C1H101JA01D)
(field (name Description) "CAP CER 100PF 50V 5% NP0 0402"))
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 52F69EB1))
(comp (ref C9)
(value 100pF)
(fields
(field (name Manufacturer) Murata)
(field (name "Part Number") GRM1555C1H101JA01D)
(field (name Description) "CAP CER 100PF 50V 5% NP0 0402"))
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 52F69EBA))
(comp (ref C2)
(value 100pF)
(fields
(field (name Manufacturer) Murata)
(field (name "Part Number") GRM1555C1H101JA01D)
(field (name Description) "CAP CER 100PF 50V 5% NP0 0402"))
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 52F69EC3))
(comp (ref C1)
(value 100pF)
(fields
(field (name Manufacturer) Murata)
(field (name "Part Number") GRM1555C1H101JA01D)
(field (name Description) "CAP CER 100PF 50V 5% NP0 0402"))
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 52F69ECC))
(comp (ref C11)
(value 1uF)
(fields
(field (name Manufacturer) "Taiyo Yuden")
(field (name "Part Number") LMK105BJ105KV-F)
(field (name Description) "CAP CER 1UF 10V 10% X5R 0402"))
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 52F69F2A))
(comp (ref D2)
(value GSG-DIODE-TVS-BI)
(fields
(field (name Manufacturer) Murata)
(field (name "Part Number") LXES15AAA1-100)
(field (name Description) "TVS DIODE ESD .05PF 15KV 0402"))
(libsource (lib hackrf) (part GSG-DIODE-TVS-BI))
(sheetpath (names /) (tstamps /))
(tstamp 52F69FCE))
(comp (ref P2)
(value ANTENNA)
(fields
(field (name Manufacturer) "Linx Technology")
(field (name "Part Number") CONSMA003.062)
(field (name Description) "CONN SMA JACK 50 OHM EDGE MNT"))
(libsource (lib hackrf) (part GSG-RF-CONN))
(sheetpath (names /) (tstamps /))
(tstamp 52F6A116))
(comp (ref R5)
(value 470)
(fields
(field (name Manufacturer) Stackpole)
(field (name "Part Number") RMCF0402JT470R)
(field (name Description) "RES TF 1/16W 470 OHM 5% 0402"))
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 52F6A21F))
(comp (ref C4)
(value 1nF)
(fields
(field (name Manufacturer) Murata)
(field (name "Part Number") GRM155R71H102KA01D)
(field (name Description) "CAP CER 1000PF 50V 10% X7R 0402"))
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 52F6A3F1))
(comp (ref C3)
(value 1nF)
(fields
(field (name Manufacturer) Murata)
(field (name "Part Number") GRM155R71H102KA01D)
(field (name Description) "CAP CER 1000PF 50V 10% X7R 0402"))
(libsource (lib device) (part C))
(sheetpath (names /) (tstamps /))
(tstamp 52F6A40A))
(comp (ref R2)
(value 100k)
(fields
(field (name Manufacturer) Stackpole)
(field (name "Part Number") RMCF0402JT100K)
(field (name Description) "RES 100K OHM 1/16W 5% 0402"))
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 52F6A598))
(comp (ref P3)
(value CONN_1)
(libsource (lib conn) (part CONN_1))
(sheetpath (names /) (tstamps /))
(tstamp 52F7A9D0))
(comp (ref P4)
(value CONN_1)
(libsource (lib conn) (part CONN_1))
(sheetpath (names /) (tstamps /))
(tstamp 52F7A9E7)))
(libparts
(libpart (lib device) (part C)
(description "Condensateur non polarise")
(footprints
(fp SM*)
(fp C?)
(fp C1-1))
(fields
(field (name Reference) C)
(field (name Value) C))
(pins
(pin (num 1) (name ~) (type passive))
(pin (num 2) (name ~) (type passive))))
(libpart (lib device) (part DIODE)
(description "Diode simple")
(footprints
(fp D?)
(fp S*))
(fields
(field (name Reference) D)
(field (name Value) DIODE))
(pins
(pin (num 1) (name A) (type passive))
(pin (num 2) (name K) (type passive))))
(libpart (lib device) (part INDUCTOR)
(fields
(field (name Reference) L)
(field (name Value) INDUCTOR))
(pins
(pin (num 1) (name 1) (type passive))
(pin (num 2) (name 2) (type passive))))
(libpart (lib device) (part LED)
(footprints
(fp LED-3MM)
(fp LED-5MM)
(fp LED-10MM)
(fp LED-0603)
(fp LED-0805)
(fp LED-1206)
(fp LEDV))
(fields
(field (name Reference) D)
(field (name Value) LED))
(pins
(pin (num 1) (name A) (type passive))
(pin (num 2) (name K) (type passive))))
(libpart (lib device) (part R)
(description Resistance)
(footprints
(fp R?)
(fp SM0603)
(fp SM0805)
(fp R?-*)
(fp SM1206))
(fields
(field (name Reference) R)
(field (name Value) R))
(pins
(pin (num 1) (name ~) (type passive))
(pin (num 2) (name ~) (type passive))))
(libpart (lib conn) (part CONN_1)
(description "1 pin")
(fields
(field (name Reference) P)
(field (name Value) CONN_1))
(pins
(pin (num 1) (name 1) (type passive))))
(libpart (lib hackrf) (part BF1118)
(fields
(field (name Reference) U)
(field (name Value) BF1118)
(field (name Footprint) ~)
(field (name Datasheet) ~))
(pins
(pin (num 1) (name G) (type input))
(pin (num 2) (name K) (type power_in))
(pin (num 3) (name S) (type BiDi))
(pin (num 4) (name D) (type BiDi))))
(libpart (lib hackrf) (part BGB741L7ESD)
(fields
(field (name Reference) U)
(field (name Value) BGB741L7ESD)
(field (name Footprint) ~)
(field (name Datasheet) ~))
(pins
(pin (num 1) (name VCC) (type power_in))
(pin (num 2) (name BIAS) (type output))
(pin (num 3) (name RFIN) (type input))
(pin (num 4) (name RFOUT) (type output))
(pin (num 5) (name VCTRL) (type input))
(pin (num 6) (name ADJ) (type input))
(pin (num 7) (name GND) (type power_in))))
(libpart (lib hackrf) (part FAR-F5QA)
(fields
(field (name Reference) U)
(field (name Value) FAR-F5QA)
(field (name Footprint) ~)
(field (name Datasheet) ~))
(pins
(pin (num 1) (name IN) (type BiDi))
(pin (num 2) (name GND) (type power_in))
(pin (num 3) (name GND) (type power_in))
(pin (num 4) (name OUT) (type BiDi))
(pin (num 5) (name GND) (type power_in))))
(libpart (lib hackrf) (part GSG-DIODE-TVS-BI)
(description "Diode zener")
(footprints
(fp D?)
(fp SO*)
(fp SM*))
(fields
(field (name Reference) D)
(field (name Value) GSG-DIODE-TVS-BI)
(field (name Footprint) ~)
(field (name Datasheet) ~))
(pins
(pin (num 1) (name A) (type passive))
(pin (num 2) (name K) (type passive))))
(libpart (lib hackrf) (part GSG-RF-CONN)
(fields
(field (name Reference) P)
(field (name Value) GSG-RF-CONN)
(field (name Footprint) ~)
(field (name Datasheet) ~))
(pins
(pin (num 1) (name RF) (type BiDi))
(pin (num 2) (name GND) (type power_in)))))
(libraries
(library (logical device)
(uri /usr/local/share/kicad/library/device.lib))
(library (logical conn)
(uri /usr/local/share/kicad/library/conn.lib))
(library (logical hackrf)
(uri ../kicad/hackrf.lib)))
(nets
(net (code 1) (name VCC)
(node (ref R1) (pin 1))
(node (ref R7) (pin 1))
(node (ref L1) (pin 2))
(node (ref R3) (pin 1))
(node (ref R4) (pin 2))
(node (ref C11) (pin 2))
(node (ref U3) (pin 1))
(node (ref R5) (pin 1))
(node (ref U3) (pin 5))
(node (ref C4) (pin 2))
(node (ref C3) (pin 2))
(node (ref R2) (pin 2))
(node (ref L5) (pin 1))
(node (ref R6) (pin 1)))
(net (code 2) (name "")
(node (ref C8) (pin 1))
(node (ref D3) (pin 2))
(node (ref L4) (pin 2)))
(net (code 3) (name GND)
(node (ref U2) (pin 5))
(node (ref U2) (pin 3))
(node (ref U3) (pin 7))
(node (ref D4) (pin 2))
(node (ref U2) (pin 2))
(node (ref C10) (pin 1))
(node (ref U1) (pin 2))
(node (ref D1) (pin 1))
(node (ref P1) (pin 2))
(node (ref C3) (pin 1))
(node (ref L4) (pin 1))
(node (ref C6) (pin 1))
(node (ref P4) (pin 1))
(node (ref P3) (pin 1))
(node (ref R2) (pin 1))
(node (ref C4) (pin 1))
(node (ref P2) (pin 2))
(node (ref C11) (pin 1))
(node (ref D2) (pin 1))
(node (ref R4) (pin 1)))
(net (code 4) (name "")
(node (ref U1) (pin 3))
(node (ref C1) (pin 2)))
(net (code 5) (name "")
(node (ref U1) (pin 4))
(node (ref C2) (pin 1))
(node (ref R1) (pin 2)))
(net (code 6) (name "")
(node (ref L2) (pin 1))
(node (ref C7) (pin 2))
(node (ref D3) (pin 1)))
(net (code 7) (name "")
(node (ref U1) (pin 1))
(node (ref R3) (pin 2)))
(net (code 8) (name "")
(node (ref P2) (pin 1))
(node (ref C5) (pin 1))
(node (ref D2) (pin 2)))
(net (code 9) (name "")
(node (ref R7) (pin 2))
(node (ref D4) (pin 1)))
(net (code 10) (name "")
(node (ref U2) (pin 4))
(node (ref C1) (pin 1))
(node (ref C7) (pin 1)))
(net (code 11) (name "")
(node (ref L2) (pin 2))
(node (ref C6) (pin 2))
(node (ref R5) (pin 2)))
(net (code 12) (name "")
(node (ref C5) (pin 2))
(node (ref U2) (pin 1)))
(net (code 13) (name "")
(node (ref R6) (pin 2))
(node (ref U3) (pin 6)))
(net (code 14) (name "")
(node (ref C9) (pin 2))
(node (ref P1) (pin 1))
(node (ref D1) (pin 2))
(node (ref L1) (pin 1))
(node (ref C2) (pin 2)))
(net (code 15) (name "")
(node (ref L5) (pin 2))
(node (ref C9) (pin 1))
(node (ref U3) (pin 4)))
(net (code 16) (name "")
(node (ref L3) (pin 1))
(node (ref U3) (pin 3))
(node (ref C8) (pin 2)))
(net (code 17) (name "")
(node (ref U3) (pin 2))
(node (ref C10) (pin 2))
(node (ref L3) (pin 2)))))

88
SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/LNA915/LNA915.pro
View File

@ -1,88 +0,0 @@
update=Sat Feb 8 14:35:27 2014
version=1
last_client=pcbnew
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[general]
version=1
[eeschema]
version=1
LibDir=../kicad
NetFmtName=
RptD_X=0
RptD_Y=100
RptLab=1
LabSize=60
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=special
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves
LibName31=hackrf
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=" 0.600000"
PadDrillOvalY=" 0.600000"
PadSizeH=" 1.500000"
PadSizeV=" 1.500000"
PcbTextSizeV=" 1.500000"
PcbTextSizeH=" 1.500000"
PcbTextThickness=" 0.300000"
ModuleTextSizeV=" 1.000000"
ModuleTextSizeH=" 1.000000"
ModuleTextSizeThickness=" 0.150000"
SolderMaskClearance=" 0.000000"
SolderMaskMinWidth=" 0.000000"
DrawSegmentWidth=" 0.200000"
BoardOutlineThickness=" 0.100000"
ModuleOutlineThickness=" 0.150000"
[pcbnew/libraries]
LibDir=../kicad
LibName1=sockets
LibName2=connect
LibName3=discret
LibName4=pin_array
LibName5=divers
LibName6=smd_capacitors
LibName7=smd_resistors
LibName8=smd_crystal&oscillator
LibName9=smd_dil
LibName10=smd_transistors
LibName11=libcms
LibName12=display
LibName13=led
LibName14=dip_sockets
LibName15=pga_sockets
LibName16=valves
LibName17=hackrf

890
SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/LNA915/LNA915.sch
View File

@ -1,890 +0,0 @@
EESchema Schematic File Version 2 date Sun 13 Apr 2014 05:31:29 PM MDT
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:hackrf
LIBS:LNA915-cache
EELAYER 27 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date "13 apr 2014"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
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F 4 "NXP" H 4650 5250 60 0001 C CNN "Manufacturer"
F 5 "BAP50-03" H 4650 5250 60 0001 C CNN "Part Number"
F 6 "DIODE PIN GP 50V 100MA SOD323" H 4650 5250 60 0001 C CNN "Description"
1 4650 5250
1 0 0 -1
$EndComp
$Comp
L GSG-RF-CONN P1
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F 0 "P1" H 9750 3900 60 0000 C CNN
F 1 "HACKRF" H 9750 3600 60 0000 C CNN
F 2 "~" H 9750 3750 60 0000 C CNN
F 3 "~" H 9750 3750 60 0000 C CNN
F 4 "Linx Technology" H 9750 3750 60 0001 C CNN "Manufacturer"
F 5 "CONSMA003.062" H 9750 3750 60 0001 C CNN "Part Number"
F 6 "CONN SMA JACK 50 OHM EDGE MNT" H 9750 3750 60 0001 C CNN "Description"
1 9750 3750
-1 0 0 -1
$EndComp
$Comp
L GSG-DIODE-TVS-BI D1
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F 0 "D1" H 9350 4200 50 0000 C CNN
F 1 "GSG-DIODE-TVS-BI" H 9350 4000 40 0000 C CNN
F 2 "~" H 9350 4100 60 0000 C CNN
F 3 "~" H 9350 4100 60 0000 C CNN
F 4 "Murata" H 9350 4100 60 0001 C CNN "Manufacturer"
F 5 "LXES15AAA1-100" H 9350 4100 60 0001 C CNN "Part Number"
F 6 "TVS DIODE ESD .05PF 15KV 0402" H 9350 4100 60 0001 C CNN "Description"
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0 -1 -1 0
$EndComp
$Comp
L GND #PWR01
U 1 1 52F44137
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F 0 "#PWR01" H 9750 4250 30 0001 C CNN
F 1 "GND" H 9750 4180 30 0001 C CNN
1 9750 4250
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$EndComp
$Comp
L GND #PWR02
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F 1 "GND" H 9350 4380 30 0001 C CNN
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$EndComp
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$Comp
L GND #PWR03
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F 1 "GND" H 1600 4530 30 0001 C CNN
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$EndComp
Wire Wire Line
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$Comp
L GND #PWR04
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1 0 0 -1
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$Comp
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$EndComp
Wire Wire Line
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$Comp
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$Comp
L GND #PWR06
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$Comp
L GND #PWR07
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$Comp
L LED D4
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F 1 "LNALED" H 10400 6150 50 0000 C CNN
F 4 "Everlight" H 10400 6250 60 0001 C CNN "Manufacturer"
F 5 "QTLP601C4TR" H 10400 6250 60 0001 C CNN "Part Number"
F 6 "LED GREEN STD BRIGHT 0603 SMD" H 10400 6250 60 0001 C CNN "Description"
1 10400 6250
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$EndComp
$Comp
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F 3 "~" H 7100 5150 60 0000 C CNN
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$EndComp
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Wire Wire Line
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Wire Wire Line
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$EndComp
$Comp
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F 0 "#PWR010" H 7850 4450 30 0001 C CNN
F 1 "VCC" H 7850 4450 30 0000 C CNN
1 7850 4350
1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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F 0 "#PWR011" H 7850 5250 30 0001 C CNN
F 1 "VCC" H 7850 5250 30 0000 C CNN
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 5550 5250
$Comp
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$Comp
L VCC #PWR012
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$Comp
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$EndComp
Wire Wire Line
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$Comp
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F 1 "GND" H 6350 5780 30 0001 C CNN
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Wire Wire Line
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F 1 "GND" H 7850 6580 30 0001 C CNN
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$Comp
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$Comp
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Wire Wire Line
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$Comp
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$Comp
L VCC #PWR017
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F 5 "BF1118,215" H 6000 1850 60 0001 C CNN "Part Number"
F 6 "IC RF SWITCH SOT143B" H 6000 1850 60 0001 C CNN "Description"
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0 1 -1 0
$EndComp
Wire Wire Line
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Wire Wire Line
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$Comp
L R R1
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1 0 0 1
$EndComp
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$Comp
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-1 0 0 -1
$EndComp
$Comp
L GND #PWR019
U 1 1 52F6916B
P 6450 2650
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-1 0 0 -1
$EndComp
$Comp
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$EndComp
$Comp
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$EndComp
$Comp
L R R4
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$EndComp
$Comp
L GND #PWR021
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$EndComp
$Comp
L GND #PWR022
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$EndComp
$Comp
L VCC #PWR023
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1 6450 3050
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$EndComp
Wire Wire Line
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$Comp
L GND #PWR024
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-1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
6450 2550 6450 2650
Wire Wire Line
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Wire Wire Line
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Connection ~ 6450 1950
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 6050 3050
Connection ~ 6350 3050
Text Notes 9600 3150 0 60 ~ 0
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$Comp
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$EndComp
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Wire Wire Line
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Wire Wire Line
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$Comp
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-1 0 0 1
$EndComp
$Comp
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1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 4350 5250
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$Comp
L C C6
U 1 1 52F69BA3
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F 1 "1nF" H 4700 4350 50 0000 L CNN
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F 6 "CAP CER 1000PF 50V 10% X7R 0402" H 4650 4450 60 0001 C CNN "Description"
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0 1 -1 0
$EndComp
Wire Wire Line
4350 4450 4450 4450
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$Comp
L GND #PWR027
U 1 1 52F69D57
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F 0 "#PWR027" H 4950 4450 30 0001 C CNN
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0 -1 -1 0
$EndComp
Wire Wire Line
4950 4450 4850 4450
Text Notes 4950 800 0 60 ~ 0
TX path (filter, no amplification) switched on when power is not applied
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RX path (filter and amplification) switched on when power is applied\n
$Comp
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F 1 "100pF" H 4100 5150 50 0000 L CNN
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F 5 "GRM1555C1H101JA01D" H 4050 5250 60 0001 C CNN "Part Number"
F 6 "CAP CER 100PF 50V 5% NP0 0402" H 4050 5250 60 0001 C CNN "Description"
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0 -1 -1 0
$EndComp
$Comp
L C C8
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0 -1 -1 0
$EndComp
$Comp
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F 5 "GRM1555C1H101JA01D" H 8250 5250 60 0001 C CNN "Part Number"
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$EndComp
$Comp
L C C2
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F 5 "GRM1555C1H101JA01D" H 6750 1250 60 0001 C CNN "Part Number"
F 6 "CAP CER 100PF 50V 5% NP0 0402" H 6750 1250 60 0001 C CNN "Description"
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0 -1 -1 0
$EndComp
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L C C1
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F 6 "CAP CER 100PF 50V 5% NP0 0402" H 5650 1250 60 0001 C CNN "Description"
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$EndComp
$Comp
L C C11
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-1 0 0 1
$EndComp
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L GSG-DIODE-TVS-BI D2
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F 0 "D2" H 1600 4350 50 0000 C CNN
F 1 "GSG-DIODE-TVS-BI" H 1600 4150 40 0000 C CNN
F 2 "~" H 1600 4250 60 0000 C CNN
F 3 "~" H 1600 4250 60 0000 C CNN
F 4 "Murata" H 1600 4250 60 0001 C CNN "Manufacturer"
F 5 "LXES15AAA1-100" H 1600 4250 60 0001 C CNN "Part Number"
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$EndComp
$Comp
L GSG-RF-CONN P2
U 1 1 52F6A116
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F 3 "~" H 1200 3900 60 0000 C CNN
F 4 "Linx Technology" H 1200 3900 60 0001 C CNN "Manufacturer"
F 5 "CONSMA003.062" H 1200 3900 60 0001 C CNN "Part Number"
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$EndComp
$Comp
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$EndComp
$Comp
L C C4
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$EndComp
$Comp
L C C3
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F 5 "GRM155R71H102KA01D" H 6750 2250 60 0001 C CNN "Part Number"
F 6 "CAP CER 1000PF 50V 10% X7R 0402" H 6750 2250 60 0001 C CNN "Description"
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$EndComp
Wire Wire Line
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$Comp
L R R2
U 1 1 52F6A598
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F 5 "RMCF0402JT100K" H 6450 2300 60 0001 C CNN "Part Number"
F 6 "RES 100K OHM 1/16W 5% 0402" H 6450 2300 60 0001 C CNN "Description"
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$EndComp
$Comp
L CONN_1 P3
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$Comp
L CONN_1 P4
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$Comp
L GND #PWR028
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$Comp
L GND #PWR029
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F 0 "#PWR029" H 1900 6900 30 0001 C CNN
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1 0 0 -1
$EndComp
Wire Wire Line
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grounded mounting holes
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11076
SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/hackrf-one/PlasticCase_CAD/HackRF_One_Case.dxf
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4
SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/hackrf-one/SoBv1_HackRF_One_16Janv2014/README
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@ -1,4 +0,0 @@
This is a case design for HackRF One following the Dangerous Prototypes Sick of
Beige style:
http://dangerousprototypes.com/docs/Sick_of_Beige_compatible_cases

2
SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/hackrf-one/SoBv1_HackRF_One_16Janv2014/SoBv1_HackRF_One-Bottom_laser_cutting_431mm_Easy.txt
View File

@ -1,2 +0,0 @@
For file SoBv1_HackRF_One_Bottom.svg:
Laser cutting size 431mm => Seeed Studio Difficulty Easy (Length of Cutting line Below 60cm)

3
SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/hackrf-one/SoBv1_HackRF_One_16Janv2014/SoBv1_HackRF_One-Top_laser_cutting_800mm_Normal.txt
View File

@ -1,3 +0,0 @@
For file SoBv1_HackRF_One_Top.svg:
Laser cutting size 800 mm => Seeed Studio Difficulty Normal (Length of Cutting line Between 60cm and 180cm)

BIN
SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/hackrf-one/SoBv1_HackRF_One_16Janv2014/SoBv1_HackRF_One_Bottom2D.png
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SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/hackrf-one/SoBv1_HackRF_One_16Janv2014/SoBv1_HackRF_One_Bottom2D.skp
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SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/hackrf-one/SoBv1_HackRF_One_16Janv2014/SoBv1_HackRF_One_Top2D+HackRF_OneTOP.png
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SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/hackrf-one/SoBv1_HackRF_One_16Janv2014/SoBv1_HackRF_One_Top2D+HackRF_OneTOP.skp
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BIN
SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/hackrf-one/SoBv1_HackRF_One_16Janv2014/SoBv1_HackRF_One_Top2D.png
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53246
SoftwareDefined/HackRF/hackrf-2015.07.2/hardware/hackrf-one/hackrf-one.brd
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99
SoftwareDefined/HackRF/hackrf-2015.07.2/host/README.md
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@ -1,99 +0,0 @@
This repository contains host software (Linux/Windows) for HackRF, a project to
produce a low cost, open source software radio platform.
##How to build the host software on Linux:
###Prerequisites for Linux (Debian/Ubuntu):
`sudo apt-get install build-essential cmake libusb-1.0-0-dev`
###Build host software on Linux:
`cd host`
`mkdir build`
`cd build`
`cmake ../ -DINSTALL_UDEV_RULES=ON`
`make`
`sudo make install`
`sudo ldconfig`
##Clean CMake temporary files/dirs:
`cd host/build`
`rm -rf *`
##How to build host software on Windows:
###Prerequisites for cygwin or mingw:
* cmake-2.8.12.1 or more see http://www.cmake.org/cmake/resources/software.html
* libusbx-1.0.18 or more see http://sourceforge.net/projects/libusbx/files/latest/download?source=files
* Install Windows driver for HackRF hardware or use Zadig see http://sourceforge.net/projects/libwdi/files/zadig
- If you want to use Zadig select HackRF USB device and just install/replace it with WinUSB driver.
>**Note for Windows build:**
You shall always execute hackrf-tools from Windows command shell and not from Cygwin or Mingw shell because on Cygwin/Mingw
Ctrl C is not managed correctly and especially for hackrf_transfer the Ctrl C(abort) will not stop correctly and will corrupt the file.
###For Cygwin:
`cd host`
`mkdir build`
`cd build`
`cmake ../ -G "Unix Makefiles" -DCMAKE_LEGACY_CYGWIN_WIN32=1 -DLIBUSB_INCLUDE_DIR=/usr/local/include/libusb-1.0/`
`make`
`make install`
###For MinGW:
`cd host`
`mkdir build`
`cd build`
Normal version:
*
`cmake ../ -G "MSYS Makefiles" -DLIBUSB_INCLUDE_DIR=/usr/local/include/libusb-1.0/`
Debug version:
*
`cmake ../ -G "MSYS Makefiles" -DCMAKE_BUILD_TYPE=Debug -DLIBUSB_INCLUDE_DIR=/usr/local/include/libusb-1.0/`
`make`
`make install`
###For Visual Studio 2012 x64
`c:\hackrf\host\cmake>cmake ../ -G "Visual Studio 11 2012 Win64" -DLIBUSB_INCLUDE_DIR=c:\libusb-1.0.18-win\include\libusb-1.0 -DLIBUSB_LIBRARIES=c:\libusb-1.0.18-win\MS64\static\libusb-1.0.lib -DTHREADS_PTHREADS_INCLUDE_DIR=c:\pthreads-w32-2-9-1-release\Pre-built.2\include -DTHREADS_PTHREADS_WIN32_LIBRARY=c:\pthreads-w32-2-9-1-release\Pre-built.2\lib\x64\pthreadVC2.lib`
Solution file: `c:\hackrf\host\cmake\hackrf_all.sln`
##How to build host the software on FreeBSD
You can use the binary package:
`# pkg install hackrf`
You can build and install from ports:
`# cd /usr/ports/comms/hackrf`
`# make install`
principal author: Michael Ossmann <mike@ossmann.com>
http://greatscottgadgets.com/hackrf/

34
SoftwareDefined/HackRF/hackrf-2015.07.2/host/hackrf-tools/Readme.md
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@ -1,34 +0,0 @@
This repository contains hardware designs and software for HackRF, a project to
produce a low cost, open source software radio platform.
![Jawbreaker](https://raw.github.com/mossmann/hackrf/master/doc/jawbreaker.jpeg)
How to build host software on Windows:
prerequisite for cygwin or mingw:
* cmake-2.8.10.2 or more see http://www.cmake.org/cmake/resources/software.html
* libusbx-1.0.14 or more see http://sourceforge.net/projects/libusbx/files/latest/download?source=files
* Install Windows driver for HackRF hardware or use Zadig see http://sourceforge.net/projects/libwdi/files/zadig
- If you want to use Zadig select HackRF USB device and just install/replace it with WinUSB driver.
* Build libhackrf before to build this library, see host/libhackrf/Readme.md.
For Cygwin:
cmake -G "Unix Makefiles" -DCMAKE_LEGACY_CYGWIN_WIN32=1 -DLIBUSB_INCLUDE_DIR=/usr/local/include/libusb-1.0/
make
make install
For Mingw:
#normal version
cmake -G "MSYS Makefiles" -DLIBUSB_INCLUDE_DIR=/usr/local/include/libusb-1.0/
#debug version
cmake -G "MSYS Makefiles" -DCMAKE_BUILD_TYPE=Debug -DLIBUSB_INCLUDE_DIR=/usr/local/include/libusb-1.0/
make
make install
How to build host software on Linux:
cmake ./
make
make install
principal author: Michael Ossmann <mike@ossmann.com>
http://greatscottgadgets.com/hackrf/

71
SoftwareDefined/HackRF/hackrf-2015.07.2/host/hackrf-tools/src/CMakeLists.txt
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@ -1,71 +0,0 @@
# Copyright 2012 Jared Boone
# Copyright 2013 Benjamin Vernoux
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
# Based heavily upon the libftdi cmake setup.
set(INSTALL_DEFAULT_BINDIR "bin" CACHE STRING "Appended to CMAKE_INSTALL_PREFIX")
if(MSVC)
add_library(libgetopt_static STATIC
../getopt/getopt.c
)
endif()
add_executable(hackrf_max2837 hackrf_max2837.c)
install(TARGETS hackrf_max2837 RUNTIME DESTINATION ${INSTALL_DEFAULT_BINDIR})
add_executable(hackrf_si5351c hackrf_si5351c.c)
install(TARGETS hackrf_si5351c RUNTIME DESTINATION ${INSTALL_DEFAULT_BINDIR})
add_executable(hackrf_transfer hackrf_transfer.c)
install(TARGETS hackrf_transfer RUNTIME DESTINATION ${INSTALL_DEFAULT_BINDIR})
add_executable(hackrf_rffc5071 hackrf_rffc5071.c)
install(TARGETS hackrf_rffc5071 RUNTIME DESTINATION ${INSTALL_DEFAULT_BINDIR})
add_executable(hackrf_spiflash hackrf_spiflash.c)
install(TARGETS hackrf_spiflash RUNTIME DESTINATION ${INSTALL_DEFAULT_BINDIR})
add_executable(hackrf_cpldjtag hackrf_cpldjtag.c)
install(TARGETS hackrf_cpldjtag RUNTIME DESTINATION ${INSTALL_DEFAULT_BINDIR})
add_executable(hackrf_info hackrf_info.c)
install(TARGETS hackrf_info RUNTIME DESTINATION ${INSTALL_DEFAULT_BINDIR})
if(NOT libhackrf_SOURCE_DIR)
include_directories(${LIBHACKRF_INCLUDE_DIR})
LIST(APPEND TOOLS_LINK_LIBS ${LIBHACKRF_LIBRARIES})
else()
LIST(APPEND TOOLS_LINK_LIBS hackrf)
endif()
if(MSVC)
LIST(APPEND TOOLS_LINK_LIBS libgetopt_static)
endif()
target_link_libraries(hackrf_max2837 ${TOOLS_LINK_LIBS})
target_link_libraries(hackrf_si5351c ${TOOLS_LINK_LIBS})
target_link_libraries(hackrf_transfer ${TOOLS_LINK_LIBS})
target_link_libraries(hackrf_rffc5071 ${TOOLS_LINK_LIBS})
target_link_libraries(hackrf_spiflash ${TOOLS_LINK_LIBS})
target_link_libraries(hackrf_cpldjtag ${TOOLS_LINK_LIBS})
target_link_libraries(hackrf_info ${TOOLS_LINK_LIBS})

179
SoftwareDefined/HackRF/hackrf-2015.07.2/host/hackrf-tools/src/hackrf_max2837.c
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/*
* Copyright 2012 Jared Boone <jared@sharebrained.com>
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <hackrf.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <getopt.h>
static void usage() {
printf("\nUsage:\n");
printf("\t-n, --register <n>: set register number for subsequent read/write operations\n");
printf("\t-r, --read: read register specified by last -n argument, or all registers\n");
printf("\t-w, --write <v>: write register specified by last -n argument with value <v>\n");
printf("\nExamples:\n");
printf("\t<command> -n 12 -r # reads from register 12\n");
printf("\t<command> -r # reads all registers\n");
printf("\t<command> -n 10 -w 22 # writes register 10 with 22 decimal\n");
}
static struct option long_options[] = {
{ "register", required_argument, 0, 'n' },
{ "write", required_argument, 0, 'w' },
{ "read", no_argument, 0, 'r' },
{ 0, 0, 0, 0 },
};
int parse_int(char* s, uint16_t* const value) {
uint_fast8_t base = 10;
char* s_end;
long long_value;
if( strlen(s) > 2 ) {
if( s[0] == '0' ) {
if( (s[1] == 'x') || (s[1] == 'X') ) {
base = 16;
s += 2;
} else if( (s[1] == 'b') || (s[1] == 'B') ) {
base = 2;
s += 2;
}
}
}
s_end = s;
long_value = strtol(s, &s_end, base);
if( (s != s_end) && (*s_end == 0) ) {
*value = (uint16_t)long_value;
return HACKRF_SUCCESS;
} else {
return HACKRF_ERROR_INVALID_PARAM;
}
}
int dump_register(hackrf_device* device, const uint16_t register_number) {
uint16_t register_value;
int result = hackrf_max2837_read(device, (uint8_t)register_number, &register_value);
if( result == HACKRF_SUCCESS ) {
printf("[%2d] -> 0x%03x\n", register_number, register_value);
} else {
printf("hackrf_max2837_read() failed: %s (%d)\n", hackrf_error_name(result), result);
}
return result;
}
int dump_registers(hackrf_device* device) {
uint16_t register_number;
int result = HACKRF_SUCCESS;
for(register_number=0; register_number<32; register_number++) {
result = dump_register(device, register_number);
if( result != HACKRF_SUCCESS ) {
break;
}
}
return result;
}
int write_register(
hackrf_device* device,
const uint16_t register_number,
const uint16_t register_value
) {
int result = HACKRF_SUCCESS;
result = hackrf_max2837_write(device, (uint8_t)register_number, register_value);
if( result == HACKRF_SUCCESS ) {
printf("0x%03x -> [%2d]\n", register_value, register_number);
} else {
printf("hackrf_max2837_write() failed: %s (%d)\n", hackrf_error_name(result), result);
}
return result;
}
#define REGISTER_INVALID 32767
int main(int argc, char** argv) {
int opt;
uint16_t register_number = REGISTER_INVALID;
uint16_t register_value;
hackrf_device* device = NULL;
int option_index = 0;
int result = hackrf_init();
if( result ) {
printf("hackrf_init() failed: %s (%d)\n", hackrf_error_name(result), result);
return -1;
}
result = hackrf_open(&device);
if( result ) {
printf("hackrf_open() failed: %s (%d)\n", hackrf_error_name(result), result);
return -1;
}
while( (opt = getopt_long(argc, argv, "n:rw:", long_options, &option_index)) != EOF ) {
switch( opt ) {
case 'n':
result = parse_int(optarg, &register_number);
break;
case 'w':
result = parse_int(optarg, &register_value);
if( result == HACKRF_SUCCESS ) {
result = write_register(device, register_number, register_value);
}
break;
case 'r':
if( register_number == REGISTER_INVALID ) {
result = dump_registers(device);
} else {
result = dump_register(device, register_number);
}
break;
default:
usage();
}
if( result != HACKRF_SUCCESS ) {
printf("argument error: %s (%d)\n", hackrf_error_name(result), result);
break;
}
}
result = hackrf_close(device);
if( result ) {
printf("hackrf_close() failed: %s (%d)\n", hackrf_error_name(result), result);
return -1;
}
hackrf_exit();
return 0;
}

181
SoftwareDefined/HackRF/hackrf-2015.07.2/host/hackrf-tools/src/hackrf_rffc5071.c
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@ -1,181 +0,0 @@
/*
* Copyright 2012 Jared Boone <jared@sharebrained.com>
* Copyright 2013 Benjamin Vernoux <titanmkd@gmail.com>
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <hackrf.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <getopt.h>
static void usage() {
printf("\nUsage:\n");
printf("\t-n, --register <n>: set register number for subsequent read/write operations\n");
printf("\t-r, --read: read register specified by last -n argument, or all registers\n");
printf("\t-w, --write <v>: write register specified by last -n argument with value <v>\n");
printf("\nExamples:\n");
printf("\t<command> -n 12 -r # reads from register 12\n");
printf("\t<command> -r # reads all registers\n");
printf("\t<command> -n 10 -w 514 # writes register 10 with 514 decimal\n");
}
static struct option long_options[] = {
{ "register", required_argument, 0, 'n' },
{ "write", required_argument, 0, 'w' },
{ "read", no_argument, 0, 'r' },
{ 0, 0, 0, 0 },
};
int parse_int(char* s, uint16_t* const value) {
uint_fast8_t base = 10;
char* s_end;
long long_value;
if( strlen(s) > 2 ) {
if( s[0] == '0' ) {
if( (s[1] == 'x') || (s[1] == 'X') ) {
base = 16;
s += 2;
} else if( (s[1] == 'b') || (s[1] == 'B') ) {
base = 2;
s += 2;
}
}
}
s_end = s;
long_value = strtol(s, &s_end, base);
if( (s != s_end) && (*s_end == 0) ) {
*value = (uint16_t)long_value;
return HACKRF_SUCCESS;
} else {
return HACKRF_ERROR_INVALID_PARAM;
}
}
int dump_register(hackrf_device* device, const uint16_t register_number) {
uint16_t register_value;
int result = hackrf_rffc5071_read(device, (uint8_t)register_number, &register_value);
if( result == HACKRF_SUCCESS ) {
printf("[%2d] -> 0x%03x\n", register_number, register_value);
} else {
printf("hackrf_rffc5071_read() failed: %s (%d)\n", hackrf_error_name(result), result);
}
return result;
}
int dump_registers(hackrf_device* device) {
uint16_t register_number;
int result = HACKRF_SUCCESS;
for(register_number=0; register_number<31; register_number++) {
result = dump_register(device, register_number);
if( result != HACKRF_SUCCESS ) {
break;
}
}
return result;
}
int write_register(
hackrf_device* device,
const uint16_t register_number,
const uint16_t register_value
) {
int result = HACKRF_SUCCESS;
result = hackrf_rffc5071_write(device, (uint8_t)register_number, register_value);
if( result == HACKRF_SUCCESS ) {
printf("0x%03x -> [%2d]\n", register_value, register_number);
} else {
printf("hackrf_rffc5071_write() failed: %s (%d)\n", hackrf_error_name(result), result);
}
return result;
}
#define REGISTER_INVALID 32767
int main(int argc, char** argv) {
int opt;
uint16_t register_number = REGISTER_INVALID;
uint16_t register_value;
hackrf_device* device = NULL;
int option_index = 0;
int result = hackrf_init();
if( result ) {
printf("hackrf_init() failed: %s (%d)\n", hackrf_error_name(result), result);
return -1;
}
result = hackrf_open(&device);
if( result ) {
printf("hackrf_open() failed: %s (%d)\n", hackrf_error_name(result), result);
return -1;
}
while( (opt = getopt_long(argc, argv, "n:rw:", long_options, &option_index)) != EOF ) {
switch( opt ) {
case 'n':
result = parse_int(optarg, &register_number);
break;
case 'w':
result = parse_int(optarg, &register_value);
if( result == HACKRF_SUCCESS ) {
result = write_register(device, register_number, register_value);
}
break;
case 'r':
if( register_number == REGISTER_INVALID ) {
result = dump_registers(device);
} else {
result = dump_register(device, register_number);
}
break;
default:
usage();
}
if( result != HACKRF_SUCCESS ) {
printf("argument error: %s (%d)\n", hackrf_error_name(result), result);
usage();
break;
}
}
result = hackrf_close(device);
if( result ) {
printf("hackrf_close() failed: %s (%d)\n", hackrf_error_name(result), result);
return -1;
}
hackrf_exit();
return 0;
}

248
SoftwareDefined/HackRF/hackrf-2015.07.2/host/hackrf-tools/src/hackrf_si5351c.c
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@ -1,248 +0,0 @@
/*
* Copyright 2012 Jared Boone <jared@sharebrained.com>
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <hackrf.h>
#include <stdio.h>
#include <stdlib.h>
#include <getopt.h>
static void usage() {
printf("\nUsage:\n");
printf("\t-c, --config: print textual configuration information\n");
printf("\t-n, --register <n>: set register number for subsequent read/write operations\n");
printf("\t-r, --read: read register specified by last -n argument, or all registers\n");
printf("\t-w, --write <v>: write register specified by last -n argument with value <v>\n");
printf("\nExamples:\n");
printf("\t<command> -n 12 -r # reads from register 12\n");
printf("\t<command> -r # reads all registers\n");
printf("\t<command> -n 10 -w 22 # writes register 10 with 22 decimal\n");
}
static struct option long_options[] = {
{ "config", no_argument, 0, 'c' },
{ "register", required_argument, 0, 'n' },
{ "write", required_argument, 0, 'w' },
{ "read", no_argument, 0, 'r' },
{ 0, 0, 0, 0 },
};
int parse_int(char* const s, uint16_t* const value) {
char* s_end = s;
const long long_value = strtol(s, &s_end, 10);
if( (s != s_end) && (*s_end == 0) ) {
*value = (uint16_t)long_value;
return HACKRF_SUCCESS;
} else {
return HACKRF_ERROR_INVALID_PARAM;
}
}
int dump_register(hackrf_device* device, const uint16_t register_number) {
uint16_t register_value;
int result = hackrf_si5351c_read(device, register_number, &register_value);
if( result == HACKRF_SUCCESS ) {
printf("[%3d] -> 0x%02x\n", register_number, register_value);
} else {
printf("hackrf_max2837_read() failed: %s (%d)\n", hackrf_error_name(result), result);
}
return result;
}
int dump_registers(hackrf_device* device) {
uint16_t register_number;
int result = HACKRF_SUCCESS;
for(register_number=0; register_number<256; register_number++) {
result = dump_register(device, register_number);
if( result != HACKRF_SUCCESS ) {
break;
}
}
return result;
}
int write_register(
hackrf_device* device,
const uint16_t register_number,
const uint16_t register_value
) {
int result = HACKRF_SUCCESS;
result = hackrf_si5351c_write(device, register_number, register_value);
if( result == HACKRF_SUCCESS ) {
printf("0x%2x -> [%3d]\n", register_value, register_number);
} else {
printf("hackrf_max2837_write() failed: %s (%d)\n", hackrf_error_name(result), result);
}
return result;
}
#define REGISTER_INVALID 32767
int dump_multisynth_config(hackrf_device* device, const uint_fast8_t ms_number) {
uint_fast8_t i;
uint_fast8_t reg_base;
uint16_t parameters[8];
uint32_t p1,p2,p3,r_div;
uint_fast8_t div_lut[] = {1,2,4,8,16,32,64,128};
printf("MS%d:", ms_number);
if(ms_number <6){
reg_base = 42 + (ms_number * 8);
for(i=0; i<8; i++) {
uint_fast8_t reg_number = reg_base + i;
int result = hackrf_si5351c_read(device, reg_number, &parameters[i]);
if( result != HACKRF_SUCCESS ) {
return result;
}
}
p1 =
((parameters[2] & 0x03) << 16)
| (parameters[3] << 8)
| parameters[4]
;
p2 =
((parameters[5] & 0x0F) << 16)
| (parameters[6] << 8)
| parameters[7]
;
p3 =
((parameters[5] & 0xF0) << 12)
| (parameters[0] << 8)
| parameters[1]
;
r_div =
(parameters[2] >> 4) & 0x7
;
printf("\tp1 = %u\n", p1);
printf("\tp2 = %u\n", p2);
printf("\tp3 = %u\n", p3);
if(p3)
printf("\tOutput (800Mhz PLL): %#.10f Mhz\n", ((double)800 / (double)(((double)p1*p3 + p2 + 512*p3)/(double)(128*p3))) / div_lut[r_div] );
} else {
// MS6 and 7 are integer only
unsigned int parms;
reg_base = 90;
for(i=0; i<3; i++) {
uint_fast8_t reg_number = reg_base + i;
int result = hackrf_si5351c_read(device, reg_number, &parameters[i]);
if( result != HACKRF_SUCCESS ) {
return result;
}
}
r_div = (ms_number == 6) ? parameters[2] & 0x7 : (parameters[2] & 0x70) >> 4 ;
parms = (ms_number == 6) ? parameters[0] : parameters[1];
printf("\tp1_int = %u\n", parms);
if(parms)
printf("\tOutput (800Mhz PLL): %#.10f Mhz\n", (800.0f / parms) / div_lut[r_div] );
}
printf("\toutput divider = %u\n", div_lut[r_div]);
return HACKRF_SUCCESS;
}
int dump_configuration(hackrf_device* device) {
uint_fast8_t ms_number;
int result;
for(ms_number=0; ms_number<8; ms_number++) {
result = dump_multisynth_config(device, ms_number);
if( result != HACKRF_SUCCESS ) {
return result;
}
}
return HACKRF_SUCCESS;
}
int main(int argc, char** argv) {
int opt;
uint16_t register_number = REGISTER_INVALID;
uint16_t register_value;
hackrf_device* device = NULL;
int option_index = 0;
int result = hackrf_init();
if( result ) {
printf("hackrf_init() failed: %s (%d)\n", hackrf_error_name(result), result);
return -1;
}
result = hackrf_open(&device);
if( result ) {
printf("hackrf_open() failed: %s (%d)\n", hackrf_error_name(result), result);
return -1;
}
while( (opt = getopt_long(argc, argv, "cn:rw:", long_options, &option_index)) != EOF ) {
switch( opt ) {
case 'n':
result = parse_int(optarg, &register_number);
break;
case 'w':
result = parse_int(optarg, &register_value);
if( result == HACKRF_SUCCESS ) {
result = write_register(device, register_number, register_value);
}
break;
case 'r':
if( register_number == REGISTER_INVALID ) {
result = dump_registers(device);
} else {
result = dump_register(device, register_number);
}
break;
case 'c':
dump_configuration(device);
break;
default:
usage();
}
if( result != HACKRF_SUCCESS ) {
printf("argument error: %s (%d)\n", hackrf_error_name(result), result);
break;
}
}
result = hackrf_close(device);
if( result ) {
printf("hackrf_close() failed: %s (%d)\n", hackrf_error_name(result), result);
return -1;
}
hackrf_exit();
return 0;
}

8
SoftwareDefined/HackRF/hackrf-2015.07.2/host/libhackrf/53-hackrf.rules.in
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@ -1,8 +0,0 @@
# HackRF Jawbreaker
ATTR{idVendor}=="1d50", ATTR{idProduct}=="604b", SYMLINK+="hackrf-jawbreaker-%k", MODE="660", GROUP="@HACKRF_GROUP@"
# HackRF One
ATTR{idVendor}=="1d50", ATTR{idProduct}=="6089", SYMLINK+="hackrf-one-%k", MODE="660", GROUP="@HACKRF_GROUP@"
# HackRF One
ATTR{idVendor}=="1d50", ATTR{idProduct}=="CC15", SYMLINK+="rad1o-%k", MODE="660", GROUP="@HACKRF_GROUP@"
# HackRF DFU
ATTR{idVendor}=="1fc9", ATTR{idProduct}=="000c", SYMLINK+="nxp-dfu-%k", MODE="660", GROUP="@HACKRF_GROUP@"

33
SoftwareDefined/HackRF/hackrf-2015.07.2/host/libhackrf/Readme.md
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@ -1,33 +0,0 @@
This repository contains hardware designs and software for HackRF, a project to
produce a low cost, open source software radio platform.
![Jawbreaker](https://raw.github.com/mossmann/hackrf/master/doc/jawbreaker.jpeg)
How to build host software on Windows:
prerequisite for cygwin or mingw:
* cmake-2.8.10.2 or more see http://www.cmake.org/cmake/resources/software.html
* libusbx-1.0.14 or more see http://sourceforge.net/projects/libusbx/files/latest/download?source=files
* Install Windows driver for HackRF hardware or use Zadig see http://sourceforge.net/projects/libwdi/files/zadig
- If you want to use Zadig select HackRF USB device and just install/replace it with WinUSB driver.
For Cygwin:
cmake -G "Unix Makefiles" -DCMAKE_LEGACY_CYGWIN_WIN32=1 -DLIBUSB_INCLUDE_DIR=/usr/local/include/libusb-1.0/
make
make install
For Mingw:
#normal version
cmake -G "MSYS Makefiles" -DLIBUSB_INCLUDE_DIR=/usr/local/include/libusb-1.0/
#debug version
cmake -G "MSYS Makefiles" -DCMAKE_BUILD_TYPE=Debug -DLIBUSB_INCLUDE_DIR=/usr/local/include/libusb-1.0/
make
make install
How to build host software on Linux:
cmake ./
make
make install
principal author: Michael Ossmann <mike@ossmann.com>
http://greatscottgadgets.com/hackrf/

53
SoftwareDefined/HackRF/hackrf-2015.07.2/host/python/max2837_dump.py
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@ -1,53 +0,0 @@
#!/usr/bin/env python
#
# Copyright 2012 Jared Boone
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
import usb
import struct
import sys
device = usb.core.find(idVendor=0x1d50, idProduct=0x604b)
if device:
print 'Find: HackRF Jawbreaker'
else:
device = usb.core.find(idVendor=0x1d50, idProduct=0x6089)
if device:
print 'Find: HackRF One'
else:
device = usb.core.find(idVendor=0x1d50, idProduct=0xCC15)
if device:
print 'Find: Rad1o'
else:
print 'Not find any HackRF device.'
sys.exit()
device.set_configuration()
def read_max2837_register(register_number):
return struct.unpack('<H', device.ctrl_transfer(0xC0, 3, 0, register_number, 2))[0]
def write_max2837_register(register_number, value):
device.ctrl_transfer(0x40, 2, value, register_number)
def dump_max2837():
for i in range(32):
print('%2d: %03x' % (i, read_max2837_register(i)))
dump_max2837()

54
SoftwareDefined/HackRF/hackrf-2015.07.2/host/python/set_transceiver_mode.py
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@ -1,54 +0,0 @@
#!/usr/bin/env python
#
# Copyright 2012 Jared Boone
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
import sys
import usb
device = usb.core.find(idVendor=0x1d50, idProduct=0x604b)
if device:
print 'Find: HackRF Jawbreaker'
else:
device = usb.core.find(idVendor=0x1d50, idProduct=0x6089)
if device:
print 'Find: HackRF One'
else:
device = usb.core.find(idVendor=0x1d50, idProduct=0xCC15)
if device:
print 'Find: Rad1o'
else:
print 'Not find any HackRF device.'
sys.exit()
device.set_configuration()
def set_rx():
device.ctrl_transfer(0x40, 1, 1, 0)
def set_tx():
device.ctrl_transfer(0x40, 1, 2, 0)
if len(sys.argv) == 2:
if sys.argv[1] == 'tx':
set_tx()
elif sys.argv[1] == 'rx':
set_rx()
else:
print 'Usage: %s [rx|tx]' % sys.argv[0]

0
SoftwareDefined/HackRF/hackrf-2015.07.2/COPYING → SoftwareDefined/HackRF/hackrf-2021.03.1/COPYING
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