Updated HackRF firmware
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SoftwareDefined/HackRF/hackrf-2021.03.1/COPYING
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340
SoftwareDefined/HackRF/hackrf-2021.03.1/COPYING
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GNU GENERAL PUBLIC LICENSE
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Version 2, June 1991
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Copyright (C) 1989, 1991 Free Software Foundation, Inc.
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51 Franklin Street, Boston, MA 02110-1301 USA
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Everyone is permitted to copy and distribute verbatim copies
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Preamble
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The licenses for most software are designed to take away your
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License is intended to guarantee your freedom to share and change free
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GNU GENERAL PUBLIC LICENSE
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TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
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END OF TERMS AND CONDITIONS
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How to Apply These Terms to Your New Programs
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If you develop a new program, and you want it to be of the greatest
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<one line to give the program's name and a brief idea of what it does.>
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Copyright (C) 19yy <name of author>
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Also add information on how to contact you by electronic and paper mail.
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If the program is interactive, make it output a short notice like this
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Gnomovision version 69, Copyright (C) 19yy name of author
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Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
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||||
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||||
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||||
|
||||
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
|
||||
`Gnomovision' (which makes passes at compilers) written by James Hacker.
|
||||
|
||||
<signature of Ty Coon>, 1 April 1989
|
||||
Ty Coon, President of Vice
|
||||
|
||||
This General Public License does not permit incorporating your program into
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||||
proprietary programs. If your program is a subroutine library, you may
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||||
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||||
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||||
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|
||||
226
SoftwareDefined/HackRF/hackrf-2021.03.1/RELEASENOTES
Normal file
226
SoftwareDefined/HackRF/hackrf-2021.03.1/RELEASENOTES
Normal file
@ -0,0 +1,226 @@
|
||||
HackRF 2021.03.1 Release Notes
|
||||
|
||||
To upgrade to this release, you must update libhackrf and hackrf-tools on your
|
||||
host computer. You must also update firmware on your HackRF.
|
||||
|
||||
Major changes in this release include:
|
||||
|
||||
- CPLD bitstreams are now included in and loaded automatically by the firmware.
|
||||
There is no longer a need to update the CPLD separately.
|
||||
|
||||
- The clock output (CLKOUT) is now turned off by default.
|
||||
|
||||
- A new utility, hackrf_clock, provides a way to inspect and modify
|
||||
configuration of hardware clocks, including turning on and off CLKOUT.
|
||||
|
||||
- The rad1o badge is now supported by firmware in this release. Firmware from
|
||||
the HackRF release/repository is different than the original CCCamp firmware
|
||||
and only supports operation as a USB SDR peripheral.
|
||||
|
||||
- When using a HackRF One with a PortaPack in "HackRF Mode" (operating as a USB
|
||||
peripheral), the PortaPack display now indicates operational status and
|
||||
settings.
|
||||
|
||||
There have been many more enhancements and bug fixes. For a full list of
|
||||
changes, see the git log.
|
||||
|
||||
Thanks to Jared Boone, Dominic Spill, schneider, and Mike Walters for major
|
||||
contributions to this release!
|
||||
|
||||
|
||||
==============================
|
||||
HackRF 2018.01.1 Release Notes
|
||||
|
||||
This is a firmware maintenance release that improves reliability of HackRF One
|
||||
when booting from the DFU bootloader. If you do not frequently use DFU boot,
|
||||
there is no reason to upgrade to this release.
|
||||
|
||||
|
||||
==============================
|
||||
HackRF 2017.02.1 Release Notes
|
||||
|
||||
To upgrade to this release, you must update libhackrf and hackrf-tools on your
|
||||
host computer. You must also update firmware on your HackRF. It is important
|
||||
to update both the host code and firmware for this release to work properly.
|
||||
If you only update one or the other, you may experience unpredictable behavior.
|
||||
|
||||
Major changes in this release include:
|
||||
|
||||
- Sweep mode: A new firmware function enables wideband spectrum monitoring by
|
||||
rapidly retuning the radio without requiring individual tuning requests from
|
||||
the host computer. The new hackrf_sweep utility demonstrates this function,
|
||||
allowing you to collect spectrum measurements at a sweep rate of 8 GHz per
|
||||
second. Thanks to Mike Walters, author of inspectrum, for getting this
|
||||
feature working!
|
||||
|
||||
- Hardware synchronization: It is now possible to wire the expansion headers of
|
||||
two or more HackRF Ones together so that they start sampling at the same
|
||||
time. This is advantageous during phase coherent operation with clock
|
||||
synchronized HackRFs. See the -H option of hackrf_transfer. Thank you, Mike
|
||||
Davis!
|
||||
|
||||
- A new utility, hackrf_debug, replaces three older debug utilities,
|
||||
hackrf_si5351c, hackrf_max2837, and hackrf_rffc5071.
|
||||
|
||||
- Power consumption has been reduced by turning off some microcontroller
|
||||
features we weren't using.
|
||||
|
||||
There have been many more enhancements and bug fixes. For a full list of
|
||||
changes, see the git log.
|
||||
|
||||
Special thanks to Dominic Spill who has taken over much of the software
|
||||
development effort and has helped with nearly every improvement since the
|
||||
previous release!
|
||||
|
||||
|
||||
==============================
|
||||
HackRF 2015.07.2 Release Notes
|
||||
|
||||
Bonus release! This release contains fixes for CMake configuration bugs that
|
||||
affected installation of 2015.07.1 on some platforms.
|
||||
|
||||
|
||||
==============================
|
||||
HackRF 2015.07.1 Release Notes
|
||||
|
||||
To upgrade to this release, you must update libhackrf and hackrf-tools on your
|
||||
host computer. You must also update firmware on your HackRF. It is important
|
||||
to update both the host code and firmware for this release to work properly.
|
||||
If you only update one or the other, you may experience unpredictable
|
||||
behaviour.
|
||||
|
||||
Major changes in this release include:
|
||||
|
||||
- Multiple HackRF support. Users with more than one HackRF can target a
|
||||
specific device from software using the device serial number. The serial
|
||||
number is easy to find with hackrf_info. Thanks, Hessu!
|
||||
|
||||
- Linux kernel module detaching. A work-around to avoid the unofficial HackRF
|
||||
kernel module in recent kernel versions that has been causing problems for
|
||||
many users.
|
||||
|
||||
- Updating the CPLD is now possible from Windows. There is no CPLD update with
|
||||
this release, but Windows users should now be able to update.
|
||||
|
||||
- Support for rad1o hardware, the badge of CCCamp 2015 based on HackRF One.
|
||||
This package contains host software supporting rad1o; for firmware and other
|
||||
resources, refer to: https://rad1o.badge.events.ccc.de/
|
||||
|
||||
There have been many more enhancements and bug fixes, for a full list of
|
||||
changes, see the git log.
|
||||
|
||||
|
||||
==============================
|
||||
HackRF 2014.08.1 Release Notes
|
||||
|
||||
To upgrade to this release, you must update libhackrf and hackrf-tools on your
|
||||
host computer. You must also update firmware and the CPLD. It is important to
|
||||
update both the firmware and the CPLD for this release to work properly. If
|
||||
you only update one or the other, you may experience an inverted baseband
|
||||
spectrum.
|
||||
|
||||
For a complete list of changes, see the git log. Highlights include:
|
||||
|
||||
- HackRF now uses high side injection when tuning to frequencies below 2150
|
||||
MHz. This significantly reduces images on both RX and TX that resulted from
|
||||
harmonics of the front-end local oscillator. If you ever wondered why you
|
||||
were picking up broadcast FM stations at frequencies well outside the FM
|
||||
broadcast band, they were probably such images.
|
||||
|
||||
- A CLKIN firmware bug was fixed. The bug prevented switching to the external
|
||||
clock source. Switching now works automatically at the start of every TX or
|
||||
RX operation. If a clock signal is detected on CLKIN, that external source
|
||||
is used. If a clock signal is not detected on CLKIN, the internal crystal is
|
||||
used.
|
||||
|
||||
- hackrf_transfer now has a signal source mode that transmits a CW signal.
|
||||
Thanks, dovecho!
|
||||
|
||||
- The optional udev rules file was moved from hackrf-tools to libhackrf.
|
||||
|
||||
|
||||
==============================
|
||||
HackRF 2014.04.1 Release Notes
|
||||
|
||||
To upgrade to this release, you must install updates to the software on your
|
||||
host computer including libhackrf, hackrf-tools, and any other software (e.g.
|
||||
gr-osmosdr) that uses libhackrf. You must also update firmware and the CPLD
|
||||
(which should be updated after firmware and host software is updated).
|
||||
|
||||
For a complete list of changes, see the git log. Highlights include:
|
||||
|
||||
- The sample format has changed from unsigned 8 bit integers to signed 8 bit
|
||||
integers. This affects all HackRF software and changes the file format used
|
||||
by hackrf_transfer. If you need to convert a file from unsigned bytes to
|
||||
signed bytes, I recommend sox:
|
||||
|
||||
$ sox old.ub new.sb
|
||||
|
||||
- HackRF One is now supported and is the default target platform when compiling
|
||||
firmware. To compile firmware for Jawbreaker, set the BOARD variable:
|
||||
|
||||
$ make -e BOARD=JAWBREAKER
|
||||
|
||||
- HackRF One hardware design and documentation are complete. It is now the
|
||||
preferred platform.
|
||||
|
||||
- Automatic clock synchronization is enabled in the firmware. To activate
|
||||
clock synchronization, simply connect an SMA cable from CLKOUT on one HackRF
|
||||
One to CLKIN on another HackRF One. The clock signal is a 10 MHz square wave
|
||||
at 3.3 V DC. This also works on Jawbreaker but requires the installation of
|
||||
SMA connectors and a few other components noted in the schematic diagram.
|
||||
|
||||
- The automatic tuning algorithm is improved for frequencies above 2150 MHz.
|
||||
The algorithm (in firmware) automatically avoids spurs caused by harmonic
|
||||
relationships between oscillator frequencies in the analog RF section.
|
||||
Similar improvements below 2150 MHz will require further effort.
|
||||
|
||||
- An explicit tuning option is now available to select tuning parameters
|
||||
different from those chosen by the automatic tuning algorithm. Automatic
|
||||
tuning should be preferred for most use cases, but advanced users can use
|
||||
explicit tuning when there is a need, for example, to avoid a particular
|
||||
local oscillator frequency for a specific application. Explicit tuning is
|
||||
implemented only in hackrf_transfer so far.
|
||||
|
||||
- Antenna port power on HackRF One can be enabled or disabled during RX or TX.
|
||||
This is implemented in hackrf_transfer. When activated, 3.0 to 3.3 V DC is
|
||||
supplied to the antenna port. This can safely supply up to 50 mA, enabling
|
||||
equipment including some active antennas.
|
||||
|
||||
- The firmware compilation and installation instructions have changed. See
|
||||
firmware/README and firmware/cpld/README for details.
|
||||
|
||||
Known bug: CPLD update does not work on Windows. See:
|
||||
https://github.com/mossmann/hackrf/issues/113
|
||||
|
||||
Many thanks to Ben Gamari and Jared Boone for their considerable efforts to
|
||||
improve the firmware in this release!
|
||||
|
||||
|
||||
==============================
|
||||
HackRF 2013.07.1 Release Notes
|
||||
|
||||
A firmware update is required to take advantage of features of this release and
|
||||
for compatibility with future software based on this release.
|
||||
|
||||
For a complete list of changes, see the git log. Highlights include:
|
||||
|
||||
- DC offset correction (greatly reducing the spike seen in the center of an FFT
|
||||
display)
|
||||
- Intermediate Frequency (IF) selection
|
||||
|
||||
|
||||
==============================
|
||||
HackRF 2013.06.1 Release Notes
|
||||
|
||||
This is the first release of the HackRF project.
|
||||
|
||||
This release package is simply a copy of the git repository with the addition
|
||||
of a binary firmware image (in the firmware-bin directory) that may be used
|
||||
to upgrade the firmware on a HackRF Jawbreaker. For instructions, see:
|
||||
|
||||
https://github.com/mossmann/hackrf/wiki/Updating-Firmware
|
||||
|
||||
The git repository is located at:
|
||||
|
||||
https://github.com/mossmann/hackrf
|
||||
10
SoftwareDefined/HackRF/hackrf-2021.03.1/Readme.md
Normal file
10
SoftwareDefined/HackRF/hackrf-2021.03.1/Readme.md
Normal file
@ -0,0 +1,10 @@
|
||||
This repository contains hardware designs and software for HackRF,
|
||||
a low cost, open source Software Defined Radio platform.
|
||||
|
||||
|
||||
|
||||
(photo by fd0 from https://github.com/fd0/hackrf-one-pictures)
|
||||
|
||||
principal author: Michael Ossmann <mike@ossmann.com>
|
||||
|
||||
http://greatscottgadgets.com/hackrf/
|
||||
3
SoftwareDefined/HackRF/hackrf-2021.03.1/TRADEMARK
Normal file
3
SoftwareDefined/HackRF/hackrf-2021.03.1/TRADEMARK
Normal file
@ -0,0 +1,3 @@
|
||||
"HackRF" is a trademark of Great Scott Gadgets. Permission to use the trademark
|
||||
with attribution to Great Scott Gadgets is granted to all licensees of HackRF for
|
||||
the sole purpose of naming or describing copies or derived works. (See COPYING.)
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 679 KiB |
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
7
SoftwareDefined/HackRF/hackrf-2021.03.1/doc/Readme.md
Normal file
7
SoftwareDefined/HackRF/hackrf-2021.03.1/doc/Readme.md
Normal file
@ -0,0 +1,7 @@
|
||||
The primary source of documentation is the wiki on github:
|
||||
|
||||
https://github.com/mossmann/hackrf/wiki
|
||||
|
||||
This directory contains supplemental documentation.
|
||||
|
||||
(photo jawbreaker-fd0-145436.jpeg by fd0 from https://github.com/fd0/jawbreaker-pictures)
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,127 @@
|
||||
|
||||
OLS version used from: git://github.com/jawi/ols.git
|
||||
Warning sometimes there's a bug between Mode3 & Mode0 in OLS 0.9.6b3
|
||||
Expected is when /CS = 0 at first SCK Rising Edge data shall be read.
|
||||
|
||||
1) Read JDEC ID:
|
||||
----------------
|
||||
SPI Standard, Mode3, 8bits, MSB first, Show /CS & Honour /CS, SCK=About 32MHz:
|
||||
Send(MOSI)=0x9F(Read JDEC ID)
|
||||
Receive(MISO)=0xEF => Manufacturer ID(Winbond) and 0x40, 0x14 => Device ID
|
||||
|
||||
2) Read Status Register-2:
|
||||
--------------------------
|
||||
SPI Standard, Mode3, 8bits, MSB first, Show /CS & Honour /CS, SCK=About 32MHz:
|
||||
Send(MOSI)=0x35(Read Status Register-2)
|
||||
Receive(MISO)=0x02 (Status Register-2 => S15-S8)
|
||||
|
||||
3) Read Unknown Command 0xA3 (maybe for other SPIFI memory ??):
|
||||
---------------------------------------------------------------
|
||||
SPI Standard, Mode3, 8bits, MSB first, Show /CS & Honour /CS, SCK=About 32MHz:
|
||||
Send(MOSI)=0xA3
|
||||
Receive(MISO)=0x00 0x00 0x00
|
||||
|
||||
4) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
|
||||
--------------------------------------------------------
|
||||
SPI Standard, Mode3, 8bits, MSB first, Show /CS & Honour /CS, SCK=About 32MHz:
|
||||
Send(MOSI)=0xEB(Fast Read Quad I/O)
|
||||
SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS:
|
||||
Send(IO0 to IO3) hexa:
|
||||
00 00 00 (A23-16) (A15-8) (A7-0)
|
||||
A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
|
||||
A5 A5 (Dummy 2 bytes)
|
||||
Receive(IO0 to IO3) hexa:
|
||||
00 00 02 10 B1 01 00 14 (Data) => Vect Table = 0x10020000(Stack Pointer), 0x140001B1(Thumb) Real Addr=0x140001B0 (Reset_Handler/ResetISR)
|
||||
79 01 00 14 7B 01 00 14 (Data)
|
||||
7D 01 00 14 7F 01 00 14 (Data)
|
||||
Dump from Debug (Big Endian to swap 32bits):
|
||||
0x80000000 00000210 B1010014 79010014 7B010014 ....<2E>...y...{...
|
||||
0x80000010 7D010014 7F010014 }.......
|
||||
|
||||
5) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
|
||||
--------------------------------------------------------
|
||||
SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS, SCK=About 32MHz:
|
||||
Send(IO0 to IO3) hexa:
|
||||
00 01 B0 (A23-16) (A15-8) (A7-0) (Corresponds to Real Addr=0x140001B0 (Reset_Handler/ResetISR))
|
||||
A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
|
||||
A5 A5 (Dummy 2 bytes)
|
||||
Receive(IO0 to IO3) hexa:
|
||||
10 B5 72 B6 19 4B 1A 4A (Data)
|
||||
1A 60 1A 4A 5A 60 1A 4A (Data)
|
||||
4F F0 FF 33 13 60 53 60 (Data)
|
||||
Dump from Debug (Big Endian to swap 32bits):
|
||||
0x800001B0 10B572B6 194B1A4A 1A601A4A 5A601A4A .<2E>r<EFBFBD>.K.J.`.JZ`.J
|
||||
0x800001C0 4FF0FF33 13605360 O<><4F>3.`S`
|
||||
|
||||
6) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
|
||||
--------------------------------------------------------
|
||||
SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS:
|
||||
Send(IO0 to IO3) hexa:
|
||||
00 02 18 (A23-16) (A15-8) (A7-0)
|
||||
A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
|
||||
A5 A5 (Dummy 2 bytes)
|
||||
Receive(IO0 to IO3) hexa:
|
||||
FE E7 00 BF 00 31 05 40 (Data)
|
||||
00 00 DF 10 FF F7 DF 01 (Data)
|
||||
80 E2 00 E0 14 01 00 14 (Data)
|
||||
Dump from Debug (Big Endian to swap 32bits):
|
||||
0x80000218 FEE700BF 00310540 0000DF10 FFF7DF01 <20><>.<2E>.1.@..<2E>.<2E><><EFBFBD>.
|
||||
0x80000228 80E200E0 14010014 .<2E>.<2E>....
|
||||
|
||||
7) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
|
||||
--------------------------------------------------------
|
||||
SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS:
|
||||
Send(IO0 to IO3) hexa:
|
||||
00 01 C8 (A23-16) (A15-8) (A7-0)
|
||||
A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
|
||||
A5 A5 (Dummy 2 bytes)
|
||||
Receive(IO0 to IO3) hexa:
|
||||
93 60 D3 60 13 61 53 61 (Data)
|
||||
93 61 D3 61 62 B6 15 4C (Data)
|
||||
Dump from Debug (Big Endian to swap 32bits):
|
||||
0x800001C8 9360D360 13615361 9361D361 62B6154C .`<60>`.aSa.a<>ab<61>.L
|
||||
|
||||
8) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
|
||||
--------------------------------------------------------
|
||||
SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS:
|
||||
Send(IO0 to IO3) hexa:
|
||||
00 02 30 (A23-16) (A15-8) (A7-0)
|
||||
A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
|
||||
A5 A5 (Dummy 2 bytes)
|
||||
Receive(IO0 to IO3) hexa:
|
||||
50 01 00 14 78 01 00 14 (Data)
|
||||
Dump from Debug (Big Endian to swap 32bits):
|
||||
0x80000230 50010014 78010014 P...x...
|
||||
|
||||
9) Fast Read Quad I/O with "Continuous Read Mode"(0xEB):
|
||||
--------------------------------------------------------
|
||||
SPI Quad, Mode3, 8bits, MSB first, Show /CS & Honour /CS:
|
||||
Send(IO0 to IO3) hexa:
|
||||
00 01 D8 (A23-16) (A15-8) (A7-0)
|
||||
A5 (M7-0) => A5 = 1010 0101 (Continuous Read Mode enabled)
|
||||
A5 A5 (Dummy 2 bytes)
|
||||
Receive(IO0 to IO3) hexa:
|
||||
05 E0 20 68 61 68 A2 68 (Data)
|
||||
0C 34 FF F7 D2 FF 12 4B (Data
|
||||
9C 42 F6 D3 04 E0 20 68 (Data)
|
||||
61 68 08 34 FF F7 D2 FF (Data)
|
||||
0E 4B 9C 42 F7 D3 DF F8 (Data)
|
||||
Dump from Debug (Big Endian to swap 32bits):
|
||||
0x800001D8 05E02068 6168A268 0C34FFF7 D2FF124B .<2E> hah<61>h.4<EFBFBD><EFBFBD><EFBFBD><EFBFBD>.K
|
||||
0x800001E8 9C42F6D3 04E02068 61680834 FFF7D2FF .B<><42>.<2E> hah.4<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
0x800001F8 0E4B9C42 F7D3DFF8 .K.B<><42><EFBFBD><EFBFBD>
|
||||
|
||||
Nota:
|
||||
Tested on JellyBean.
|
||||
SCK is about 32MHz After about 620us from startup.
|
||||
SCK change to about 660KHz/700KHz during about 400us. (During Read from 00 0C 78 => During CGU SetPLL1 code).
|
||||
SCK change from 4MHz to about 8MHz during about 15us. (Read from 00 0D 98 => During CGU SetPLL1 code).
|
||||
SCK stabilize to 8MHz during 122us (no data anymore OLS memory is full) (Read from 00 05 B0).
|
||||
|
||||
...
|
||||
During Code running the SCK run at 8MHz MCU is configured at 72MHz => 12MHz(IRC)*6.
|
||||
SPIFI CLK(0x40050070) = 0xD000800 0x0D=IDIVB & 0x800=AUTOBLOCK_CLOCK_BIT Enabled
|
||||
IDIVB_CTRL(0x4005004C) = 0x9000820 => IDIB=1000(8+1)=9 => for 72MHz Core => 72/9=8MHz
|
||||
IDIVB_CTRL(0x4005004C) = 0x9000800 => IDIB=0000(0+1)=1 => for 72MHz Core => 72/1=72MHz => This configuration just crash.
|
||||
IDIVB_CTRL(0x4005004C) = 0x9000800 => IDIB=0000(0+1)=1 => for 72MHz Core => 72/2=36MHz => This configuration works fine.
|
||||
|
||||
Binary file not shown.
@ -0,0 +1,67 @@
|
||||
Item,Qty,Reference(s),Value,LibPart,Footprint,Datasheet,Description,Manufacturer,Note,Note:,Part Number
|
||||
1,26,"C1, C3, C5, C7, C11, C24, C29, C33, C34, C35, C36, C37, C38, C39, C40, C45, C47, C55, C57, C60, C63, C65, C66, C67, C115, C125",33pF,Device:C,hackrf:GSG-0402,,CAP CER 33PF 50V 5% NP0 0402,Murata,,,GRM1555C1H330JA01D
|
||||
2,17,"C2, C4, C6, C10, C16, C19, C22, C30, C54, C56, C87, C88, C89, C92, C93, C162, C163",10nF,Device:C,hackrf:GSG-0402,,CAP CER 10000PF 16V 10% X7R 0402,Murata,,,GRM155R71C103KA01D
|
||||
3,3,"C97, C98, C100",330nF,Device:C,hackrf:GSG-0402,,CAP CER 0.33UF 10V 10% X5R 0402,Murata,,,GRM155R61A334KE15D
|
||||
4,12,"C8, C21, C32, C43, C48, C51, C84, C85, C86, C94, C99, C102",22pF,Device:C,hackrf:GSG-0402,,CAP CER 22PF 50V 5% NP0 0402,Murata,,,GRM1555C1H220JA01D
|
||||
5,2,"C104, C111",3pF,Device:C,hackrf:GSG-0402,,CAP CER 3PF 50V NP0 0402,Murata,,,GRM1555C1H3R0CA01D
|
||||
6,6,"C105, C126, C127, C143, C145, C146",10uF,Device:C,hackrf:GSG-0805,,CAP CER 10UF 10V 10% X5R 0805,Murata,,,GRM21BR61A106KE19L
|
||||
7,4,"C53, C106, C161, C171",1uF,Device:C,hackrf:GSG-0402,,CAP CER 1UF 10V 10% X5R 0402,Taiyo Yuden,,,LMK105BJ105KV-F
|
||||
8,2,"C15, C112",180pF,Device:C,hackrf:GSG-0402,,CAP CER 180PF 50V 5% NP0 0402,Murata,,,GRM1555C1H181JA01D
|
||||
9,57,"C9, C17, C18, C20, C23, C25, C28, C31, C44, C46, C49, C50, C58, C59, C61, C62, C64, C71, C73, C75, C77, C79, C81, C83, C91, C113, C119, C120, C121, C122, C123, C128, C129, C130, C131, C132, C133, C134, C135, C136, C137, C138, C139, C140, C141, C142, C144, C147, C148, C149, C150, C151, C152, C153, C154, C166, C167",100nF,Device:C,hackrf:GSG-0402,,CAP CER 0.1UF 10V 10% X5R 0402,Murata,,,GRM155R61A104KA01D
|
||||
10,1,C114,3.3nF,Device:C,hackrf:GSG-0402,,CAP CER 3300PF 50V 10% X7R 0402,Murata,,,GRM155R71H332KA01D
|
||||
11,3,"C26, C27, C116",47pF,Device:C,hackrf:GSG-0402,,CAP CER 47PF 50V 5% NP0 0402,Murata,,,GRM1555C1H470JA01D
|
||||
12,4,"C118, C157, C158, C164",18pF,Device:C,hackrf:GSG-0402,,CAP CER 18PF 50V 5% NP0 0402,Murata,,,GRM1555C1H180JA01D
|
||||
13,2,"C12, C13",330pF,Device:C,hackrf:GSG-0402,,CAP CER 330PF 50V 10% X7R 0402,Murata,,,GRM155R71H331KA01D
|
||||
14,7,"C72, C74, C76, C78, C80, C82, C124",2.2uF,Device:C,hackrf:GSG-0402,,CAP CER 2.2UF 10V 20% X5R 0402,Taiyo Yuden,,,LMK105BJ225MV-F
|
||||
15,1,C14,8p2,Device:C,hackrf:GSG-0402,,CAP CER 8.2PF 50V NP0 0402,Taiyo Yuden,,,UMK105CG8R2DV-F
|
||||
16,6,"C41, C42, C52, C70, C90, C160",100pF,Device:C,hackrf:GSG-0402,,CAP CER 100PF 50V 5% NP0 0402,Murata,,,GRM1555C1H101JA01D
|
||||
17,2,"C169, C170",1.8pF,Device:C,hackrf:GSG-0402,,CAP CER 1.8PF 25V C0G/NP0 0402,Murata,,,GRM1555C1E1R8BA01D
|
||||
18,3,"D1, D3, D9",GSG-DIODE-TVS-BI,hackrf:GSG-DIODE-TVS-BI,hackrf:GSG-0402,,TVS DIODE ESD .05PF 15KV 0402,Murata,,,LXES15AAA1-100
|
||||
19,2,"D2, D6",TXLED,Device:LED,gsg-modules:LTST-S220,,LED SUPR RED CLR RT ANG 0805,Lite-On,,,LTST-S220KRKT
|
||||
20,2,"D4, D7",VCCLED,Device:LED,gsg-modules:LTST-S220,,LED GREEN CLEAR RT ANG 0805,Lite-On,,,LTST-S220KGKT
|
||||
21,2,"D5, D8",1V8LED,Device:LED,gsg-modules:LTST-S220,,LED YELLOW CLEAR RT ANG 0805,Lite-On,,,LTST-S220KSKT
|
||||
22,3,"FB1, FB2, FB3",FILTER,Device:Ferrite_Bead_Small,hackrf:GSG-0805,,FERRITE CHIP 220 OHM 2000MA 0805,Murata,,,BLM21PG221SN1D
|
||||
23,1,J1,USB-MICRO-B,hackrf:GSG-USB-MICRO-B-SHIELDED,hackrf:GSG-USB-MICROB-FCI-10103592-EXT,,CONN RCPT REV MICRO USB TYPE B,FCI,,,10103592-0001LF
|
||||
24,2,"L10, L11",4u7,Device:L,hackrf:GSG-NRG4026,,INDUCTOR 4.7UH 1.6A 20% SMD,Taiyo Yuden,,,NRG4026T4R7M
|
||||
25,5,"L2, L3, L5, L12, L13",10uH,Device:L,hackrf:GSG-0603,,INDUCTR 10UH 220MA 20% 0603 SMD,Taiyo Yuden,,,BRL1608T100M
|
||||
26,1,L7,6.2nH,Device:L,hackrf:GSG-0402,,INDUCTOR HIFREQ 6.2+/-0.3NH 0402,Taiyo Yuden,,,HK10056N2S-T
|
||||
27,3,"P2, P4, P16",ANTENNA,hackrf:GSG-RF-CONN,hackrf:GSG-SMA-73251-2120,,CONN SMA JACK 50 OHM EDGE MNT W/JAM NUT & LOCK WASHER,Molex,,,73251-2121
|
||||
28,2,"P20, P28",SD,Connector_Generic:Conn_02x11_Odd_Even,hackrf:GSG-HEADER-2x11,,"CONN HEADER FMAL 22PS.1"" DL GOLD",Sullins,,,PPPC112LFBN-RC
|
||||
29,1,P22,I2S,Connector_Generic:Conn_02x13_Odd_Even,hackrf:GSG-HEADER-2x13,,"CONN HEADER FMAL 26PS.1"" DL GOLD",Sullins,,,PPPC132LFBN-RC
|
||||
30,1,P9,BASEBAND,Connector_Generic:Conn_02x08_Odd_Even,hackrf:GSG-HEADER-2x8,,"CONN HEADER FMAL 16PS.1"" DL GOLD",Sullins,,,PPPC082LFBN-RC
|
||||
31,3,"Q1, Q2, Q4",MOSFET_P,Device:Q_PMOS_GSD,gsg-modules:SOT23-3,,MOSFET P-CH 50V 130MA SOT-23,Fairchild,,,BSS84
|
||||
32,1,Q3,MOSFET_P,Device:Q_PMOS_GSD,gsg-modules:SOT23-3,,MOSFET P-CH 20V 4.2A SOT-23,Diodes Inc.,,,DMP2305U-7
|
||||
33,1,Q5,MOSFET_P,Device:Q_PMOS_GSD,gsg-modules:SOT23-3,,MOSFET P-CH -30V -4.3A SOT23,Alpha and Omega,,,AO3407A
|
||||
34,6,"R1, R2, R25, R26, R72, R75",470,Device:R,hackrf:GSG-0402,,RES TF 1/16W 470 OHM 5% 0402,Stackpole,,,RMCF0402JT470R
|
||||
35,6,"R8, R9, R10, R13, R73, R76",1k,Device:R,hackrf:GSG-0402,,RES 1K OHM 1/16W 1% 0402,Stackpole,,,RMCF0402FT1K00
|
||||
36,22,"R19, R30, R31, R32, R33, R34, R77, R78, R79, R80, R81, R86, R87, R88, R89, R90, R91, R94, R96, R98, R99, R100",39,Device:R,hackrf:GSG-0402,,RES 39 OHM 1/16W 5% 0402 SMD,Stackpole,,,RMCF0402JT39R0
|
||||
37,26,"R5, R6, R7, R11, R12, R24, R29, R36, R37, R41, R48, R49, R51, R52, R54, R59, R63, R64, R65, R66, R67, R68, R85, R93, R104, R105",10k,Device:R,hackrf:GSG-0402,,RES 10K OHM 1/16W 5% 0402 SMD,Stackpole,,,RMCF0402JT10K0
|
||||
38,4,"R14, R15, R16, R17",4k7,Device:R,hackrf:GSG-0402,,RES 4.7K OHM 1/16W 1% 0402,Stackpole,,,RMCF0402FT4K70
|
||||
39,4,"R18, R27, R28, R74",1k8,Device:R,hackrf:GSG-0402,,RES TF 1.8K OHM 5% 1/16W 0402,Stackpole,,,RMCF0402JT1K80
|
||||
40,7,"R20, R21, R22, R23, R57, R58, R62",0,Device:R,hackrf:GSG-0402,,RES 0.0 OHM 1/16W 0402 SMD,Stackpole,,,RMCF0402ZT0R00
|
||||
41,1,R3,22k,Device:R,hackrf:GSG-0402,,RES 22K OHM 1/10W 5% 0402 SMD,Panasonic,,,ERJ-2GEJ223X
|
||||
42,1,R4,51k,Device:R,hackrf:GSG-0402,,RES TF 51K OHM 1% 0.0625W 0402,Stackpole,,,RMCF0402FT51K0
|
||||
43,2,"R46, R55",162k,Device:R,hackrf:GSG-0402,,RES TF 1/16W 162K OHM 1% 0402,Stackpole,,,RMCF0402FT162K
|
||||
44,1,R47,330k,Device:R,hackrf:GSG-0402,,RES TF 1/16W 330K OHM 1% 0402,Stackpole,,,RMCF0402FT330K
|
||||
45,1,R56,715k,Device:R,hackrf:GSG-0402,,RES TF 1/16W 715K OHM 1% 0402,Stackpole,,,RMCF0402FT715K
|
||||
46,1,R69,12k,Device:R,hackrf:GSG-0402,,RES 12.0K OHM 1/16W 1% 0402 SMD,Rohm,,,MCR01MRTF1202
|
||||
47,2,"SW1, SW2",RESET,hackrf:SW_PUSH_SHIELDED,hackrf:GSG-SWITCH-FSMRA,,SWITCH TACTILE SPST-NO 0.05A 12V,TE Connectivity,,,FSMRA3JH
|
||||
48,2,"T1, T2",MIX_OUT_BALUN,hackrf:BALUN-B0310J50100AHF,hackrf:GSG-B0310J50100AHF,,Ultra Low Profile 0805 Balun 50 to 100 ohm Balanced,Anaren,,,B0310J50100AHF
|
||||
49,2,"T3, T4",TX_BALUN,hackrf:BALUN,hackrf:GSG-2500BL14M100,,BALUN CERAMIC CHIP WIMAX 2.5GHZ,Johanson Technology,Alternative part: Murata LDB182G4510G-120,Alternative part: Murata LDB182G4510G-120,2500BL14M100T
|
||||
50,7,"U1, U2, U5, U6, U7, U10, U11",SKY13453,gsg-symbols:SKY13453,gsg-modules:SKY13350-385LF,,IC RF SWITCH 6GHZ 6QFN,Skyworks,,,SKY13453-385LF
|
||||
51,3,"U9, U12, U14",SKY13317,hackrf:SKY13317,hackrf:GSG-SKY13317-373LF,,20 MHz-6.0 GHz pHEMT GaAs SP3T Switch,Skyworks,,,SKY13317-373LF
|
||||
52,2,"U13, U25",MGA-81563,hackrf:MGA-81563,hackrf:GSG-SOT363,,"0.1-6 GHz 3 V, 14 dBm Amplifier",Avago,,,MGA-81563-TR1G
|
||||
53,1,U15,TVS,hackrf:LXES1TBCC2-004,hackrf:GSG-LXES1TBCC2-004,~,TVS DIODE 5.5V 22V LLP75-6L,Vishay,,,VBUS54CV-HSF-G4-08
|
||||
54,1,U17,MAX2837,hackrf:MAX2837,hackrf:GSG-QFN48-6,,IC TXRX 2.3GHZ-2.7GHZ 48TQFN,Maxim,,,MAX2837ETM+
|
||||
55,1,U18,MAX5864,hackrf:MAX5864,hackrf:GSG-QFN48-7,,IC ANLG FRONT END 22MSPS 48-TQFN,Maxim,,,MAX5864ETM+
|
||||
56,1,U19,SI5351C,hackrf:SI5351C,hackrf:GSG-QFN20-4,,IC CLK GENERATOR 160MHZ 20QFN,Silicon Laboratories Inc,,,SI5351C-B-GM
|
||||
57,1,U20,W25Q80,hackrf:W25Q80BV,hackrf:GSG-SOIC8-208,,IC FLASH 8MBIT 8SOIC,Winbond,,,W25Q80DVSSIG
|
||||
58,1,U21,TPS62410,hackrf:TPS62410,hackrf:GSG-S-PVSON-N10,,IC BUCK SYNC DUAL ADJ 0.8A 10SON,Texas Instruments,,,TPS62410DRCR
|
||||
59,1,U23,LPC4320FBD144,hackrf:LPC43XXFBD144,hackrf:GSG-LQFP144,,IC MCU 32BIT 144LQFP,NXP,,,"LPC4320FBD144,551"
|
||||
60,1,U24,GSG-XC2C64A-7VQG100C,hackrf:GSG-XC2C64A-7VQG100C,hackrf:GSG-VQ100,,IC CR-II CPLD 64MCELL 100-VQFP,Xilinx,,,XC2C64A-7VQG100C
|
||||
61,1,U3,RX_LOWPASS_FILTER,hackrf:FIL-LP0603,hackrf:GSG-LP0603,,FILTER LOW PASS 1880MHZ 0603 SMD,AVX,,,LP0603A1880ANTR
|
||||
62,1,U4,RFFC5072,hackrf:RFFC5072,hackrf:GSG-QFN32,,WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6GHz MIXER,RFMD,,,RFFC5072TR7
|
||||
63,1,U8,RX_HIGHPASS_FILTER,hackrf:FIL-DEA,hackrf:GSG-HP-DEA,,FILTER HIGHPASS WLAN&BLUETOOTH,TDK,,,DEA162400HT-8004B1
|
||||
64,1,X1,GSG-XTAL4PIN,hackrf:GSG-XTAL4PIN,hackrf:GSG-XTAL3.2x2.5mm,,CRYSTAL 25.0000MHZ 10PF SMD,Abracon,,,ABM8-25.000MHZ-10-D1G-T
|
||||
65,1,X2,MCU_XTAL,hackrf:GSG-XTAL4PIN,hackrf:GSG-XTAL3.2x2.5mm,,CRYSTAL 12.000 MHZ 12PF SMD,TXC,,,7V-12.000MAAE-T
|
||||
66,1,X3,RTC_XTAL,Device:Crystal,hackrf:GSG-XTAL-AB26TRQ,,CRYSTAL 32.768KHZ 12.5PF SMD,Abracon,,,AB26TRQ-32.768KHZ-T
|
||||
|
@ -0,0 +1,48 @@
|
||||
Copyright 2012, 2013, 2014 Michael Ossmann
|
||||
|
||||
These files are part of HackRF.
|
||||
|
||||
This is a free hardware design; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This design is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this design; see the file COPYING. If not, write to
|
||||
the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
Boston, MA 02110-1301, USA.
|
||||
|
||||
|
||||
HackRF One is a wideband software radio transceiver with a USB interface.
|
||||
|
||||
hardware notes:
|
||||
|
||||
Schematic and layout files were designed in KiCad, an open source electronic
|
||||
design automation package.
|
||||
|
||||
order of copper layers:
|
||||
Copper 1: C1F (front)
|
||||
Copper 2: C2
|
||||
Copper 3: C3
|
||||
Copper 4: C4B (back)
|
||||
|
||||
PCB description: 4 layer PCB 0.062 in
|
||||
Copper 1 0.5 oz foil plated to approximately 0.0017 in
|
||||
Dielectric 1-2 0.0119 in
|
||||
Copper 2 1 oz foil (0.0014 in)
|
||||
Dielectric 2-3 0.0280 in
|
||||
Copper 3 1 oz foil (0.0014 in)
|
||||
Dielectric 3-4 0.0119 in
|
||||
Copper 4 0.5 oz foil plated to approximately 0.0017 in
|
||||
|
||||
FR4 or similar substrate with Er=4.5 (+/- 0.1)
|
||||
required impedance: 50 ohm (+/- 5%) 20 mil microstrip impedance
|
||||
double side solder mask green
|
||||
single side silkscreen white
|
||||
6 mil min trace width and
|
||||
6 mil min isolation
|
||||
@ -0,0 +1,829 @@
|
||||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.1.9*
|
||||
G04 #@! TF.CreationDate,2021-03-19T18:57:38-06:00*
|
||||
G04 #@! TF.ProjectId,hackrf-one,6861636b-7266-42d6-9f6e-652e6b696361,r6*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Soldermask,Bot*
|
||||
G04 #@! TF.FilePolarity,Negative*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW 5.1.9) date 2021-03-19 18:57:38*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G01*
|
||||
G04 APERTURE LIST*
|
||||
%ADD10C,1.676400*%
|
||||
%ADD11C,0.742240*%
|
||||
%ADD12C,2.000000*%
|
||||
%ADD13C,1.652400*%
|
||||
%ADD14C,1.552400*%
|
||||
%ADD15C,5.752400*%
|
||||
%ADD16C,0.752400*%
|
||||
%ADD17C,1.219200*%
|
||||
%ADD18C,2.152400*%
|
||||
%ADD19C,0.737400*%
|
||||
%ADD20C,0.736600*%
|
||||
%ADD21C,0.777240*%
|
||||
G04 APERTURE END LIST*
|
||||
G04 #@! TO.C,NT3*
|
||||
G36*
|
||||
G01*
|
||||
X84892000Y-128848200D02*
|
||||
X83368000Y-128848200D01*
|
||||
G75*
|
||||
G02*
|
||||
X83291800Y-128772000I0J76200D01*
|
||||
G01*
|
||||
X83291800Y-127248000D01*
|
||||
G75*
|
||||
G02*
|
||||
X83368000Y-127171800I76200J0D01*
|
||||
G01*
|
||||
X84892000Y-127171800D01*
|
||||
G75*
|
||||
G02*
|
||||
X84968200Y-127248000I0J-76200D01*
|
||||
G01*
|
||||
X84968200Y-128772000D01*
|
||||
G75*
|
||||
G02*
|
||||
X84892000Y-128848200I-76200J0D01*
|
||||
G01*
|
||||
G37*
|
||||
D10*
|
||||
X84130000Y-125470000D03*
|
||||
G04 #@! TD*
|
||||
G04 #@! TO.C,NT2*
|
||||
G36*
|
||||
G01*
|
||||
X156951800Y-113532000D02*
|
||||
X156951800Y-112008000D01*
|
||||
G75*
|
||||
G02*
|
||||
X157028000Y-111931800I76200J0D01*
|
||||
G01*
|
||||
X158552000Y-111931800D01*
|
||||
G75*
|
||||
G02*
|
||||
X158628200Y-112008000I0J-76200D01*
|
||||
G01*
|
||||
X158628200Y-113532000D01*
|
||||
G75*
|
||||
G02*
|
||||
X158552000Y-113608200I-76200J0D01*
|
||||
G01*
|
||||
X157028000Y-113608200D01*
|
||||
G75*
|
||||
G02*
|
||||
X156951800Y-113532000I0J76200D01*
|
||||
G01*
|
||||
G37*
|
||||
X160330000Y-112770000D03*
|
||||
G04 #@! TD*
|
||||
G04 #@! TO.C,NT1*
|
||||
G36*
|
||||
G01*
|
||||
X144251800Y-113532000D02*
|
||||
X144251800Y-112008000D01*
|
||||
G75*
|
||||
G02*
|
||||
X144328000Y-111931800I76200J0D01*
|
||||
G01*
|
||||
X145852000Y-111931800D01*
|
||||
G75*
|
||||
G02*
|
||||
X145928200Y-112008000I0J-76200D01*
|
||||
G01*
|
||||
X145928200Y-113532000D01*
|
||||
G75*
|
||||
G02*
|
||||
X145852000Y-113608200I-76200J0D01*
|
||||
G01*
|
||||
X144328000Y-113608200D01*
|
||||
G75*
|
||||
G02*
|
||||
X144251800Y-113532000I0J76200D01*
|
||||
G01*
|
||||
G37*
|
||||
X147630000Y-112770000D03*
|
||||
G04 #@! TD*
|
||||
D11*
|
||||
G04 #@! TO.C,U19*
|
||||
X127469200Y-162926000D03*
|
||||
X126809200Y-163586000D03*
|
||||
X126809200Y-162266000D03*
|
||||
X128129200Y-162266000D03*
|
||||
X128129200Y-163586000D03*
|
||||
G04 #@! TD*
|
||||
D12*
|
||||
G04 #@! TO.C,MARK1MM*
|
||||
X171000000Y-102000000D03*
|
||||
G04 #@! TD*
|
||||
D13*
|
||||
G04 #@! TO.C,J1*
|
||||
X178800000Y-128125000D03*
|
||||
X178800000Y-119875000D03*
|
||||
D14*
|
||||
X175770000Y-126490000D03*
|
||||
X175770000Y-121510000D03*
|
||||
G04 #@! TD*
|
||||
D15*
|
||||
G04 #@! TO.C,J4*
|
||||
X64000000Y-104000000D03*
|
||||
D16*
|
||||
X64000000Y-101800000D03*
|
||||
X61800000Y-104000000D03*
|
||||
X64000000Y-106200000D03*
|
||||
X66200000Y-104000000D03*
|
||||
X65550000Y-102450000D03*
|
||||
X62450000Y-102450000D03*
|
||||
X62450000Y-105550000D03*
|
||||
X65550000Y-105550000D03*
|
||||
G04 #@! TD*
|
||||
D15*
|
||||
G04 #@! TO.C,J5*
|
||||
X64000000Y-171000000D03*
|
||||
D16*
|
||||
X64000000Y-168800000D03*
|
||||
X61800000Y-171000000D03*
|
||||
X64000000Y-173200000D03*
|
||||
X66200000Y-171000000D03*
|
||||
X65550000Y-169450000D03*
|
||||
X62450000Y-169450000D03*
|
||||
X62450000Y-172550000D03*
|
||||
X65550000Y-172550000D03*
|
||||
G04 #@! TD*
|
||||
D15*
|
||||
G04 #@! TO.C,J6*
|
||||
X176000000Y-171000000D03*
|
||||
D16*
|
||||
X176000000Y-168800000D03*
|
||||
X173800000Y-171000000D03*
|
||||
X176000000Y-173200000D03*
|
||||
X178200000Y-171000000D03*
|
||||
X177550000Y-169450000D03*
|
||||
X174450000Y-169450000D03*
|
||||
X174450000Y-172550000D03*
|
||||
X177550000Y-172550000D03*
|
||||
G04 #@! TD*
|
||||
D15*
|
||||
G04 #@! TO.C,J7*
|
||||
X176000000Y-104000000D03*
|
||||
D16*
|
||||
X176000000Y-101800000D03*
|
||||
X173800000Y-104000000D03*
|
||||
X176000000Y-106200000D03*
|
||||
X178200000Y-104000000D03*
|
||||
X177550000Y-102450000D03*
|
||||
X174450000Y-102450000D03*
|
||||
X174450000Y-105550000D03*
|
||||
X177550000Y-105550000D03*
|
||||
G04 #@! TD*
|
||||
D15*
|
||||
G04 #@! TO.C,J8*
|
||||
X126000000Y-104000000D03*
|
||||
D16*
|
||||
X126000000Y-101800000D03*
|
||||
X123800000Y-104000000D03*
|
||||
X126000000Y-106200000D03*
|
||||
X128200000Y-104000000D03*
|
||||
X127550000Y-102450000D03*
|
||||
X124450000Y-102450000D03*
|
||||
X124450000Y-105550000D03*
|
||||
X127550000Y-105550000D03*
|
||||
G04 #@! TD*
|
||||
D15*
|
||||
G04 #@! TO.C,J9*
|
||||
X131000000Y-144000000D03*
|
||||
D16*
|
||||
X131000000Y-141800000D03*
|
||||
X128800000Y-144000000D03*
|
||||
X131000000Y-146200000D03*
|
||||
X133200000Y-144000000D03*
|
||||
X132550000Y-142450000D03*
|
||||
X129450000Y-142450000D03*
|
||||
X129450000Y-145550000D03*
|
||||
X132550000Y-145550000D03*
|
||||
G04 #@! TD*
|
||||
G04 #@! TO.C,P2*
|
||||
G36*
|
||||
G01*
|
||||
X179056200Y-147160000D02*
|
||||
X179056200Y-149825000D01*
|
||||
G75*
|
||||
G02*
|
||||
X178980000Y-149901200I-76200J0D01*
|
||||
G01*
|
||||
X174790000Y-149901200D01*
|
||||
G75*
|
||||
G02*
|
||||
X174713800Y-149825000I0J76200D01*
|
||||
G01*
|
||||
X174713800Y-147160000D01*
|
||||
G75*
|
||||
G02*
|
||||
X174790000Y-147083800I76200J0D01*
|
||||
G01*
|
||||
X178980000Y-147083800D01*
|
||||
G75*
|
||||
G02*
|
||||
X179056200Y-147160000I0J-76200D01*
|
||||
G01*
|
||||
G37*
|
||||
G36*
|
||||
G01*
|
||||
X179056200Y-140175000D02*
|
||||
X179056200Y-142840000D01*
|
||||
G75*
|
||||
G02*
|
||||
X178980000Y-142916200I-76200J0D01*
|
||||
G01*
|
||||
X174790000Y-142916200D01*
|
||||
G75*
|
||||
G02*
|
||||
X174713800Y-142840000I0J76200D01*
|
||||
G01*
|
||||
X174713800Y-140175000D01*
|
||||
G75*
|
||||
G02*
|
||||
X174790000Y-140098800I76200J0D01*
|
||||
G01*
|
||||
X178980000Y-140098800D01*
|
||||
G75*
|
||||
G02*
|
||||
X179056200Y-140175000I0J-76200D01*
|
||||
G01*
|
||||
G37*
|
||||
G04 #@! TD*
|
||||
G04 #@! TO.C,P3*
|
||||
G36*
|
||||
G01*
|
||||
X144328000Y-117011800D02*
|
||||
X145852000Y-117011800D01*
|
||||
G75*
|
||||
G02*
|
||||
X145928200Y-117088000I0J-76200D01*
|
||||
G01*
|
||||
X145928200Y-118612000D01*
|
||||
G75*
|
||||
G02*
|
||||
X145852000Y-118688200I-76200J0D01*
|
||||
G01*
|
||||
X144328000Y-118688200D01*
|
||||
G75*
|
||||
G02*
|
||||
X144251800Y-118612000I0J76200D01*
|
||||
G01*
|
||||
X144251800Y-117088000D01*
|
||||
G75*
|
||||
G02*
|
||||
X144328000Y-117011800I76200J0D01*
|
||||
G01*
|
||||
G37*
|
||||
D10*
|
||||
X145090000Y-120390000D03*
|
||||
G04 #@! TD*
|
||||
G04 #@! TO.C,P4*
|
||||
G36*
|
||||
G01*
|
||||
X60943800Y-158840000D02*
|
||||
X60943800Y-156175000D01*
|
||||
G75*
|
||||
G02*
|
||||
X61020000Y-156098800I76200J0D01*
|
||||
G01*
|
||||
X65210000Y-156098800D01*
|
||||
G75*
|
||||
G02*
|
||||
X65286200Y-156175000I0J-76200D01*
|
||||
G01*
|
||||
X65286200Y-158840000D01*
|
||||
G75*
|
||||
G02*
|
||||
X65210000Y-158916200I-76200J0D01*
|
||||
G01*
|
||||
X61020000Y-158916200D01*
|
||||
G75*
|
||||
G02*
|
||||
X60943800Y-158840000I0J76200D01*
|
||||
G01*
|
||||
G37*
|
||||
G36*
|
||||
G01*
|
||||
X60943800Y-165825000D02*
|
||||
X60943800Y-163160000D01*
|
||||
G75*
|
||||
G02*
|
||||
X61020000Y-163083800I76200J0D01*
|
||||
G01*
|
||||
X65210000Y-163083800D01*
|
||||
G75*
|
||||
G02*
|
||||
X65286200Y-163160000I0J-76200D01*
|
||||
G01*
|
||||
X65286200Y-165825000D01*
|
||||
G75*
|
||||
G02*
|
||||
X65210000Y-165901200I-76200J0D01*
|
||||
G01*
|
||||
X61020000Y-165901200D01*
|
||||
G75*
|
||||
G02*
|
||||
X60943800Y-165825000I0J76200D01*
|
||||
G01*
|
||||
G37*
|
||||
G04 #@! TD*
|
||||
G04 #@! TO.C,P5*
|
||||
G36*
|
||||
G01*
|
||||
X92588200Y-104388000D02*
|
||||
X92588200Y-105912000D01*
|
||||
G75*
|
||||
G02*
|
||||
X92512000Y-105988200I-76200J0D01*
|
||||
G01*
|
||||
X90988000Y-105988200D01*
|
||||
G75*
|
||||
G02*
|
||||
X90911800Y-105912000I0J76200D01*
|
||||
G01*
|
||||
X90911800Y-104388000D01*
|
||||
G75*
|
||||
G02*
|
||||
X90988000Y-104311800I76200J0D01*
|
||||
G01*
|
||||
X92512000Y-104311800D01*
|
||||
G75*
|
||||
G02*
|
||||
X92588200Y-104388000I0J-76200D01*
|
||||
G01*
|
||||
G37*
|
||||
X91750000Y-107690000D03*
|
||||
X89210000Y-105150000D03*
|
||||
X89210000Y-107690000D03*
|
||||
X86670000Y-105150000D03*
|
||||
X86670000Y-107690000D03*
|
||||
G04 #@! TD*
|
||||
G04 #@! TO.C,P9*
|
||||
G36*
|
||||
G01*
|
||||
X107828200Y-127248000D02*
|
||||
X107828200Y-128772000D01*
|
||||
G75*
|
||||
G02*
|
||||
X107752000Y-128848200I-76200J0D01*
|
||||
G01*
|
||||
X106228000Y-128848200D01*
|
||||
G75*
|
||||
G02*
|
||||
X106151800Y-128772000I0J76200D01*
|
||||
G01*
|
||||
X106151800Y-127248000D01*
|
||||
G75*
|
||||
G02*
|
||||
X106228000Y-127171800I76200J0D01*
|
||||
G01*
|
||||
X107752000Y-127171800D01*
|
||||
G75*
|
||||
G02*
|
||||
X107828200Y-127248000I0J-76200D01*
|
||||
G01*
|
||||
G37*
|
||||
X106990000Y-130550000D03*
|
||||
X104450000Y-128010000D03*
|
||||
X104450000Y-130550000D03*
|
||||
X101910000Y-128010000D03*
|
||||
X101910000Y-130550000D03*
|
||||
X99370000Y-128010000D03*
|
||||
X99370000Y-130550000D03*
|
||||
X96830000Y-128010000D03*
|
||||
X96830000Y-130550000D03*
|
||||
X94290000Y-128010000D03*
|
||||
X94290000Y-130550000D03*
|
||||
X91750000Y-128010000D03*
|
||||
X91750000Y-130550000D03*
|
||||
X89210000Y-128010000D03*
|
||||
X89210000Y-130550000D03*
|
||||
G04 #@! TD*
|
||||
G04 #@! TO.C,P16*
|
||||
G36*
|
||||
G01*
|
||||
X179056200Y-165160000D02*
|
||||
X179056200Y-167825000D01*
|
||||
G75*
|
||||
G02*
|
||||
X178980000Y-167901200I-76200J0D01*
|
||||
G01*
|
||||
X174790000Y-167901200D01*
|
||||
G75*
|
||||
G02*
|
||||
X174713800Y-167825000I0J76200D01*
|
||||
G01*
|
||||
X174713800Y-165160000D01*
|
||||
G75*
|
||||
G02*
|
||||
X174790000Y-165083800I76200J0D01*
|
||||
G01*
|
||||
X178980000Y-165083800D01*
|
||||
G75*
|
||||
G02*
|
||||
X179056200Y-165160000I0J-76200D01*
|
||||
G01*
|
||||
G37*
|
||||
G36*
|
||||
G01*
|
||||
X179056200Y-158175000D02*
|
||||
X179056200Y-160840000D01*
|
||||
G75*
|
||||
G02*
|
||||
X178980000Y-160916200I-76200J0D01*
|
||||
G01*
|
||||
X174790000Y-160916200D01*
|
||||
G75*
|
||||
G02*
|
||||
X174713800Y-160840000I0J76200D01*
|
||||
G01*
|
||||
X174713800Y-158175000D01*
|
||||
G75*
|
||||
G02*
|
||||
X174790000Y-158098800I76200J0D01*
|
||||
G01*
|
||||
X178980000Y-158098800D01*
|
||||
G75*
|
||||
G02*
|
||||
X179056200Y-158175000I0J-76200D01*
|
||||
G01*
|
||||
G37*
|
||||
G04 #@! TD*
|
||||
G04 #@! TO.C,P20*
|
||||
G36*
|
||||
G01*
|
||||
X173792000Y-156788200D02*
|
||||
X172268000Y-156788200D01*
|
||||
G75*
|
||||
G02*
|
||||
X172191800Y-156712000I0J76200D01*
|
||||
G01*
|
||||
X172191800Y-155188000D01*
|
||||
G75*
|
||||
G02*
|
||||
X172268000Y-155111800I76200J0D01*
|
||||
G01*
|
||||
X173792000Y-155111800D01*
|
||||
G75*
|
||||
G02*
|
||||
X173868200Y-155188000I0J-76200D01*
|
||||
G01*
|
||||
X173868200Y-156712000D01*
|
||||
G75*
|
||||
G02*
|
||||
X173792000Y-156788200I-76200J0D01*
|
||||
G01*
|
||||
G37*
|
||||
X170490000Y-155950000D03*
|
||||
X173030000Y-153410000D03*
|
||||
X170490000Y-153410000D03*
|
||||
X173030000Y-150870000D03*
|
||||
X170490000Y-150870000D03*
|
||||
X173030000Y-148330000D03*
|
||||
X170490000Y-148330000D03*
|
||||
X173030000Y-145790000D03*
|
||||
X170490000Y-145790000D03*
|
||||
X173030000Y-143250000D03*
|
||||
X170490000Y-143250000D03*
|
||||
X173030000Y-140710000D03*
|
||||
X170490000Y-140710000D03*
|
||||
X173030000Y-138170000D03*
|
||||
X170490000Y-138170000D03*
|
||||
X173030000Y-135630000D03*
|
||||
X170490000Y-135630000D03*
|
||||
X173030000Y-133090000D03*
|
||||
X170490000Y-133090000D03*
|
||||
X173030000Y-130550000D03*
|
||||
X170490000Y-130550000D03*
|
||||
G04 #@! TD*
|
||||
G04 #@! TO.C,P22*
|
||||
G36*
|
||||
G01*
|
||||
X168788200Y-162808000D02*
|
||||
X168788200Y-164332000D01*
|
||||
G75*
|
||||
G02*
|
||||
X168712000Y-164408200I-76200J0D01*
|
||||
G01*
|
||||
X167188000Y-164408200D01*
|
||||
G75*
|
||||
G02*
|
||||
X167111800Y-164332000I0J76200D01*
|
||||
G01*
|
||||
X167111800Y-162808000D01*
|
||||
G75*
|
||||
G02*
|
||||
X167188000Y-162731800I76200J0D01*
|
||||
G01*
|
||||
X168712000Y-162731800D01*
|
||||
G75*
|
||||
G02*
|
||||
X168788200Y-162808000I0J-76200D01*
|
||||
G01*
|
||||
G37*
|
||||
X167950000Y-166110000D03*
|
||||
X165410000Y-163570000D03*
|
||||
X165410000Y-166110000D03*
|
||||
X162870000Y-163570000D03*
|
||||
X162870000Y-166110000D03*
|
||||
X160330000Y-163570000D03*
|
||||
X160330000Y-166110000D03*
|
||||
X157790000Y-163570000D03*
|
||||
X157790000Y-166110000D03*
|
||||
X155250000Y-163570000D03*
|
||||
X155250000Y-166110000D03*
|
||||
X152710000Y-163570000D03*
|
||||
X152710000Y-166110000D03*
|
||||
X150170000Y-163570000D03*
|
||||
X150170000Y-166110000D03*
|
||||
X147630000Y-163570000D03*
|
||||
X147630000Y-166110000D03*
|
||||
X145090000Y-163570000D03*
|
||||
X145090000Y-166110000D03*
|
||||
X142550000Y-163570000D03*
|
||||
X142550000Y-166110000D03*
|
||||
X140010000Y-163570000D03*
|
||||
X140010000Y-166110000D03*
|
||||
X137470000Y-163570000D03*
|
||||
X137470000Y-166110000D03*
|
||||
G04 #@! TD*
|
||||
G04 #@! TO.C,P25*
|
||||
G36*
|
||||
G01*
|
||||
X136631800Y-159252000D02*
|
||||
X136631800Y-157728000D01*
|
||||
G75*
|
||||
G02*
|
||||
X136708000Y-157651800I76200J0D01*
|
||||
G01*
|
||||
X138232000Y-157651800D01*
|
||||
G75*
|
||||
G02*
|
||||
X138308200Y-157728000I0J-76200D01*
|
||||
G01*
|
||||
X138308200Y-159252000D01*
|
||||
G75*
|
||||
G02*
|
||||
X138232000Y-159328200I-76200J0D01*
|
||||
G01*
|
||||
X136708000Y-159328200D01*
|
||||
G75*
|
||||
G02*
|
||||
X136631800Y-159252000I0J76200D01*
|
||||
G01*
|
||||
G37*
|
||||
X140010000Y-158490000D03*
|
||||
X142550000Y-158490000D03*
|
||||
X145090000Y-158490000D03*
|
||||
X147630000Y-158490000D03*
|
||||
X150170000Y-158490000D03*
|
||||
G04 #@! TD*
|
||||
G04 #@! TO.C,P26*
|
||||
G36*
|
||||
G01*
|
||||
X151129200Y-113857000D02*
|
||||
X152196000Y-113857000D01*
|
||||
G75*
|
||||
G02*
|
||||
X152272200Y-113933200I0J-76200D01*
|
||||
G01*
|
||||
X152272200Y-115000000D01*
|
||||
G75*
|
||||
G02*
|
||||
X152196000Y-115076200I-76200J0D01*
|
||||
G01*
|
||||
X151129200Y-115076200D01*
|
||||
G75*
|
||||
G02*
|
||||
X151053000Y-115000000I0J76200D01*
|
||||
G01*
|
||||
X151053000Y-113933200D01*
|
||||
G75*
|
||||
G02*
|
||||
X151129200Y-113857000I76200J0D01*
|
||||
G01*
|
||||
G37*
|
||||
D17*
|
||||
X152932600Y-114466600D03*
|
||||
X151662600Y-115736600D03*
|
||||
X152932600Y-115736600D03*
|
||||
X151662600Y-117006600D03*
|
||||
X152932600Y-117006600D03*
|
||||
X151662600Y-118276600D03*
|
||||
X152932600Y-118276600D03*
|
||||
X151662600Y-119546600D03*
|
||||
X152932600Y-119546600D03*
|
||||
G04 #@! TD*
|
||||
G04 #@! TO.C,P28*
|
||||
G36*
|
||||
G01*
|
||||
X125532000Y-156788200D02*
|
||||
X124008000Y-156788200D01*
|
||||
G75*
|
||||
G02*
|
||||
X123931800Y-156712000I0J76200D01*
|
||||
G01*
|
||||
X123931800Y-155188000D01*
|
||||
G75*
|
||||
G02*
|
||||
X124008000Y-155111800I76200J0D01*
|
||||
G01*
|
||||
X125532000Y-155111800D01*
|
||||
G75*
|
||||
G02*
|
||||
X125608200Y-155188000I0J-76200D01*
|
||||
G01*
|
||||
X125608200Y-156712000D01*
|
||||
G75*
|
||||
G02*
|
||||
X125532000Y-156788200I-76200J0D01*
|
||||
G01*
|
||||
G37*
|
||||
D10*
|
||||
X122230000Y-155950000D03*
|
||||
X124770000Y-153410000D03*
|
||||
X122230000Y-153410000D03*
|
||||
X124770000Y-150870000D03*
|
||||
X122230000Y-150870000D03*
|
||||
X124770000Y-148330000D03*
|
||||
X122230000Y-148330000D03*
|
||||
X124770000Y-145790000D03*
|
||||
X122230000Y-145790000D03*
|
||||
X124770000Y-143250000D03*
|
||||
X122230000Y-143250000D03*
|
||||
X124770000Y-140710000D03*
|
||||
X122230000Y-140710000D03*
|
||||
X124770000Y-138170000D03*
|
||||
X122230000Y-138170000D03*
|
||||
X124770000Y-135630000D03*
|
||||
X122230000Y-135630000D03*
|
||||
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|
||||
X6.8224Y-4.5075
|
||||
X6.8904Y-4.2575
|
||||
T3
|
||||
X3.6032Y-6.1679
|
||||
X3.6032Y-6.2112
|
||||
X3.6032Y-6.2545
|
||||
X3.6465Y-6.1679
|
||||
X3.6465Y-6.2112
|
||||
X3.6465Y-6.2545
|
||||
X3.6898Y-6.1679
|
||||
X3.6898Y-6.2112
|
||||
X3.6898Y-6.2545
|
||||
X4.9925Y-6.3884
|
||||
X4.9925Y-6.4404
|
||||
X5.0185Y-6.4144
|
||||
X5.0445Y-6.3884
|
||||
X5.0445Y-6.4404
|
||||
T4
|
||||
X2.4331Y-4.0945
|
||||
X2.4331Y-6.7323
|
||||
X2.4587Y-4.0335
|
||||
X2.4587Y-4.1555
|
||||
X2.4587Y-6.6713
|
||||
X2.4587Y-6.7933
|
||||
X2.4614Y-6.1614
|
||||
X2.4614Y-6.2008
|
||||
X2.4614Y-6.2402
|
||||
X2.4614Y-6.437
|
||||
X2.4614Y-6.4764
|
||||
X2.4614Y-6.5157
|
||||
X2.5008Y-6.1614
|
||||
X2.5008Y-6.2008
|
||||
X2.5008Y-6.2402
|
||||
X2.5008Y-6.437
|
||||
X2.5008Y-6.4764
|
||||
X2.5008Y-6.5157
|
||||
X2.5197Y-4.0079
|
||||
X2.5197Y-4.1811
|
||||
X2.5197Y-6.6457
|
||||
X2.5197Y-6.8189
|
||||
X2.5402Y-6.1614
|
||||
X2.5402Y-6.2008
|
||||
X2.5402Y-6.2402
|
||||
X2.5402Y-6.437
|
||||
X2.5402Y-6.4764
|
||||
X2.5402Y-6.5157
|
||||
X2.5807Y-4.0335
|
||||
X2.5807Y-4.1555
|
||||
X2.5807Y-6.6713
|
||||
X2.5807Y-6.7933
|
||||
X2.6063Y-4.0945
|
||||
X2.6063Y-6.7323
|
||||
X3.986Y-4.3627
|
||||
X3.986Y-4.4276
|
||||
X3.986Y-4.4926
|
||||
X4.051Y-4.3627
|
||||
X4.051Y-4.4276
|
||||
X4.051Y-4.4926
|
||||
X4.116Y-4.3627
|
||||
X4.116Y-4.4276
|
||||
X4.116Y-4.4926
|
||||
X4.2184Y-5.5274
|
||||
X4.2184Y-5.5865
|
||||
X4.2184Y-5.6456
|
||||
X4.2775Y-5.5274
|
||||
X4.2775Y-5.5865
|
||||
X4.2775Y-5.6456
|
||||
X4.3366Y-5.5274
|
||||
X4.3366Y-5.5865
|
||||
X4.3366Y-5.6456
|
||||
X4.874Y-4.0945
|
||||
X4.8996Y-4.0335
|
||||
X4.8996Y-4.1555
|
||||
X4.9606Y-4.0079
|
||||
X4.9606Y-4.1811
|
||||
X5.0217Y-4.0335
|
||||
X5.0217Y-4.1555
|
||||
X5.0472Y-4.0945
|
||||
X5.0709Y-5.6693
|
||||
X5.0965Y-5.6083
|
||||
X5.0965Y-5.7303
|
||||
X5.1575Y-5.5827
|
||||
X5.1575Y-5.7559
|
||||
X5.2185Y-5.6083
|
||||
X5.2185Y-5.7303
|
||||
X5.2441Y-5.6693
|
||||
X6.8425Y-4.0945
|
||||
X6.8425Y-6.7323
|
||||
X6.8681Y-4.0335
|
||||
X6.8681Y-4.1555
|
||||
X6.8681Y-6.6713
|
||||
X6.8681Y-6.7933
|
||||
X6.9087Y-5.5315
|
||||
X6.9087Y-5.5709
|
||||
X6.9087Y-5.6102
|
||||
X6.9087Y-5.8071
|
||||
X6.9087Y-5.8465
|
||||
X6.9087Y-5.8858
|
||||
X6.9087Y-6.2402
|
||||
X6.9087Y-6.2795
|
||||
X6.9087Y-6.3189
|
||||
X6.9087Y-6.5157
|
||||
X6.9087Y-6.5551
|
||||
X6.9087Y-6.5945
|
||||
X6.9291Y-4.0079
|
||||
X6.9291Y-4.1811
|
||||
X6.9291Y-6.6457
|
||||
X6.9291Y-6.8189
|
||||
X6.948Y-5.5315
|
||||
X6.948Y-5.5709
|
||||
X6.948Y-5.6102
|
||||
X6.948Y-5.8071
|
||||
X6.948Y-5.8465
|
||||
X6.948Y-5.8858
|
||||
X6.948Y-6.2402
|
||||
X6.948Y-6.2795
|
||||
X6.948Y-6.3189
|
||||
X6.948Y-6.5157
|
||||
X6.948Y-6.5551
|
||||
X6.948Y-6.5945
|
||||
X6.9874Y-5.5315
|
||||
X6.9874Y-5.5709
|
||||
X6.9874Y-5.6102
|
||||
X6.9874Y-5.8071
|
||||
X6.9874Y-5.8465
|
||||
X6.9874Y-5.8858
|
||||
X6.9874Y-6.2402
|
||||
X6.9874Y-6.2795
|
||||
X6.9874Y-6.3189
|
||||
X6.9874Y-6.5157
|
||||
X6.9874Y-6.5551
|
||||
X6.9874Y-6.5945
|
||||
X6.9902Y-4.0335
|
||||
X6.9902Y-4.1555
|
||||
X6.9902Y-6.6713
|
||||
X6.9902Y-6.7933
|
||||
X7.0157Y-4.0945
|
||||
X7.0157Y-6.7323
|
||||
T5
|
||||
X2.5032Y-4.6368
|
||||
X3.6355Y-5.8922
|
||||
X3.6355Y-5.9452
|
||||
X3.6755Y-5.9452
|
||||
X3.7155Y-5.9452
|
||||
X3.7452Y-5.9098
|
||||
X3.7805Y-5.8812
|
||||
X3.796Y-4.7176
|
||||
X3.8255Y-5.8962
|
||||
X3.836Y-4.7176
|
||||
X3.8705Y-5.9262
|
||||
X3.876Y-4.7176
|
||||
X3.916Y-4.7176
|
||||
X3.9212Y-4.2148
|
||||
X3.9268Y-4.2578
|
||||
X3.956Y-4.6076
|
||||
X3.956Y-4.7176
|
||||
X3.9892Y-6.3158
|
||||
X4.0052Y-6.4648
|
||||
X4.04Y-4.7176
|
||||
X4.076Y-4.7136
|
||||
X4.1055Y-5.5195
|
||||
X4.112Y-6.286
|
||||
X4.1532Y-4.7228
|
||||
X4.1607Y-6.5113
|
||||
X4.1992Y-4.7288
|
||||
X4.269Y-6.483
|
||||
X4.4375Y-5.5305
|
||||
X4.4435Y-5.5845
|
||||
X4.4602Y-5.6588
|
||||
X4.4725Y-5.5475
|
||||
X4.546Y-5.364
|
||||
X4.61Y-4.393
|
||||
X4.6192Y-4.7448
|
||||
X4.6232Y-4.8048
|
||||
X4.699Y-6.6475
|
||||
X4.736Y-6.812
|
||||
X4.7462Y-4.7868
|
||||
X4.8042Y-4.6878
|
||||
X4.8042Y-4.8028
|
||||
X4.8052Y-4.7648
|
||||
X4.8062Y-4.7268
|
||||
X4.8542Y-6.2188
|
||||
X4.8902Y-6.3418
|
||||
X4.9232Y-4.9848
|
||||
X4.9642Y-5.8258
|
||||
X4.9792Y-5.8908
|
||||
X4.9942Y-5.9438
|
||||
X5.0062Y-5.8648
|
||||
X5.0082Y-4.4088
|
||||
X5.0102Y-4.3698
|
||||
X5.0202Y-5.8998
|
||||
X5.0602Y-4.4328
|
||||
X5.0692Y-4.3748
|
||||
X5.0832Y-5.3108
|
||||
X5.0892Y-4.4068
|
||||
X5.0912Y-5.1178
|
||||
X5.0972Y-5.3458
|
||||
X5.1082Y-4.4398
|
||||
X5.1202Y-5.3988
|
||||
X5.1792Y-5.9088
|
||||
X5.2052Y-5.1268
|
||||
X5.2442Y-5.9538
|
||||
X5.2792Y-6.2628
|
||||
X5.3072Y-5.9548
|
||||
X5.3082Y-6.4048
|
||||
X5.3223Y-5.1069
|
||||
X5.3292Y-6.4428
|
||||
X5.3662Y-6.3488
|
||||
X5.4302Y-5.0778
|
||||
X5.4422Y-5.0198
|
||||
X5.499Y-5.641
|
||||
X5.592Y-5.532
|
||||
X5.6182Y-5.0338
|
||||
X5.6212Y-6.0358
|
||||
X5.6332Y-5.8068
|
||||
X5.641Y-5.537
|
||||
X5.6722Y-4.5148
|
||||
X5.6912Y-5.7288
|
||||
X5.7022Y-5.8718
|
||||
X5.7282Y-4.8168
|
||||
X5.7712Y-4.8158
|
||||
X5.8522Y-5.4918
|
||||
X5.9062Y-5.2108
|
||||
X5.9222Y-5.2468
|
||||
X5.9692Y-5.3098
|
||||
X6.0762Y-5.6748
|
||||
X6.08Y-5.846
|
||||
X6.108Y-4.5976
|
||||
X6.1082Y-4.6388
|
||||
X6.117Y-6.27
|
||||
X6.1492Y-4.7878
|
||||
X6.1632Y-6.1358
|
||||
X6.1782Y-6.1008
|
||||
X6.1872Y-5.1258
|
||||
X6.2042Y-5.3228
|
||||
X6.2082Y-4.6858
|
||||
X6.2172Y-6.1048
|
||||
X6.2342Y-4.5988
|
||||
X6.2342Y-4.8668
|
||||
X6.2358Y-5.8647
|
||||
X6.2772Y-4.9368
|
||||
X6.2832Y-6.0688
|
||||
X6.3202Y-4.8768
|
||||
X6.3572Y-4.6988
|
||||
X6.3701Y-4.8583
|
||||
X6.39Y-6.191
|
||||
X6.417Y-6.221
|
||||
X6.4472Y-5.9808
|
||||
X6.49Y-5.485
|
||||
X6.5082Y-5.0818
|
||||
X6.5682Y-5.9148
|
||||
X6.599Y-5.891
|
||||
X6.6142Y-5.2108
|
||||
X6.628Y-6.198
|
||||
X6.665Y-5.806
|
||||
X6.7934Y-4.3505
|
||||
X6.8044Y-4.4675
|
||||
X6.8894Y-4.3075
|
||||
X6.8894Y-4.5575
|
||||
X6.925Y-4.2336
|
||||
T6
|
||||
X2.8774Y-6.4385
|
||||
X2.9234Y-6.3705
|
||||
X3.5715Y-6.4792
|
||||
X3.6765Y-6.4792
|
||||
X3.7335Y-4.4801
|
||||
X4.0015Y-5.5375
|
||||
X4.081Y-4.6076
|
||||
X4.2855Y-5.9445
|
||||
X4.2995Y-5.9885
|
||||
X4.3275Y-5.3055
|
||||
X4.3385Y-5.4105
|
||||
X4.5575Y-5.5065
|
||||
X4.5585Y-5.5845
|
||||
X5.0985Y-6.6144
|
||||
X5.1885Y-6.5594
|
||||
X6.2591Y-5.6646
|
||||
X6.3348Y-5.2495
|
||||
T7
|
||||
X2.4622Y-4.6738
|
||||
X2.4722Y-5.1898
|
||||
X2.4722Y-5.3698
|
||||
X2.4722Y-5.5488
|
||||
X2.4722Y-5.7288
|
||||
X2.4722Y-5.9088
|
||||
X2.5122Y-5.2898
|
||||
X2.5822Y-6.4098
|
||||
X2.6673Y-5.3937
|
||||
X2.6673Y-5.6299
|
||||
X2.6673Y-5.8661
|
||||
X2.6673Y-6.1024
|
||||
X2.6673Y-6.5748
|
||||
X2.6722Y-4.3088
|
||||
X2.6722Y-4.8188
|
||||
X2.7165Y-6.2598
|
||||
X2.7244Y-6.0205
|
||||
X2.7284Y-6.0995
|
||||
X2.7284Y-6.1825
|
||||
X2.7342Y-5.8268
|
||||
X2.7594Y-5.9405
|
||||
X2.7704Y-5.8805
|
||||
X2.7894Y-6.0875
|
||||
X2.7932Y-5.6721
|
||||
X2.8254Y-6.2705
|
||||
X2.8312Y-5.5851
|
||||
X2.8346Y-5.2362
|
||||
X2.8346Y-6.7323
|
||||
X2.8702Y-6.5008
|
||||
X2.8982Y-6.6198
|
||||
X2.9324Y-5.9245
|
||||
X2.9344Y-5.8605
|
||||
X2.948Y-5.5
|
||||
X2.9494Y-6.1135
|
||||
X2.96Y-6.6064
|
||||
X2.965Y-6.42
|
||||
X2.987Y-5.862
|
||||
X3.0034Y-6.0675
|
||||
X3.025Y-5.945
|
||||
X3.0604Y-6.2075
|
||||
X3.065Y-5.823
|
||||
X3.0702Y-5.6641
|
||||
X3.0709Y-5.2362
|
||||
X3.0709Y-6.7323
|
||||
X3.1002Y-5.5281
|
||||
X3.113Y-6.642
|
||||
X3.125Y-6.5514
|
||||
X3.1652Y-5.6781
|
||||
X3.1802Y-4.7498
|
||||
X3.2152Y-5.6781
|
||||
X3.2194Y-6.2335
|
||||
X3.2244Y-6.0405
|
||||
X3.239Y-5.822
|
||||
X3.2602Y-4.6718
|
||||
X3.2702Y-5.5281
|
||||
X3.2892Y-4.1898
|
||||
X3.2952Y-5.6691
|
||||
X3.3071Y-5.2362
|
||||
X3.3071Y-6.7323
|
||||
X3.3232Y-4.0778
|
||||
X3.3802Y-4.3278
|
||||
X3.3912Y-4.0428
|
||||
X3.4048Y-5.6489
|
||||
X3.4312Y-4.7898
|
||||
X3.4528Y-5.4409
|
||||
X3.4615Y-5.9812
|
||||
X3.492Y-6.202
|
||||
X3.4965Y-6.0812
|
||||
X3.5065Y-6.4192
|
||||
X3.5388Y-5.7589
|
||||
X3.5433Y-5.2362
|
||||
X3.5433Y-6.7323
|
||||
X3.5865Y-6.3692
|
||||
X3.6265Y-6.4792
|
||||
X3.6405Y-6.0462
|
||||
X3.6488Y-5.5899
|
||||
X3.6655Y-6.3712
|
||||
X3.7008Y-5.2854
|
||||
X3.7185Y-6.5412
|
||||
X3.7252Y-4.4233
|
||||
X3.7485Y-4.3451
|
||||
X3.7795Y-6.7323
|
||||
X3.7827Y-4.5788
|
||||
X3.8055Y-6.0962
|
||||
X3.8427Y-4.4258
|
||||
X3.8475Y-6.4062
|
||||
X3.8515Y-4.5171
|
||||
X3.8635Y-4.2401
|
||||
X3.8682Y-4.3368
|
||||
X3.8965Y-6.5962
|
||||
X3.8976Y-5.2953
|
||||
X3.905Y-6.42
|
||||
X3.9225Y-4.1661
|
||||
X3.9255Y-6.1412
|
||||
X3.926Y-6.321
|
||||
X3.954Y-6.096
|
||||
X3.9705Y-6.3712
|
||||
X3.9945Y-4.2451
|
||||
X4.0157Y-6.7323
|
||||
X4.016Y-6.09
|
||||
X4.0365Y-5.4765
|
||||
X4.0365Y-5.6915
|
||||
X4.039Y-6.324
|
||||
X4.0412Y-4.1668
|
||||
X4.1009Y-6.5769
|
||||
X4.1043Y-5.2854
|
||||
X4.1529Y-6.4429
|
||||
X4.156Y-4.6086
|
||||
X4.1725Y-5.7475
|
||||
X4.1725Y-5.8665
|
||||
X4.1785Y-5.9665
|
||||
X4.1874Y-6.2269
|
||||
X4.2065Y-4.5711
|
||||
X4.215Y-6.037
|
||||
X4.229Y-4.6886
|
||||
X4.2362Y-4.4458
|
||||
X4.252Y-5.2362
|
||||
X4.252Y-6.7323
|
||||
X4.2769Y-6.6369
|
||||
X4.2925Y-5.7485
|
||||
X4.2925Y-5.8665
|
||||
X4.3161Y-6.2076
|
||||
X4.3505Y-4.4071
|
||||
X4.3505Y-4.4551
|
||||
X4.3775Y-5.3055
|
||||
X4.4065Y-5.9665
|
||||
X4.4094Y-5.0984
|
||||
X4.416Y-6.223
|
||||
X4.4375Y-5.6965
|
||||
X4.4475Y-5.3455
|
||||
X4.4775Y-5.7765
|
||||
X4.4882Y-5.2362
|
||||
X4.4882Y-6.7323
|
||||
X4.49Y-4.567
|
||||
X4.57Y-4.607
|
||||
X4.5875Y-5.5465
|
||||
X4.6063Y-5.7087
|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
X4.7047Y-5.5512
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
X4.7742Y-6.2598
|
||||
X4.8085Y-6.5354
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
X4.8722Y-5.6898
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
X5.4932Y-6.1098
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||||
X5.5172Y-4.3868
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||||
X5.5711Y-5.9212
|
||||
X5.6112Y-6.1568
|
||||
X5.6242Y-4.8924
|
||||
X5.6672Y-6.1318
|
||||
X5.7168Y-4.9737
|
||||
X5.7514Y-6.1016
|
||||
X5.8165Y-5.055
|
||||
X5.8964Y-4.8677
|
||||
X5.9636Y-4.9136
|
||||
X5.9742Y-6.1207
|
||||
X5.988Y-6.322
|
||||
X6.0131Y-6.0874
|
||||
X6.0732Y-5.1929
|
||||
X6.0979Y-6.1723
|
||||
X6.111Y-6.321
|
||||
X6.1297Y-5.2495
|
||||
X6.151Y-5.0656
|
||||
X6.2358Y-4.9808
|
||||
X6.2623Y-5.1846
|
||||
X6.2712Y-5.0162
|
||||
X6.2942Y-5.8108
|
||||
X6.3207Y-5.9495
|
||||
X6.3355Y-5.4496
|
||||
X6.3461Y-5.0968
|
||||
X6.3737Y-5.7268
|
||||
X6.3744Y-4.4075
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||||
X6.3772Y-5.893
|
||||
X6.4303Y-5.6702
|
||||
X6.4367Y-5.3588
|
||||
X6.4586Y-5.8116
|
||||
X6.479Y-6.124
|
||||
X6.5072Y-4.7368
|
||||
X6.5151Y-5.2955
|
||||
X6.5151Y-5.7551
|
||||
X6.5328Y-5.1222
|
||||
X6.5363Y-5.3591
|
||||
X6.5399Y-5.2071
|
||||
X6.5594Y-4.4075
|
||||
X6.6112Y-4.9163
|
||||
X6.6302Y-5.0318
|
||||
X6.6372Y-4.8048
|
||||
X6.7144Y-4.1425
|
||||
X6.7144Y-4.6725
|
||||
X6.7594Y-4.2575
|
||||
X6.7594Y-4.5575
|
||||
X6.7776Y-4.9163
|
||||
X6.8122Y-6.5718
|
||||
X6.8694Y-4.5075
|
||||
X6.8898Y-4.6969
|
||||
X6.9324Y-4.3749
|
||||
X6.9372Y-5.9848
|
||||
T8
|
||||
X6.9201Y-4.7839
|
||||
X6.9201Y-4.9799
|
||||
T9
|
||||
X5.971Y-4.5066
|
||||
X5.971Y-4.5566
|
||||
X5.971Y-4.6066
|
||||
X5.971Y-4.6566
|
||||
X5.971Y-4.7066
|
||||
X6.021Y-4.5066
|
||||
X6.021Y-4.5566
|
||||
X6.021Y-4.6066
|
||||
X6.021Y-4.6566
|
||||
X6.021Y-4.7066
|
||||
T10
|
||||
X7.0394Y-4.7195
|
||||
X7.0394Y-5.0443
|
||||
T11
|
||||
X2.4685Y-4.2972
|
||||
X2.4685Y-4.4744
|
||||
X2.4685Y-4.8091
|
||||
X2.4685Y-4.9862
|
||||
T12
|
||||
X3.3122Y-4.9398
|
||||
X3.3122Y-5.0398
|
||||
X3.4122Y-4.1398
|
||||
X3.4122Y-4.2398
|
||||
X3.5122Y-4.1398
|
||||
X3.5122Y-4.2398
|
||||
X3.5122Y-5.0398
|
||||
X3.5122Y-5.1398
|
||||
X3.6122Y-4.1398
|
||||
X3.6122Y-4.2398
|
||||
X3.6122Y-5.0398
|
||||
X3.6122Y-5.1398
|
||||
X3.7122Y-5.0398
|
||||
X3.7122Y-5.1398
|
||||
X3.8122Y-5.0398
|
||||
X3.8122Y-5.1398
|
||||
X3.9122Y-5.0398
|
||||
X3.9122Y-5.1398
|
||||
X4.0122Y-5.0398
|
||||
X4.0122Y-5.1398
|
||||
X4.1122Y-5.0398
|
||||
X4.1122Y-5.1398
|
||||
X4.2122Y-5.0398
|
||||
X4.2122Y-5.1398
|
||||
X4.8122Y-5.1398
|
||||
X4.8122Y-5.2398
|
||||
X4.8122Y-5.3398
|
||||
X4.8122Y-5.4398
|
||||
X4.8122Y-5.5398
|
||||
X4.8122Y-5.6398
|
||||
X4.8122Y-5.7398
|
||||
X4.8122Y-5.8398
|
||||
X4.8122Y-5.9398
|
||||
X4.8122Y-6.0398
|
||||
X4.8122Y-6.1398
|
||||
X4.9122Y-5.1398
|
||||
X4.9122Y-5.2398
|
||||
X4.9122Y-5.3398
|
||||
X4.9122Y-5.4398
|
||||
X4.9122Y-5.5398
|
||||
X4.9122Y-5.6398
|
||||
X4.9122Y-5.7398
|
||||
X4.9122Y-5.8398
|
||||
X4.9122Y-5.9398
|
||||
X4.9122Y-6.0398
|
||||
X4.9122Y-6.1398
|
||||
X5.1122Y-5.2398
|
||||
X5.2122Y-5.2398
|
||||
X5.4122Y-4.1398
|
||||
X5.4122Y-4.2398
|
||||
X5.4122Y-6.2398
|
||||
X5.4122Y-6.4398
|
||||
X5.4122Y-6.5398
|
||||
X5.5122Y-4.1398
|
||||
X5.5122Y-4.2398
|
||||
X5.5122Y-6.2398
|
||||
X5.5122Y-6.4398
|
||||
X5.5122Y-6.5398
|
||||
X5.6122Y-4.1398
|
||||
X5.6122Y-4.2398
|
||||
X5.6122Y-6.2398
|
||||
X5.6122Y-6.4398
|
||||
X5.6122Y-6.5398
|
||||
X5.7122Y-4.1398
|
||||
X5.7122Y-4.2398
|
||||
X5.7122Y-4.4398
|
||||
X5.7122Y-4.6398
|
||||
X5.7122Y-4.7398
|
||||
X5.7122Y-6.2398
|
||||
X5.7122Y-6.4398
|
||||
X5.7122Y-6.5398
|
||||
X5.8122Y-4.1398
|
||||
X5.8122Y-4.2398
|
||||
X5.8122Y-4.4398
|
||||
X5.8122Y-6.2398
|
||||
X5.8122Y-6.4398
|
||||
X5.8122Y-6.5398
|
||||
X5.9122Y-4.1398
|
||||
X5.9122Y-4.2398
|
||||
X5.9122Y-6.2398
|
||||
X5.9122Y-6.4398
|
||||
X5.9122Y-6.5398
|
||||
X6.0122Y-4.1398
|
||||
X6.0122Y-4.2398
|
||||
X6.0122Y-6.4398
|
||||
X6.0122Y-6.5398
|
||||
X6.1122Y-4.1398
|
||||
X6.1122Y-4.2398
|
||||
X6.1122Y-6.4398
|
||||
X6.1122Y-6.5398
|
||||
X6.2122Y-4.1398
|
||||
X6.2122Y-4.2398
|
||||
X6.2122Y-4.4398
|
||||
X6.2122Y-6.4398
|
||||
X6.2122Y-6.5398
|
||||
X6.3122Y-4.1398
|
||||
X6.3122Y-4.2398
|
||||
X6.3122Y-4.4398
|
||||
X6.3122Y-6.4398
|
||||
X6.3122Y-6.5398
|
||||
X6.4122Y-6.4398
|
||||
X6.4122Y-6.5398
|
||||
X6.5122Y-6.4398
|
||||
X6.5122Y-6.5398
|
||||
X6.6122Y-6.4398
|
||||
X6.6122Y-6.5398
|
||||
X6.7122Y-5.1398
|
||||
X6.7122Y-5.2398
|
||||
X6.7122Y-5.3398
|
||||
X6.7122Y-5.4398
|
||||
X6.7122Y-5.5398
|
||||
X6.7122Y-5.6398
|
||||
X6.7122Y-5.7398
|
||||
X6.7122Y-5.8398
|
||||
X6.7122Y-5.9398
|
||||
X6.7122Y-6.0398
|
||||
X6.7122Y-6.1398
|
||||
X6.8122Y-5.1398
|
||||
X6.8122Y-5.2398
|
||||
X6.8122Y-5.3398
|
||||
X6.8122Y-5.4398
|
||||
X6.8122Y-5.5398
|
||||
X6.8122Y-5.6398
|
||||
X6.8122Y-5.7398
|
||||
X6.8122Y-5.8398
|
||||
X6.8122Y-5.9398
|
||||
X6.8122Y-6.0398
|
||||
X6.8122Y-6.1398
|
||||
X7.0122Y-5.1398
|
||||
X7.0122Y-5.2398
|
||||
T13
|
||||
X2.5665Y-4.2478
|
||||
X2.5665Y-4.5238
|
||||
X2.5665Y-4.7596
|
||||
X2.5665Y-5.0356
|
||||
T14
|
||||
X2.5197Y-4.0945
|
||||
X2.5197Y-6.7323
|
||||
X4.9606Y-4.0945
|
||||
X5.1575Y-5.6693
|
||||
X6.9291Y-4.0945
|
||||
X6.9291Y-6.7323
|
||||
T0
|
||||
M30
|
||||
Binary file not shown.
Binary file not shown.
@ -0,0 +1,368 @@
|
||||
ref;value;Field1;Field2;Field3;Field4;Field5;Field6;Field7;Field8
|
||||
C1;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C2;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C3;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C4;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C5;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C6;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C7;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C8;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
|
||||
C9;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C10;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C11;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C12;330pF;Murata;GRM155R71H331KA01D;CAP CER 330PF 50V 10% X7R 0402
|
||||
C13;330pF;Murata;GRM155R71H331KA01D;CAP CER 330PF 50V 10% X7R 0402
|
||||
C14;8p2;Taiyo Yuden;UMK105CG8R2DV-F;CAP CER 8.2PF 50V NP0 0402
|
||||
C15;180pF;Murata;GRM1555C1H181JA01D;CAP CER 180PF 50V 5% NP0 0402
|
||||
C16;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C17;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C18;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C19;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C20;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C21;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
|
||||
C22;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C23;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C24;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C25;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C26;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
|
||||
C27;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
|
||||
C28;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C29;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C30;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C31;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C32;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
|
||||
C33;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C34;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C35;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C36;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C37;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C38;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C39;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C40;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C41;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
|
||||
C42;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
|
||||
C43;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
|
||||
C44;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C45;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C46;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C47;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C48;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
|
||||
C49;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C50;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
|
||||
C51;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
|
||||
C52;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
|
||||
C53;1uF;Taiyo Yuden;LMK105BJ105KV-F;CAP CER 1UF 10V 10% X5R 0402
|
||||
C54;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C55;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C56;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C57;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C58;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
|
||||
C59;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
|
||||
C60;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C61;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C62;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
|
||||
C63;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C64;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C65;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C66;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C67;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
|
||||
C68;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C69;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C70;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
|
||||
C71;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C72;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402
|
||||
C73;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C74;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402
|
||||
C75;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C76;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402
|
||||
C77;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C78;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402
|
||||
C79;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C80;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402
|
||||
C81;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C82;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402
|
||||
C83;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C84;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402
|
||||
C85;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402
|
||||
C86;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402
|
||||
C87;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C88;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C89;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C90;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
|
||||
C91;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C92;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C93;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C94;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402
|
||||
C95;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
|
||||
C96;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
|
||||
C97;330nF;Murata;GRM155R61A334KE15D;CAP CER 0.33UF 10V 10% X5R 0402
|
||||
C98;330nF;Murata;GRM155R61A334KE15D;CAP CER 0.33UF 10V 10% X5R 0402
|
||||
C99;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402
|
||||
C100;330nF;Murata;GRM155R61A334KE15D;CAP CER 0.33UF 10V 10% X5R 0402
|
||||
C101;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
|
||||
C102;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402
|
||||
C103;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
|
||||
C104;3pF;Murata;GRM1555C1H3R0CA01D;CAP CER 3PF 50V NP0 0402
|
||||
C105;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805
|
||||
C106;1uF;Taiyo Yuden;LMK105BJ105KV-F;CAP CER 1UF 10V 10% X5R 0402
|
||||
C107;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
|
||||
C108;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
|
||||
C109;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
|
||||
C110;22pF;Murata;GRM1555C1H220JA01D;CAP CER 22PF 50V 5% NP0 0402;DNP
|
||||
C111;3pF;Murata;GRM1555C1H3R0CA01D;CAP CER 3PF 50V NP0 0402
|
||||
C112;180pF;Murata;GRM1555C1H181JA01D;CAP CER 180PF 50V 5% NP0 0402
|
||||
C113;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C114;3.3nF;Murata;GRM155R71H332KA01D;CAP CER 3300PF 50V 10% X7R 0402
|
||||
C115;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C116;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
|
||||
C117;DNP;DNP
|
||||
C118;DNP;DNP
|
||||
C119;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C120;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C121;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C122;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C123;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C124;2.2uF;Taiyo Yuden;LMK105BJ225MV-F;CAP CER 2.2UF 10V 20% X5R 0402
|
||||
C125;33pF;Murata;GRM1555C1H330JZ01D;CAP CER 33PF 50V 5% NP0 0402
|
||||
C126;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805
|
||||
C127;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805
|
||||
C128;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C129;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C130;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C131;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C132;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C133;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C134;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C135;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C136;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C137;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C138;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C139;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C140;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C141;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C142;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C143;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805
|
||||
C144;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C145;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805
|
||||
C146;10uF;Murata;GRM21BR61A106KE19L;CAP CER 10UF 10V 10% X5R 0805
|
||||
C147;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C148;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C149;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C150;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C151;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C152;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C153;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C154;100nF;Murata;GRM155R61A104KA01D;CAP CER 0.1UF 10V 10% X5R 0402
|
||||
C155;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
|
||||
C156;47pF;Murata;GRM1555C1H470JZ01D;CAP CER 47PF 50V 5% NP0 0402
|
||||
C157;18pF;Murata;GRM1555C1H180JZ01D;CAP CER 18PF 50V 5% NP0 0402
|
||||
C158;18pF;Murata;GRM1555C1H180JZ01D;CAP CER 18PF 50V 5% NP0 0402
|
||||
C159;1uF;Murata;GRM155R61A105ME15D;CAP CER 1UF 10V 20% X5R 0402;DNP
|
||||
C160;100pF;Murata;GRM1555C1H101JZ01D;CAP CER 100PF 50V 5% NP0 0402
|
||||
C161;1uF;Taiyo Yuden;LMK105BJ105KV-F;CAP CER 1UF 10V 10% X5R 0402
|
||||
C162;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C163;10nF;Murata;GRM155R71C103KA01D;CAP CER 10000PF 16V 10% X7R 0402
|
||||
C164;DNP;DNP
|
||||
C165;DNP;DNP
|
||||
D1;GSG-DIODE-TVS-BI;Murata;LXES15AAA1-100;TVS DIODE ESD .05PF 15KV 0402
|
||||
D2;USBLED1;Everlight;QTLP601C4TR;LED GREEN STD BRIGHT 0603 SMD
|
||||
D3;USBLED0;Everlight;QTLP600CYTR;LED YLW SUPER BRIGHT 0606 SMD
|
||||
D4;LED1;Everlight;QTLP601C4TR;LED GREEN STD BRIGHT 0603 SMD
|
||||
D5;LED2;Everlight;QTLP600CYTR;LED YLW SUPER BRIGHT 0606 SMD
|
||||
D6;LED3;Everlight;QTLP601CRTR;LED RED STD BRIGHT 0603 SMD
|
||||
D7;VCCLED;Everlight;QTLP601C4TR;LED GREEN STD BRIGHT 0603 SMD
|
||||
D8;1V8LED;Everlight;QTLP600CYTR;LED YLW SUPER BRIGHT 0606 SMD
|
||||
FB1;FILTER;Murata;BLM21PG221SN1D;FERRITE CHIP 220 OHM 2000MA 0805
|
||||
FB2;FILTER;Murata;BLM21PG221SN1D;FERRITE CHIP 220 OHM 2000MA 0805
|
||||
J1;GSG-USB-MICRO-B;FCI;10103594-0001LF;CONN RCPT STD MICRO USB TYPE B
|
||||
J2;900MHZ-F-ANTENNA;DNP
|
||||
L1;DNP;DNP
|
||||
L2;1uH;Taiyo Yuden;BRL1608T1R0M;INDUCTR 1.0UH 650MA 20% 0603 SMD
|
||||
L3;1uH;Taiyo Yuden;BRL1608T1R0M;INDUCTR 1.0UH 650MA 20% 0603 SMD
|
||||
L4;DNP;DNP
|
||||
L5;1uH;Taiyo Yuden;BRL1608T1R0M;INDUCTR 1.0UH 650MA 20% 0603 SMD
|
||||
L6;DNP;DNP
|
||||
L7;6.2nH;Taiyo Yuden;HK10056N2S-T;INDUCTOR HIFREQ 6.2+/-0.3NH 0402
|
||||
L8;DNP;DNP
|
||||
L9;DNP;DNP
|
||||
L10;4u7;Taiyo Yuden;NRG4026T4R7M;INDUCTOR 4.7UH 1.6A 20% SMD
|
||||
L11;4u7;Taiyo Yuden;NRG4026T4R7M;INDUCTOR 4.7UH 1.6A 20% SMD
|
||||
L12;1uH;Taiyo Yuden;BRL1608T1R0M;INDUCTR 1.0UH 650MA 20% 0603 SMD
|
||||
L13;INDUCTOR;DNP
|
||||
L14;INDUCTOR;DNP
|
||||
P1;1V8;DNP
|
||||
P2;CLKOUT;TE Connectivity;2081233-1;CONN JACK SMA PCB VERT;DNP
|
||||
P3;GND;DNP
|
||||
P4;ANTENNA;TE Connectivity;2081233-1;CONN JACK SMA PCB VERT
|
||||
P5;WAKEUP;DNP
|
||||
P6;TRACECLK;DNP
|
||||
P7;CTIN_4;DNP
|
||||
P8;VCC;DNP
|
||||
P9;CTOUT_4;DNP
|
||||
P10;CTOUT_2;DNP
|
||||
P11;CTIN_2;DNP
|
||||
P12;U3_RXD;DNP
|
||||
P13;U3_TXD;DNP
|
||||
P14;XCVR_CLKOUT;DNP
|
||||
P15;INTR;DNP
|
||||
P16;CLKIN;TE Connectivity;2081233-1;CONN JACK SMA PCB VERT;DNP
|
||||
P17;CLKIN_JMP;DNP
|
||||
P18;OEB;DNP
|
||||
P19;SPIFI;DNP
|
||||
P20;GPIO;DNP
|
||||
P21;ANALOG;DNP
|
||||
P22;I2S;DNP
|
||||
P23;DBGEN;DNP
|
||||
P24;TRST;DNP
|
||||
P25;LPC_ISP;DNP
|
||||
P26;LPC_JTAG;DNP
|
||||
P27;CONN_3;DNP
|
||||
P28;SD;DNP
|
||||
P29;CPLD_JTAG;DNP
|
||||
P30;BANK2_AUX;DNP
|
||||
P31;BANK1_AUX;DNP
|
||||
P32;CONN_3;DNP
|
||||
P33;CONN_3;DNP
|
||||
P34;CONN_3;DNP
|
||||
P35;GCK0;DNP
|
||||
P36;VAA;DNP
|
||||
P37;SCL;DNP
|
||||
P38;SDA;DNP
|
||||
P39;SSP1_SCK;DNP
|
||||
P40;SSP1_MOSI;DNP
|
||||
P41;SSP1_MISO;DNP
|
||||
Q1;MOSFET_P;Fairchild;BSS84;MOSFET P-CH 50V 130MA SOT-23
|
||||
Q2;MOSFET_P;Fairchild;BSS84;MOSFET P-CH 50V 130MA SOT-23
|
||||
R1;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
|
||||
R2;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
|
||||
R3;22k;Panasonic;ERJ-2GEJ223X;RES 22K OHM 1/10W 5% 0402 SMD
|
||||
R4;51k;Stackpole;RMCF0402FT51K0;RES TF 51K OHM 1% 0.0625W 0402
|
||||
R5;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
|
||||
R6;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
|
||||
R7;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
|
||||
R8;1k;Stackpole;RMCF0402JT1K00;RES 1K OHM 1/16W 5% 0402 SMD
|
||||
R9;1k;Stackpole;RMCF0402JT1K00;RES 1K OHM 1/16W 5% 0402 SMD
|
||||
R10;1k;Stackpole;RMCF0402JT1K00;RES 1K OHM 1/16W 5% 0402 SMD
|
||||
R11;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R12;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R13;1k;Stackpole;RMCF0402JT1K00;RES 1K OHM 1/16W 5% 0402 SMD
|
||||
R14;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
|
||||
R15;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
|
||||
R16;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
|
||||
R17;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
|
||||
R18;47;DNP
|
||||
R19;47;DNP
|
||||
R20;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD
|
||||
R21;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD
|
||||
R22;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD
|
||||
R23;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD
|
||||
R24;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
|
||||
R25;475;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
|
||||
R26;475;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
|
||||
R27;1k8;Stackpole;RMCF0402JT1K80;RES TF 1.8K OHM 5% 1/16W 0402
|
||||
R28;1k8;Stackpole;RMCF0402JT1K80;RES TF 1.8K OHM 5% 1/16W 0402
|
||||
R29;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
|
||||
R30;0;DNP
|
||||
R31;0;DNP
|
||||
R32;0;DNP
|
||||
R33;0;DNP
|
||||
R34;0;DNP
|
||||
R35;0;DNP
|
||||
R36;0;DNP
|
||||
R37;0;DNP
|
||||
R38;0;DNP
|
||||
R39;0;DNP
|
||||
R40;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;DNP
|
||||
R41;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
|
||||
R42;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;DNP
|
||||
R43;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;DNP
|
||||
R44;0;DNP
|
||||
R45;DNP;DNP
|
||||
R46;162k;Stackpole;RMCF0402FT162K;RES TF 1/16W 162K OHM 1% 0402
|
||||
R47;330k;Stackpole;RMCF0402FT330K;RES TF 1/16W 330K OHM 1% 0402
|
||||
R48;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
|
||||
R49;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
|
||||
R50;DNP;DNP
|
||||
R51;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
|
||||
R52;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
|
||||
R53;DNP;DNP
|
||||
R54;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
|
||||
R55;162k;Stackpole;RMCF0402FT162K;RES TF 1/16W 162K OHM 1% 0402
|
||||
R56;715k;Stackpole;RMCF0402FT715K;RES TF 1/16W 715K OHM 1% 0402
|
||||
R57;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD
|
||||
R58;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD
|
||||
R59;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
|
||||
R60;0;DNP
|
||||
R61;0;DNP
|
||||
R62;0;Stackpole;RMCF0402ZT0R00;RES 0.0 OHM 1/16W 0402 SMD
|
||||
R63;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
|
||||
R64;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
|
||||
R65;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;DNP
|
||||
R66;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
|
||||
R67;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
|
||||
R68;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
|
||||
R69;12k;Rohm;MCR01MRTF1202;RES 12.0K OHM 1/16W 1% 0402 SMD
|
||||
R70;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
|
||||
R71;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
|
||||
R72;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
|
||||
R73;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
|
||||
R74;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
|
||||
R75;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
|
||||
R76;470;Stackpole;RMCF0402JT470R;RES TF 1/16W 470 OHM 5% 0402
|
||||
R77;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R78;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R79;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R80;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R81;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R82;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD;DNP
|
||||
R83;0;DNP
|
||||
R84;50;DNP
|
||||
R85;DNP;DNP
|
||||
R86;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R87;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R88;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R89;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R90;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R91;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R92;50;DNP
|
||||
R93;10k;Stackpole;RMCF0402JT10K0;RES 10K OHM 1/16W 5% 0402 SMD
|
||||
R94;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R96;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R97;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD;DNP
|
||||
R98;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R99;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R100;39;Stackpole;RMCF0402JT39R0;RES 39 OHM 1/16W 5% 0402 SMD
|
||||
R104;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
|
||||
R105;4k7;Stackpole;RMCF0402JT4K70;RES 4.7K OHM 1/16W 5% 0402 SMD
|
||||
T1;MIX_IN_BALUN;Anaren;B0310J50100AHF;Ultra Low Profile 0805 Balun 50 to 100 ohm Balanced
|
||||
T2;MIX_OUT_BALUN;Anaren;B0310J50100AHF;Ultra Low Profile 0805 Balun 50 to 100 ohm Balanced
|
||||
T3;RX_BALUN;Johanson Technology;2500BL14M100T;BALUN CERAMIC CHIP WIMAX 2.5GHZ
|
||||
T4;TX_BALUN;Johanson Technology;2500BL14M100T;BALUN CERAMIC CHIP WIMAX 2.5GHZ
|
||||
U1;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch
|
||||
U2;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch
|
||||
U3;RX_LOWPASS_FILTER;AVX;LP0603A1880ANTR;FILTER LOW PASS 1880MHZ 0603 SMD
|
||||
U4;RFFC5072;RFMD;RFFC5072TR7;WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6GHz MIXER
|
||||
U5;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch
|
||||
U6;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch
|
||||
U7;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch
|
||||
U8;RX_HIGHPASS_FILTER;TDK;DEA162400HT-8004B1;FILTER HIGHPASS WLAN&BLUETOOTH
|
||||
U9;SKY13317;Skyworks;SKY13317-373LF;20 MHz-6.0 GHz pHEMT GaAs SP3T Switch
|
||||
U10;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch
|
||||
U11;SKY13350;Skyworks;SKY13350-385LF;0.01-6.0 GHz GaAs SPDT Switch
|
||||
U12;SKY13317;Skyworks;SKY13317-373LF;20 MHz-6.0 GHz pHEMT GaAs SP3T Switch
|
||||
U13;MGA-81563;Avago;MGA-81563-TR1G;0.1-6 GHz 3 V, 14 dBm Amplifier
|
||||
U14;SKY13317;Skyworks;SKY13317-373LF;20 MHz-6.0 GHz pHEMT GaAs SP3T Switch
|
||||
U15;GSG-74HC04;Texas Instruments;SN74AHC04RGYR;IC HEX INVERTERS 14-QFN
|
||||
U16;GSG-74HC08;Texas Instruments;SN74AHC08RGYR;IC QUAD 2IN POS-AND GATE 14-QFN
|
||||
U17;MAX2837;Maxim;MAX2837ETM+;IC TXRX 2.3GHZ-2.7GHZ 48TQFN
|
||||
U18;MAX5864;Maxim;MAX5864ETM+;IC ANLG FRONT END 22MSPS 48-TQFN
|
||||
U19;SI5351C;Silicon Laboratories Inc;SI5351C-B-GM;IC CLK GENERATOR 160MHZ 20QFN
|
||||
U20;W25Q80BV;Winbond;W25Q80BVSSIG;IC FLASH 8MBIT 8SOIC
|
||||
U21;TPS62410;Texas Instruments;TPS62410DRCR;IC BUCK SYNC DUAL ADJ 0.8A 10SON
|
||||
U22;GSG-IP4220CZ6;NXP;IP4220CZ6,125;IC USB DUAL ESD PROTECT 6TSOP
|
||||
U23;LPC43XXFBD144;NXP;LPC4330FBD144,551;IC MCU 32BIT 144LQFP
|
||||
U24;GSG-XC2C64A-7VQG100C;Xilinx;XC2C64A-7VQG100C;IC CR-II CPLD 64MCELL 100-VQFP
|
||||
U25;MGA-81563;Avago;MGA-81563-TR1G;0.1-6 GHz 3 V, 14 dBm Amplifier
|
||||
U26;RF LDO;DNP
|
||||
X1;GSG-XTAL4PIN;AVX;CX3225GB25000D0HEQZ1;CRYSTAL 25.000MHZ 8PF SMD
|
||||
X2;MCU_XTAL;TXC;7V-12.000MAAE-T;CRYSTAL 12.000 MHZ 12PF SMD
|
||||
|
Can't render this file because it has a wrong number of fields in line 353.
|
@ -0,0 +1,19 @@
|
||||
order of copper layers:
|
||||
Copper 1: Front
|
||||
Copper 2: Inner3
|
||||
Copper 3: Inner2
|
||||
Copper 4: Back
|
||||
|
||||
PCB description: 4 layer PCB 0.062 in
|
||||
Copper 1 0.5 oz foil plated to approximately 0.0017 in
|
||||
Dielectric 1-2 0.0119 in
|
||||
Copper 2 1 oz foil (0.0014 in)
|
||||
Dielectric 2-3 0.0280 in
|
||||
Copper 3 1 oz foil (0.0014 in)
|
||||
Dielectric 3-4 0.0119 in
|
||||
Copper 4 0.5 oz foil plated to approximately 0.0017 in
|
||||
FR4 or similar substrate with Er=4.5 (+/- 0.1)
|
||||
double side solder mask black
|
||||
single side silkscreen white
|
||||
6 mil min trace width and
|
||||
6 mil min isolation
|
||||
@ -0,0 +1,257 @@
|
||||
G04 (created by PCBNEW (2013-01-23 BZR 3920)-stable) date Mon Jun 10 00:49:26 2013*
|
||||
%MOIN*%
|
||||
G04 Gerber Fmt 3.4, Leading zero omitted, Abs format*
|
||||
%FSLAX34Y34*%
|
||||
G01*
|
||||
G70*
|
||||
G90*
|
||||
G04 APERTURE LIST*
|
||||
%ADD10C,2.3622e-06*%
|
||||
%ADD11C,0.075*%
|
||||
%ADD12C,0.0691*%
|
||||
%ADD13C,0.0292*%
|
||||
%ADD14C,0.029*%
|
||||
%ADD15R,0.072X0.072*%
|
||||
%ADD16C,0.072*%
|
||||
%ADD17C,0.112*%
|
||||
%ADD18C,0.138*%
|
||||
%ADD19C,0.0306*%
|
||||
%ADD20R,0.054X0.054*%
|
||||
%ADD21C,0.054*%
|
||||
%ADD22C,0.035*%
|
||||
G04 APERTURE END LIST*
|
||||
G54D10*
|
||||
G54D11*
|
||||
X70583Y-22169D03*
|
||||
X68417Y-22169D03*
|
||||
G54D12*
|
||||
X70479Y-23339D03*
|
||||
X68521Y-23339D03*
|
||||
G54D13*
|
||||
X44202Y-47702D03*
|
||||
X43798Y-47702D03*
|
||||
X43798Y-47298D03*
|
||||
X44202Y-47298D03*
|
||||
X40202Y-47702D03*
|
||||
X39798Y-47702D03*
|
||||
X39798Y-47298D03*
|
||||
X40202Y-47298D03*
|
||||
G54D14*
|
||||
X51225Y-27025D03*
|
||||
X51225Y-26431D03*
|
||||
X51819Y-26431D03*
|
||||
X51819Y-27025D03*
|
||||
X51819Y-27619D03*
|
||||
X51225Y-27619D03*
|
||||
X50631Y-27619D03*
|
||||
X50631Y-27025D03*
|
||||
X50631Y-26431D03*
|
||||
G54D13*
|
||||
X38150Y-27200D03*
|
||||
X37717Y-27200D03*
|
||||
X37717Y-26767D03*
|
||||
X38150Y-26767D03*
|
||||
X38583Y-26767D03*
|
||||
X38583Y-27200D03*
|
||||
X38583Y-27633D03*
|
||||
X38150Y-27633D03*
|
||||
X37717Y-27633D03*
|
||||
X46300Y-31600D03*
|
||||
X46039Y-31339D03*
|
||||
X46561Y-31339D03*
|
||||
X46561Y-31861D03*
|
||||
X46039Y-31861D03*
|
||||
G54D15*
|
||||
X59500Y-29000D03*
|
||||
G54D16*
|
||||
X60500Y-29000D03*
|
||||
X59500Y-30000D03*
|
||||
X60500Y-30000D03*
|
||||
X59500Y-31000D03*
|
||||
X60500Y-31000D03*
|
||||
X59500Y-32000D03*
|
||||
X60500Y-32000D03*
|
||||
X59500Y-33000D03*
|
||||
X60500Y-33000D03*
|
||||
X59500Y-34000D03*
|
||||
X60500Y-34000D03*
|
||||
X59500Y-35000D03*
|
||||
X60500Y-35000D03*
|
||||
X59500Y-36000D03*
|
||||
X60500Y-36000D03*
|
||||
G54D15*
|
||||
X66500Y-48500D03*
|
||||
G54D16*
|
||||
X66500Y-49500D03*
|
||||
X65500Y-48500D03*
|
||||
X65500Y-49500D03*
|
||||
X64500Y-48500D03*
|
||||
X64500Y-49500D03*
|
||||
X63500Y-48500D03*
|
||||
X63500Y-49500D03*
|
||||
X62500Y-48500D03*
|
||||
X62500Y-49500D03*
|
||||
X61500Y-48500D03*
|
||||
X61500Y-49500D03*
|
||||
G54D15*
|
||||
X78500Y-43500D03*
|
||||
G54D16*
|
||||
X77500Y-43500D03*
|
||||
X78500Y-42500D03*
|
||||
X77500Y-42500D03*
|
||||
X78500Y-41500D03*
|
||||
X77500Y-41500D03*
|
||||
X78500Y-40500D03*
|
||||
X77500Y-40500D03*
|
||||
X78500Y-39500D03*
|
||||
X77500Y-39500D03*
|
||||
X78500Y-38500D03*
|
||||
X77500Y-38500D03*
|
||||
G54D15*
|
||||
X78500Y-35500D03*
|
||||
G54D16*
|
||||
X77500Y-35500D03*
|
||||
X78500Y-34500D03*
|
||||
X77500Y-34500D03*
|
||||
X78500Y-33500D03*
|
||||
X77500Y-33500D03*
|
||||
X78500Y-32500D03*
|
||||
X77500Y-32500D03*
|
||||
X78500Y-31500D03*
|
||||
X77500Y-31500D03*
|
||||
G54D15*
|
||||
X50500Y-49500D03*
|
||||
G54D16*
|
||||
X50500Y-48500D03*
|
||||
X51500Y-49500D03*
|
||||
X51500Y-48500D03*
|
||||
X52500Y-49500D03*
|
||||
X52500Y-48500D03*
|
||||
X53500Y-49500D03*
|
||||
X53500Y-48500D03*
|
||||
X54500Y-49500D03*
|
||||
X54500Y-48500D03*
|
||||
G54D15*
|
||||
X76500Y-29000D03*
|
||||
G54D16*
|
||||
X76500Y-30000D03*
|
||||
X75500Y-29000D03*
|
||||
X75500Y-30000D03*
|
||||
X74500Y-29000D03*
|
||||
X74500Y-30000D03*
|
||||
X73500Y-29000D03*
|
||||
X73500Y-30000D03*
|
||||
G54D15*
|
||||
X78510Y-46500D03*
|
||||
G54D16*
|
||||
X78510Y-47500D03*
|
||||
X77510Y-46500D03*
|
||||
X77510Y-47500D03*
|
||||
X76510Y-46500D03*
|
||||
X76510Y-47500D03*
|
||||
G54D15*
|
||||
X69500Y-49500D03*
|
||||
G54D16*
|
||||
X70500Y-49500D03*
|
||||
X71500Y-49500D03*
|
||||
X72500Y-49500D03*
|
||||
X73500Y-49500D03*
|
||||
X74500Y-49500D03*
|
||||
G54D15*
|
||||
X47500Y-44500D03*
|
||||
G54D16*
|
||||
X47500Y-45500D03*
|
||||
X47500Y-46500D03*
|
||||
X47500Y-47500D03*
|
||||
X47500Y-48500D03*
|
||||
X47500Y-49500D03*
|
||||
G54D15*
|
||||
X63500Y-24000D03*
|
||||
G54D16*
|
||||
X64500Y-24000D03*
|
||||
X65500Y-24000D03*
|
||||
G54D15*
|
||||
X63500Y-23000D03*
|
||||
G54D16*
|
||||
X64500Y-23000D03*
|
||||
X65500Y-23000D03*
|
||||
G54D15*
|
||||
X63500Y-25000D03*
|
||||
G54D16*
|
||||
X64500Y-25000D03*
|
||||
X65500Y-25000D03*
|
||||
G54D15*
|
||||
X63500Y-26000D03*
|
||||
G54D16*
|
||||
X64500Y-26000D03*
|
||||
X65500Y-26000D03*
|
||||
G54D15*
|
||||
X67500Y-26000D03*
|
||||
G54D16*
|
||||
X67500Y-25000D03*
|
||||
G54D17*
|
||||
X43500Y-36500D03*
|
||||
X42500Y-37500D03*
|
||||
X44500Y-37500D03*
|
||||
X44500Y-35500D03*
|
||||
X42500Y-35500D03*
|
||||
X35000Y-44500D03*
|
||||
X36000Y-43500D03*
|
||||
X34000Y-43500D03*
|
||||
X34000Y-45500D03*
|
||||
X36000Y-45500D03*
|
||||
X43500Y-42500D03*
|
||||
X42500Y-43500D03*
|
||||
X44500Y-43500D03*
|
||||
X44500Y-41500D03*
|
||||
X42500Y-41500D03*
|
||||
G54D15*
|
||||
X54500Y-24000D03*
|
||||
G54D16*
|
||||
X54500Y-23000D03*
|
||||
G54D15*
|
||||
X77500Y-24000D03*
|
||||
G54D16*
|
||||
X77500Y-23000D03*
|
||||
G54D15*
|
||||
X77500Y-27000D03*
|
||||
G54D16*
|
||||
X77500Y-26000D03*
|
||||
G54D15*
|
||||
X42500Y-33500D03*
|
||||
G54D16*
|
||||
X43500Y-33500D03*
|
||||
G54D18*
|
||||
X26075Y-23075D03*
|
||||
X80925Y-23075D03*
|
||||
X80925Y-48925D03*
|
||||
X26075Y-48925D03*
|
||||
G54D19*
|
||||
X52575Y-34275D03*
|
||||
X52575Y-33625D03*
|
||||
X53225Y-33625D03*
|
||||
X53225Y-34275D03*
|
||||
X53225Y-34925D03*
|
||||
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y="0"
|
||||
sodipodi:role="line"
|
||||
id="tspan3386">Up to 22MHz</tspan></text>
|
||||
</g><path
|
||||
d="m 457.6,443.7 c 0,12.7 16.9,25.4 33.8,25.4 l 220.5,0 c 16.9,0 33.9,-12.7 33.9,-25.4 l 0,-165.2 c 0,-12.7 -17,-25.4 -33.9,-25.4 l -220.5,0 c -16.9,0 -33.8,12.7 -33.8,25.4 l 0,165.2 z"
|
||||
style="fill:#99ccff;fill-opacity:1;fill-rule:evenodd;stroke:none"
|
||||
id="path3388" /><g
|
||||
id="g3390"><path
|
||||
d="m 457.6,443.7 c 0,12.7 16.9,25.4 33.8,25.4 l 220.5,0 c 16.9,0 33.9,-12.7 33.9,-25.4 l 0,-165.2 c 0,-12.7 -17,-25.4 -33.9,-25.4 l -220.5,0 c -16.9,0 -33.8,12.7 -33.8,25.4 l 0,165.2 z"
|
||||
style="fill:none;stroke:none"
|
||||
id="path3392" /></g><g
|
||||
id="g3394"><path
|
||||
d="m 457.6,469.1 0,0 z"
|
||||
style="fill:none;stroke:none"
|
||||
id="path3396" /></g><g
|
||||
id="g3398"><path
|
||||
d="m 745.8,253.1 0,0 z"
|
||||
style="fill:none;stroke:none"
|
||||
id="path3400" /></g><g
|
||||
id="g3402"><text
|
||||
transform="matrix(1,0,0,-1,545.7,376)"
|
||||
id="text3404"><tspan
|
||||
style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-family:Arial;font-variant:normal;font-weight:900;font-size:48;writing-mode:lr;-inkscape-font-specification:Arial-Black"
|
||||
x="0 39.888 77.184"
|
||||
y="0"
|
||||
sodipodi:role="line"
|
||||
id="tspan3406">NXP</tspan></text>
|
||||
</g><g
|
||||
id="g3408"><text
|
||||
transform="matrix(1,0,0,-1,485.5,308.3)"
|
||||
id="text3410"><tspan
|
||||
style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-family:Arial;font-variant:normal;font-weight:900;font-size:48;writing-mode:lr;-inkscape-font-specification:Arial-Black"
|
||||
x="0 32.064 66.72 104.016 135.984 168.048 200.016"
|
||||
y="0"
|
||||
sodipodi:role="line"
|
||||
id="tspan3412">LPC43xx</tspan></text>
|
||||
</g><g
|
||||
id="g3414"><path
|
||||
d="m 429.9,361.1 -39.4,0"
|
||||
style="fill:none;stroke:#000000;stroke-opacity:1;stroke-width:7.07499;stroke-linecap:butt;stroke-linejoin:round;stroke-miterlimit:10;stroke-dasharray:none"
|
||||
id="path3416" /></g><path
|
||||
d="m 457.6,361.1 -28.9,9.6 0,-19.3 28.9,9.7 z"
|
||||
style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:none"
|
||||
id="path3418" /><path
|
||||
d="m 362.8,361.1 28.9,-9.7 0,19.3 -28.9,-9.6 z"
|
||||
style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:none"
|
||||
id="path3420" /><text
|
||||
transform="matrix(1,0,0,-1,49,181.9)"
|
||||
id="text3422"><tspan
|
||||
style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-family:Arial;font-variant:normal;font-weight:900;font-size:48;writing-mode:lr;-inkscape-font-specification:Arial-Black"
|
||||
x="0 45.264 77.328 109.296 125.28 173.28 205.248 253.248 269.232 301.2 333.264 378.528 418.512 445.104 461.088 498.384 535.68 572.976 586.32 621.504 657.984 695.28"
|
||||
y="0"
|
||||
sodipodi:role="line"
|
||||
id="tspan3424">Maximum 20MHz ADC/DAC </tspan></text>
|
||||
<text
|
||||
transform="matrix(1,0,0,-1,142.3,114.2)"
|
||||
id="text3426"><tspan
|
||||
style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-family:Arial;font-variant:normal;font-weight:900;font-size:48;writing-mode:lr;-inkscape-font-specification:Arial-Black"
|
||||
x="0 15.888 31.872 79.872 95.76 117.12 149.088 181.152 197.136 229.104 258.384 274.272 314.256 348.912 386.208 418.176 434.16 474.144"
|
||||
y="0"
|
||||
sodipodi:role="line"
|
||||
id="tspan3428">limited by USB2 HS</tspan></text>
|
||||
<text
|
||||
transform="matrix(1,0,0,-1,192.5,46.5)"
|
||||
id="text3430"><tspan
|
||||
style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:none;font-family:Arial;font-variant:normal;font-weight:900;font-size:48;writing-mode:lr;-inkscape-font-specification:Arial-Black"
|
||||
x="0 18.672 51.216 83.184 115.152 147.216 168.48 184.464 216.432 248.496 293.76 309.744 347.04 360.336 389.616"
|
||||
y="0"
|
||||
sodipodi:role="line"
|
||||
id="tspan3432">(about 40MiB/s)</tspan></text>
|
||||
</g></g><g
|
||||
id="g3434"><g
|
||||
id="g3436" /><g
|
||||
id="g3442"><g
|
||||
clip-path="url(#clipPath3438)"
|
||||
opacity="0.5"
|
||||
id="g3444" /></g></g></g></svg>
|
||||
|
After Width: | Height: | Size: 9.5 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 132 KiB |
File diff suppressed because one or more lines are too long
|
After Width: | Height: | Size: 62 KiB |
BIN
SoftwareDefined/HackRF/hackrf-2021.03.1/firmware-bin/hackrf_jawbreaker_usb.bin
Executable file
BIN
SoftwareDefined/HackRF/hackrf-2021.03.1/firmware-bin/hackrf_jawbreaker_usb.bin
Executable file
Binary file not shown.
Binary file not shown.
BIN
SoftwareDefined/HackRF/hackrf-2021.03.1/firmware-bin/hackrf_one_usb.bin
Executable file
BIN
SoftwareDefined/HackRF/hackrf-2021.03.1/firmware-bin/hackrf_one_usb.bin
Executable file
Binary file not shown.
Binary file not shown.
BIN
SoftwareDefined/HackRF/hackrf-2021.03.1/firmware-bin/hackrf_rad1o_usb.bin
Executable file
BIN
SoftwareDefined/HackRF/hackrf-2021.03.1/firmware-bin/hackrf_rad1o_usb.bin
Executable file
Binary file not shown.
Binary file not shown.
@ -0,0 +1,29 @@
|
||||
# Copyright 2012 Jared Boone <jared@sharebrained.com>
|
||||
#
|
||||
# This file is part of HackRF.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; see the file COPYING. If not, write to
|
||||
# the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
# Boston, MA 02110-1301, USA.
|
||||
#
|
||||
|
||||
# Top directory CMake project for HackRF firmware
|
||||
|
||||
cmake_minimum_required(VERSION 3.1.3)
|
||||
set(CMAKE_TOOLCHAIN_FILE toolchain-arm-cortex-m.cmake)
|
||||
|
||||
project (hackrf_firmware_all C)
|
||||
|
||||
add_subdirectory(blinky)
|
||||
add_subdirectory(hackrf_usb)
|
||||
50
SoftwareDefined/HackRF/hackrf-2021.03.1/firmware/README
Normal file
50
SoftwareDefined/HackRF/hackrf-2021.03.1/firmware/README
Normal file
@ -0,0 +1,50 @@
|
||||
The primary firmware source code for USB HackRF devices is hackrf_usb. Most of
|
||||
the other directories contain firmware source code for test and development.
|
||||
The common directory contains source code shared by multiple HackRF firmware
|
||||
projects. The cpld directory contains HDL source for the CPLD.
|
||||
|
||||
|
||||
The firmware is set up for compilation with the GCC toolchain available here:
|
||||
|
||||
https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads
|
||||
|
||||
Required dependency:
|
||||
|
||||
https://github.com/mossmann/libopencm3
|
||||
|
||||
If you are using git, the preferred way to install libopencm3 is to use the
|
||||
submodule:
|
||||
|
||||
$ cd ..
|
||||
$ git submodule init
|
||||
$ git submodule update
|
||||
|
||||
To build and install a standard firmware image for HackRF One:
|
||||
|
||||
$ cd hackrf_usb
|
||||
$ mkdir build
|
||||
$ cd build
|
||||
$ cmake ..
|
||||
$ make
|
||||
$ hackrf_spiflash -w hackrf_usb.bin
|
||||
|
||||
If you have a Jawbreaker, add -DBOARD=JAWBREAKER to the cmake command.
|
||||
If you have a rad1o, use -DBOARD=RAD1O instead.
|
||||
|
||||
It is possible to use a USB Device Firmware Upgrade (DFU) method to load
|
||||
firmware into RAM. This is normally only required to recover a device that has
|
||||
had faulty firmware loaded, but it can also be useful for firmware developers.
|
||||
|
||||
For loading firmware into RAM with DFU you will need:
|
||||
|
||||
http://dfu-util.sourceforge.net/
|
||||
|
||||
To start up HackRF One in DFU mode, hold down the DFU button while powering it
|
||||
on or while pressing and releasing the RESET button. Release the DFU button
|
||||
after the 3V3 LED illuminates.
|
||||
|
||||
A .dfu file is built by default when building firmware. Alternatively you can
|
||||
use a known good .dfu file from a release package. Load the firmware into RAM
|
||||
with:
|
||||
|
||||
$ dfu-util --device 1fc9:000c --alt 0 --download hackrf_usb.dfu
|
||||
14
SoftwareDefined/HackRF/hackrf-2021.03.1/firmware/appveyor.sh
Normal file
14
SoftwareDefined/HackRF/hackrf-2021.03.1/firmware/appveyor.sh
Normal file
@ -0,0 +1,14 @@
|
||||
#!/bin/sh
|
||||
|
||||
/usr/bin/env python -m ensurepip
|
||||
/usr/bin/env python -m pip install pyyaml
|
||||
|
||||
cd firmware/libopencm3
|
||||
export SRCLIBDIR='c:\projects\hackrf\firmware\libopencm3\lib\'
|
||||
make lib/lpc43xx/m0
|
||||
make lib/lpc43xx/m4
|
||||
cd ..
|
||||
mkdir build-hackrf-one
|
||||
cd build-hackrf-one
|
||||
cmake -G "Unix Makefiles" ..
|
||||
make VERBOSE=1
|
||||
@ -0,0 +1,33 @@
|
||||
# Copyright 2012 Michael Ossmann <mike@ossmann.com>
|
||||
# Copyright 2012 Jared Boone <jared@sharebrained.com>
|
||||
#
|
||||
# This file is part of HackRF.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; see the file COPYING. If not, write to
|
||||
# the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
# Boston, MA 02110-1301, USA.
|
||||
#
|
||||
|
||||
cmake_minimum_required(VERSION 3.1.3)
|
||||
set(CMAKE_TOOLCHAIN_FILE ../toolchain-arm-cortex-m.cmake)
|
||||
|
||||
project(blinky C)
|
||||
|
||||
include(../hackrf-common.cmake)
|
||||
|
||||
set(SRC_M4
|
||||
blinky.c
|
||||
)
|
||||
|
||||
DeclareTargets()
|
||||
@ -0,0 +1 @@
|
||||
This is the simplest example firmware for HackRF. It flashes three LEDs.
|
||||
@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright 2010 - 2012 Michael Ossmann
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include "hackrf_core.h"
|
||||
|
||||
int main(void)
|
||||
{
|
||||
pin_setup();
|
||||
|
||||
/* enable all power supplies */
|
||||
enable_1v8_power();
|
||||
|
||||
/* Blink LED1/2/3 on the board. */
|
||||
while (1)
|
||||
{
|
||||
led_on(LED1);
|
||||
led_on(LED2);
|
||||
led_on(LED3);
|
||||
|
||||
delay(2000000);
|
||||
|
||||
led_off(LED1);
|
||||
led_off(LED2);
|
||||
led_off(LED3);
|
||||
|
||||
delay(2000000);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright 2012 Michael Ossmann <mike@ossmann.com>
|
||||
* Copyright 2012 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
/* Linker script for HackRF One (LPC4320, 1M SPI flash, 200K SRAM). */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* rom is really the shadow region that points to SPI flash or elsewhere */
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 96K
|
||||
ram_local1 (rwx) : ORIGIN = 0x10000000, LENGTH = 96K
|
||||
ram_local2 (rwx) : ORIGIN = 0x10080000, LENGTH = 32K
|
||||
ram_sleep (rwx) : ORIGIN = 0x10088000, LENGTH = 8K
|
||||
}
|
||||
|
||||
INCLUDE LPC43xx_M4_memory.ld
|
||||
@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright 2012 Michael Ossmann <mike@ossmann.com>
|
||||
* Copyright 2012 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
/* Linker script for Rad1o badge - (LPC4330, 1M SPI flash, 264K SRAM). */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* rom is really the shadow region that points to SPI flash or elsewhere */
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 128K
|
||||
ram_local1 (rwx) : ORIGIN = 0x10000000, LENGTH = 128K
|
||||
ram_local2 (rwx) : ORIGIN = 0x10080000, LENGTH = 64K
|
||||
ram_sleep (rwx) : ORIGIN = 0x10090000, LENGTH = 8K
|
||||
}
|
||||
|
||||
INCLUDE LPC43xx_M4_memory.ld
|
||||
@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright 2012 Michael Ossmann <mike@ossmann.com>
|
||||
* Copyright 2012 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ram (rwx) : ORIGIN = 0x00000000, LENGTH = 28K
|
||||
}
|
||||
@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright 2012 Michael Ossmann <mike@ossmann.com>
|
||||
* Copyright 2012 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text : {
|
||||
PROVIDE(__m0_start__ = .);
|
||||
KEEP(*(.m0_bin*));
|
||||
. = ALIGN(4);
|
||||
PROVIDE(__m0_end__ = .);
|
||||
} >rom
|
||||
}
|
||||
@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright 2012 Michael Ossmann <mike@ossmann.com>
|
||||
* Copyright 2012 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Physical address in Flash used to copy Code from Flash to RAM */
|
||||
rom_flash (rx) : ORIGIN = 0x80000000, LENGTH = 1M
|
||||
ram_m0 (rwx) : ORIGIN = 0x20000000, LENGTH = 28K
|
||||
ram_shared (rwx) : ORIGIN = 0x20007000, LENGTH = 4K
|
||||
ram_usb (rwx) : ORIGIN = 0x20008000, LENGTH = 32K
|
||||
/* ram_usb: USB buffer. Straddles two blocks of RAM
|
||||
* to get performance benefit of having two USB buffers addressable
|
||||
* simultaneously (on two different buses of the AHB multilayer matrix)
|
||||
*/
|
||||
}
|
||||
|
||||
usb_bulk_buffer = ORIGIN(ram_usb);
|
||||
usb_bulk_buffer_offset = ORIGIN(ram_shared);
|
||||
usb_bulk_buffer_tx = ORIGIN(ram_shared)+4;
|
||||
PROVIDE(__ram_m0_start__ = ORIGIN(ram_m0));
|
||||
@ -0,0 +1,2 @@
|
||||
This directory contains things shared by multiple HackRF firmware
|
||||
implementations.
|
||||
@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright 2012 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include "bitband.h"
|
||||
|
||||
volatile uint32_t* peripheral_bitband_address(volatile void* const address, const uint_fast8_t bit_number) {
|
||||
const uint32_t bit_band_base = 0x42000000;
|
||||
const uint32_t byte_offset = (uint32_t)address - 0x40000000;
|
||||
const uint32_t bit_word_offset = (byte_offset * 32) + (bit_number * 4);
|
||||
const uint32_t bit_word_address = bit_band_base + bit_word_offset;
|
||||
return (volatile uint32_t*)bit_word_address;
|
||||
}
|
||||
|
||||
void peripheral_bitband_set(volatile void* const peripheral_address, const uint_fast8_t bit_number) {
|
||||
volatile uint32_t* const bitband_address = peripheral_bitband_address(peripheral_address, bit_number);
|
||||
*bitband_address = 1;
|
||||
}
|
||||
|
||||
void peripheral_bitband_clear(volatile void* const peripheral_address, const uint_fast8_t bit_number) {
|
||||
volatile uint32_t* const bitband_address = peripheral_bitband_address(peripheral_address, bit_number);
|
||||
*bitband_address = 0;
|
||||
}
|
||||
|
||||
uint32_t peripheral_bitband_get(volatile void* const peripheral_address, const uint_fast8_t bit_number) {
|
||||
volatile uint32_t* const bitband_address = peripheral_bitband_address(peripheral_address, bit_number);
|
||||
return *bitband_address;
|
||||
}
|
||||
@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright 2012 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __BITBAND_H__
|
||||
#define __BITBAND_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
volatile uint32_t* peripheral_bitband_address(volatile void* const address, const uint_fast8_t bit_number);
|
||||
void peripheral_bitband_set(volatile void* const peripheral_address, const uint_fast8_t bit_number);
|
||||
void peripheral_bitband_clear(volatile void* const peripheral_address, const uint_fast8_t bit_number);
|
||||
uint32_t peripheral_bitband_get(volatile void* const peripheral_address, const uint_fast8_t bit_number);
|
||||
|
||||
#endif//__BITBAND_H__
|
||||
@ -0,0 +1,101 @@
|
||||
/*
|
||||
* Copyright 2013 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include "cpld_jtag.h"
|
||||
#include "hackrf_core.h"
|
||||
#include "xapp058/micro.h"
|
||||
#include <libopencm3/lpc43xx/scu.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static refill_buffer_cb refill_buffer;
|
||||
static uint32_t xsvf_buffer_len, xsvf_pos;
|
||||
static unsigned char* xsvf_buffer;
|
||||
|
||||
void cpld_jtag_take(jtag_t* const jtag) {
|
||||
const jtag_gpio_t* const gpio = jtag->gpio;
|
||||
|
||||
/* Set initial GPIO state to the voltages of the internal or external pull-ups/downs,
|
||||
* to avoid any glitches.
|
||||
*/
|
||||
#ifdef HACKRF_ONE
|
||||
gpio_set(gpio->gpio_pp_tms);
|
||||
#endif
|
||||
gpio_set(gpio->gpio_tms);
|
||||
gpio_set(gpio->gpio_tdi);
|
||||
gpio_clear(gpio->gpio_tck);
|
||||
|
||||
#ifdef HACKRF_ONE
|
||||
/* Do not drive PortaPack-specific TMS pin initially, just to be cautious. */
|
||||
gpio_input(gpio->gpio_pp_tms);
|
||||
gpio_input(gpio->gpio_pp_tdo);
|
||||
#endif
|
||||
gpio_output(gpio->gpio_tms);
|
||||
gpio_output(gpio->gpio_tdi);
|
||||
gpio_output(gpio->gpio_tck);
|
||||
gpio_input(gpio->gpio_tdo);
|
||||
}
|
||||
|
||||
void cpld_jtag_release(jtag_t* const jtag) {
|
||||
const jtag_gpio_t* const gpio = jtag->gpio;
|
||||
|
||||
/* Make all pins inputs when JTAG interface not active.
|
||||
* Let the pull-ups/downs do the work.
|
||||
*/
|
||||
#ifdef HACKRF_ONE
|
||||
/* Do not drive PortaPack-specific pins, initially, just to be cautious. */
|
||||
gpio_input(gpio->gpio_pp_tms);
|
||||
gpio_input(gpio->gpio_pp_tdo);
|
||||
#endif
|
||||
gpio_input(gpio->gpio_tms);
|
||||
gpio_input(gpio->gpio_tdi);
|
||||
gpio_input(gpio->gpio_tck);
|
||||
gpio_input(gpio->gpio_tdo);
|
||||
}
|
||||
|
||||
/* return 0 if success else return error code see xsvfExecute() */
|
||||
int cpld_jtag_program(
|
||||
jtag_t* const jtag,
|
||||
const uint32_t buffer_length,
|
||||
unsigned char* const buffer,
|
||||
refill_buffer_cb refill
|
||||
) {
|
||||
int error;
|
||||
cpld_jtag_take(jtag);
|
||||
xsvf_buffer = buffer;
|
||||
xsvf_buffer_len = buffer_length;
|
||||
refill_buffer = refill;
|
||||
error = xsvfExecute(jtag->gpio);
|
||||
cpld_jtag_release(jtag);
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
/* this gets called by the XAPP058 code */
|
||||
unsigned char cpld_jtag_get_next_byte(void) {
|
||||
if (xsvf_pos == xsvf_buffer_len) {
|
||||
refill_buffer();
|
||||
xsvf_pos = 0;
|
||||
}
|
||||
|
||||
unsigned char byte = xsvf_buffer[xsvf_pos];
|
||||
xsvf_pos++;
|
||||
return byte;
|
||||
}
|
||||
@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright 2013 Michael Ossmann <mike@ossmann.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __CPLD_JTAG_H__
|
||||
#define __CPLD_JTAG_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "gpio.h"
|
||||
|
||||
typedef struct jtag_gpio_t {
|
||||
gpio_t gpio_tms;
|
||||
gpio_t gpio_tck;
|
||||
gpio_t gpio_tdi;
|
||||
gpio_t gpio_tdo;
|
||||
#ifdef HACKRF_ONE
|
||||
gpio_t gpio_pp_tms;
|
||||
gpio_t gpio_pp_tdo;
|
||||
#endif
|
||||
} jtag_gpio_t;
|
||||
|
||||
typedef struct jtag_t {
|
||||
jtag_gpio_t* const gpio;
|
||||
} jtag_t;
|
||||
|
||||
typedef void (*refill_buffer_cb)(void);
|
||||
|
||||
void cpld_jtag_take(jtag_t* const jtag);
|
||||
void cpld_jtag_release(jtag_t* const jtag);
|
||||
|
||||
/* Return 0 if success else return error code see xsvfExecute() see micro.h.
|
||||
*
|
||||
* We expect the buffer to be initially full of data. After the entire
|
||||
* contents of the buffer has been streamed to the CPLD the given
|
||||
* refill_buffer callback will be called. */
|
||||
int cpld_jtag_program(
|
||||
jtag_t* const jtag,
|
||||
const uint32_t buffer_length,
|
||||
unsigned char* const buffer,
|
||||
refill_buffer_cb refill
|
||||
);
|
||||
unsigned char cpld_jtag_get_next_byte(void);
|
||||
|
||||
#endif//__CPLD_JTAG_H__
|
||||
@ -0,0 +1,418 @@
|
||||
/*
|
||||
* Copyright 2019 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include "cpld_xc2c.h"
|
||||
|
||||
#include "crc.h"
|
||||
|
||||
#include <stddef.h>
|
||||
#include <string.h>
|
||||
|
||||
typedef enum {
|
||||
CPLD_XC2C_IR_INTEST = 0b00000010,
|
||||
CPLD_XC2C_IR_BYPASS = 0b11111111,
|
||||
CPLD_XC2C_IR_SAMPLE = 0b00000011,
|
||||
CPLD_XC2C_IR_EXTEST = 0b00000000,
|
||||
CPLD_XC2C_IR_IDCODE = 0b00000001,
|
||||
CPLD_XC2C_IR_USERCODE = 0b11111101,
|
||||
CPLD_XC2C_IR_HIGHZ = 0b11111100,
|
||||
CPLD_XC2C_IR_ISC_ENABLE_CLAMP = 0b11101001,
|
||||
CPLD_XC2C_IR_ISC_ENABLE_OTF = 0b11100100,
|
||||
CPLD_XC2C_IR_ISC_ENABLE = 0b11101000,
|
||||
CPLD_XC2C_IR_ISC_SRAM_READ = 0b11100111,
|
||||
CPLD_XC2C_IR_ISC_WRITE = 0b11100110,
|
||||
CPLD_XC2C_IR_ISC_ERASE = 0b11101101,
|
||||
CPLD_XC2C_IR_ISC_PROGRAM = 0b11101010,
|
||||
CPLD_XC2C_IR_ISC_READ = 0b11101110,
|
||||
CPLD_XC2C_IR_ISC_INIT = 0b11110000,
|
||||
CPLD_XC2C_IR_ISC_DISABLE = 0b11000000,
|
||||
CPLD_XC2C_IR_TEST_ENABLE = 0b00010001,
|
||||
CPLD_XC2C_IR_BULKPROG = 0b00010010,
|
||||
CPLD_XC2C_IR_ERASE_ALL = 0b00010100,
|
||||
CPLD_XC2C_IR_MVERIFY = 0b00010011,
|
||||
CPLD_XC2C_IR_TEST_DISABLE = 0b00010101,
|
||||
CPLD_XC2C_IR_STCTEST = 0b00010110,
|
||||
CPLD_XC2C_IR_ISC_NOOP = 0b11100000,
|
||||
} cpld_xc2c_ir_t;
|
||||
|
||||
static bool cpld_xc2c_jtag_clock(const jtag_t* const jtag, const uint32_t tms, const uint32_t tdi) {
|
||||
// 8 ns TMS/TDI to TCK setup
|
||||
gpio_write(jtag->gpio->gpio_tdi, tdi);
|
||||
gpio_write(jtag->gpio->gpio_tms, tms);
|
||||
|
||||
// 20 ns TCK high time
|
||||
__asm__("nop");
|
||||
__asm__("nop");
|
||||
__asm__("nop");
|
||||
__asm__("nop");
|
||||
__asm__("nop");
|
||||
|
||||
gpio_clear(jtag->gpio->gpio_tck);
|
||||
|
||||
// 25 ns TCK falling edge to TDO valid
|
||||
// 20 ns TCK low time
|
||||
__asm__("nop");
|
||||
__asm__("nop");
|
||||
__asm__("nop");
|
||||
__asm__("nop");
|
||||
__asm__("nop");
|
||||
__asm__("nop");
|
||||
__asm__("nop");
|
||||
|
||||
gpio_set(jtag->gpio->gpio_tck);
|
||||
|
||||
// 15 ns TCK to TMS/TDI hold time
|
||||
__asm__("nop");
|
||||
__asm__("nop");
|
||||
__asm__("nop");
|
||||
__asm__("nop");
|
||||
|
||||
return gpio_read(jtag->gpio->gpio_tdo);
|
||||
}
|
||||
|
||||
static void cpld_xc2c_jtag_shift_ptr_tms(const jtag_t* const jtag, uint8_t* const tdi_tdo, const size_t start, const size_t end, const bool tms) {
|
||||
for(size_t i=start; i<end; i++) {
|
||||
const size_t byte_n = i >> 3;
|
||||
const size_t bit_n = i & 7;
|
||||
const uint32_t mask = (1U << bit_n);
|
||||
|
||||
const uint32_t tdo = cpld_xc2c_jtag_clock(jtag, tms, tdi_tdo[byte_n] & mask) ? 1 : 0;
|
||||
|
||||
tdi_tdo[byte_n] &= ~mask;
|
||||
tdi_tdo[byte_n] |= (tdo << bit_n);
|
||||
}
|
||||
}
|
||||
|
||||
static void cpld_xc2c_jtag_shift_ptr(const jtag_t* const jtag, uint8_t* const tdi_tdo, const size_t count) {
|
||||
if( count > 0 ) {
|
||||
cpld_xc2c_jtag_shift_ptr_tms(jtag, tdi_tdo, 0, count - 1, false);
|
||||
cpld_xc2c_jtag_shift_ptr_tms(jtag, tdi_tdo, count - 1, count, true);
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t cpld_xc2c_jtag_shift_u32(const jtag_t* const jtag, const uint32_t tms, const uint32_t tdi, const size_t count) {
|
||||
uint32_t tdo = 0;
|
||||
|
||||
for(size_t i=0; i<count; i++) {
|
||||
const uint32_t mask = (1U << i);
|
||||
tdo |= cpld_xc2c_jtag_clock(jtag, tms & mask, tdi & mask) << i;
|
||||
}
|
||||
|
||||
return tdo;
|
||||
}
|
||||
|
||||
static void cpld_xc2c_jtag_clocks(const jtag_t* const jtag, const size_t count) {
|
||||
for(size_t i=0; i<count; i++) {
|
||||
cpld_xc2c_jtag_clock(jtag, 0, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void cpld_xc2c_jtag_pause(const jtag_t* const jtag, const size_t count) {
|
||||
for(size_t i=0; i<count; i++) {
|
||||
cpld_xc2c_jtag_clock(jtag, (i == (count - 1)), 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void cpld_xc2c_jtag_shift_dr_ir(const jtag_t* const jtag, uint8_t* const tdi_tdo, const size_t bit_count, const size_t pause_count) {
|
||||
/* Run-Test/Idle or Select-DR-Scan -> Shift-DR or Shift-IR */
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0b001, 0b000, 3);
|
||||
/* Shift-[DI]R -> Exit1-[DI]R */
|
||||
cpld_xc2c_jtag_shift_ptr(jtag, tdi_tdo, bit_count);
|
||||
if( pause_count ) {
|
||||
/* Exit1-[DI]R -> Pause-[DI]R */
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0b0, 0, 1);
|
||||
/* Pause-[DI]R -> Exit2-[DI]R */
|
||||
cpld_xc2c_jtag_pause(jtag, pause_count);
|
||||
}
|
||||
/* Exit1-[DI]R or Exit2-[DI]R -> Run-Test/Idle */
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0b01, 0, 2);
|
||||
}
|
||||
|
||||
static void cpld_xc2c_jtag_shift_dr(const jtag_t* const jtag, uint8_t* const tdi_tdo, const size_t bit_count, const size_t pause_count) {
|
||||
cpld_xc2c_jtag_shift_dr_ir(jtag, tdi_tdo, bit_count, pause_count);
|
||||
}
|
||||
|
||||
static uint8_t cpld_xc2c_jtag_shift_ir_pause(const jtag_t* const jtag, const cpld_xc2c_ir_t ir, const size_t pause_count) {
|
||||
/* Run-Test/Idle -> Select-DR-Scan */
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0b1, 0b0, 1);
|
||||
uint8_t value = ir;
|
||||
cpld_xc2c_jtag_shift_dr_ir(jtag, &value, 8, pause_count);
|
||||
return value;
|
||||
}
|
||||
|
||||
static uint8_t cpld_xc2c_jtag_shift_ir(const jtag_t* const jtag, const cpld_xc2c_ir_t ir) {
|
||||
return cpld_xc2c_jtag_shift_ir_pause(jtag, ir, 0);
|
||||
}
|
||||
|
||||
static void cpld_xc2c_jtag_reset(const jtag_t* const jtag) {
|
||||
/* Five TMS=1 to reach Test-Logic-Reset from any point in the TAP state diagram.
|
||||
*/
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0b11111, 0, 5);
|
||||
}
|
||||
|
||||
static void cpld_xc2c_jtag_reset_and_idle(const jtag_t* const jtag) {
|
||||
/* Five TMS=1 to reach Test-Logic-Reset from any point in the TAP state diagram.
|
||||
* One TMS=0 to move from Test-Logic-Reset to Run-Test-Idle.
|
||||
*/
|
||||
cpld_xc2c_jtag_reset(jtag);
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0, 0, 1);
|
||||
}
|
||||
|
||||
static uint32_t cpld_xc2c_jtag_idcode(const jtag_t* const jtag) {
|
||||
/* Enter and end at Run-Test-Idle state. */
|
||||
cpld_xc2c_jtag_shift_ir(jtag, CPLD_XC2C_IR_IDCODE);
|
||||
uint32_t result = 0;
|
||||
cpld_xc2c_jtag_shift_dr(jtag, (uint8_t*)&result, 32, 0);
|
||||
return result;
|
||||
}
|
||||
|
||||
static bool cpld_xc2c64a_jtag_idcode_ok(const jtag_t* const jtag) {
|
||||
return ((cpld_xc2c_jtag_idcode(jtag) ^ 0xf6e5f093) & 0x0fff8fff) == 0;
|
||||
}
|
||||
|
||||
static void cpld_xc2c_jtag_conld(const jtag_t* const jtag) {
|
||||
cpld_xc2c_jtag_shift_ir(jtag, CPLD_XC2C_IR_ISC_DISABLE);
|
||||
cpld_xc2c_jtag_clocks(jtag, 100);
|
||||
}
|
||||
|
||||
static void cpld_xc2c_jtag_enable(const jtag_t* const jtag) {
|
||||
cpld_xc2c_jtag_shift_ir(jtag, CPLD_XC2C_IR_ISC_ENABLE);
|
||||
cpld_xc2c_jtag_clocks(jtag, 800);
|
||||
}
|
||||
|
||||
static void cpld_xc2c_jtag_disable(const jtag_t* const jtag) {
|
||||
cpld_xc2c_jtag_shift_ir(jtag, CPLD_XC2C_IR_ISC_DISABLE);
|
||||
cpld_xc2c_jtag_clocks(jtag, 100);
|
||||
}
|
||||
|
||||
static void cpld_xc2c_jtag_sram_write(const jtag_t* const jtag) {
|
||||
cpld_xc2c_jtag_shift_ir(jtag, CPLD_XC2C_IR_ISC_WRITE);
|
||||
}
|
||||
|
||||
static void cpld_xc2c_jtag_sram_read(const jtag_t* const jtag) {
|
||||
cpld_xc2c_jtag_shift_ir(jtag, CPLD_XC2C_IR_ISC_SRAM_READ);
|
||||
}
|
||||
|
||||
static uint32_t cpld_xc2c_jtag_bypass(const jtag_t* const jtag, const bool shift_dr) {
|
||||
const uint8_t result = cpld_xc2c_jtag_shift_ir(jtag, CPLD_XC2C_IR_BYPASS);
|
||||
if( shift_dr ) {
|
||||
uint8_t dr = 0;
|
||||
cpld_xc2c_jtag_shift_dr(jtag, &dr, 1, 0);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
static bool cpld_xc2c_jtag_read_write_protect(const jtag_t* const jtag) {
|
||||
/* Enter and end at Run-Test-Idle state. */
|
||||
return ((cpld_xc2c_jtag_bypass(jtag, false) ^ 0x01) & 0x03) == 0;
|
||||
}
|
||||
|
||||
static bool cpld_xc2c_jtag_is_done(const jtag_t* const jtag) {
|
||||
return ((cpld_xc2c_jtag_bypass(jtag, false) ^ 0x05) & 0x07) == 0;
|
||||
}
|
||||
|
||||
static void cpld_xc2c_jtag_init_special(const jtag_t* const jtag) {
|
||||
cpld_xc2c_jtag_shift_ir(jtag, CPLD_XC2C_IR_ISC_INIT);
|
||||
cpld_xc2c_jtag_clocks(jtag, 20);
|
||||
/* Run-Test/Idle -> Shift-IR */
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0b0011, 0b0000, 4);
|
||||
/* Shift-IR: 0xf0 -> Exit1-IR */
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0x80, CPLD_XC2C_IR_ISC_INIT, 8);
|
||||
/* Exit1-IR -> Pause-IR */
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0b0, 0, 1);
|
||||
/* Pause-IR -> Exit2-IR -> Update-IR -> Select-DR-Scan -> Capture-DR -> Exit1-DR -> Update-DR -> Run-Test/Idle */
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0b0110111, 0, 7);
|
||||
cpld_xc2c_jtag_clocks(jtag, 800);
|
||||
}
|
||||
|
||||
static void cpld_xc2c_jtag_read(const jtag_t* const jtag) {
|
||||
cpld_xc2c_jtag_shift_ir_pause(jtag, CPLD_XC2C_IR_ISC_READ, 1);
|
||||
}
|
||||
|
||||
static void cpld_xc2c64a_jtag_read_row(const jtag_t* const jtag, uint8_t address, uint8_t* const dr) {
|
||||
cpld_xc2c_jtag_shift_dr(jtag, &address, 7, 20);
|
||||
cpld_xc2c_jtag_clocks(jtag, 100);
|
||||
|
||||
/* Set array to all ones so we don't transmit memory contents over TDI, and if we're not
|
||||
* reading a full byte's worth of bits, the excess bits will be zero.
|
||||
*/
|
||||
memset(dr, 0xff, CPLD_XC2C64A_BYTES_IN_ROW);
|
||||
cpld_xc2c_jtag_shift_dr(jtag, dr, CPLD_XC2C64A_BITS_IN_ROW, 0);
|
||||
cpld_xc2c_jtag_clocks(jtag, 100);
|
||||
}
|
||||
|
||||
bool cpld_xc2c64a_jtag_checksum(
|
||||
const jtag_t* const jtag,
|
||||
const cpld_xc2c64a_verify_t* const verify,
|
||||
uint32_t* const crc_value
|
||||
) {
|
||||
cpld_xc2c_jtag_reset_and_idle(jtag);
|
||||
|
||||
if( cpld_xc2c64a_jtag_idcode_ok(jtag) && cpld_xc2c_jtag_read_write_protect(jtag) &&
|
||||
cpld_xc2c64a_jtag_idcode_ok(jtag) && cpld_xc2c_jtag_read_write_protect(jtag) ) {
|
||||
|
||||
cpld_xc2c_jtag_bypass(jtag, false);
|
||||
|
||||
cpld_xc2c_jtag_enable(jtag);
|
||||
cpld_xc2c_jtag_enable(jtag);
|
||||
cpld_xc2c_jtag_enable(jtag);
|
||||
|
||||
cpld_xc2c_jtag_read(jtag);
|
||||
|
||||
crc32_t crc;
|
||||
crc32_init(&crc);
|
||||
|
||||
uint8_t dr[CPLD_XC2C64A_BYTES_IN_ROW];
|
||||
for(size_t row=0; row<CPLD_XC2C64A_ROWS; row++) {
|
||||
const size_t address = cpld_hackrf_row_addresses.address[row];
|
||||
cpld_xc2c64a_jtag_read_row(jtag, address, dr);
|
||||
|
||||
const size_t mask_index = verify->mask_index[row];
|
||||
for(size_t i=0; i<CPLD_XC2C64A_BYTES_IN_ROW; i++) {
|
||||
dr[i] &= verify->mask[mask_index].value[i];
|
||||
}
|
||||
|
||||
/* Important checksum calculation NOTE:
|
||||
* Do checksum of all bits in row bytes, but ensure that invalid bits
|
||||
* are set to zero by masking. This subtlety just wasted several hours
|
||||
* of my life...
|
||||
*/
|
||||
crc32_update(&crc, dr, CPLD_XC2C64A_BYTES_IN_ROW);
|
||||
}
|
||||
|
||||
*crc_value = crc32_digest(&crc);
|
||||
|
||||
cpld_xc2c_jtag_init_special(jtag);
|
||||
cpld_xc2c_jtag_conld(jtag);
|
||||
|
||||
if( cpld_xc2c64a_jtag_idcode_ok(jtag) && cpld_xc2c_jtag_is_done(jtag) ) {
|
||||
cpld_xc2c_jtag_conld(jtag);
|
||||
cpld_xc2c_jtag_bypass(jtag, false);
|
||||
cpld_xc2c_jtag_bypass(jtag, true);
|
||||
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
cpld_xc2c_jtag_reset_and_idle(jtag);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static void cpld_xc2c64a_jtag_sram_write_row(const jtag_t* const jtag, uint8_t address, const uint8_t* const data) {
|
||||
uint8_t write[CPLD_XC2C64A_BYTES_IN_ROW];
|
||||
memcpy(&write[0], data, sizeof(write));
|
||||
|
||||
/* Update-IR or Run-Test/Idle -> Shift-DR */
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0b001, 0b000, 3);
|
||||
|
||||
/* Shift-DR -> Shift-DR */
|
||||
cpld_xc2c_jtag_shift_ptr_tms(jtag, &write[0], 0, CPLD_XC2C64A_BITS_IN_ROW, false);
|
||||
|
||||
/* Shift-DR -> Exit1-DR */
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0b1000000, address, 7);
|
||||
|
||||
/* Exit1-DR -> Update-DR -> Run-Test/Idle */
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0b01, 0b00, 2);
|
||||
}
|
||||
|
||||
static void cpld_xc2c64a_jtag_sram_read_row(const jtag_t* const jtag, uint8_t* const data, const uint8_t next_address) {
|
||||
/* Run-Test/Idle -> Shift-DR */
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0b001, 0b000, 3);
|
||||
|
||||
/* Shift-DR */
|
||||
cpld_xc2c_jtag_shift_ptr_tms(jtag, data, 0, CPLD_XC2C64A_BITS_IN_ROW, false);
|
||||
|
||||
/* Shift-DR -> Exit1-DR */
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0b1000000, next_address, 7);
|
||||
|
||||
/* Weird, non-IEEE1532 compliant path through TAP machine, described in Xilinx
|
||||
* Programmer Qualification Specification, applicable only to XC2C64/A.
|
||||
* Exit1-DR -> Pause-DR -> Exit2-DR -> Update-DR -> Run-Test/Idle
|
||||
*/
|
||||
cpld_xc2c_jtag_shift_u32(jtag, 0b0110, 0b0000, 4);
|
||||
}
|
||||
|
||||
static bool cpld_xc2c64a_jtag_sram_compare_row(const jtag_t* const jtag, const uint8_t* const expected, const uint8_t* const mask, const uint8_t next_address) {
|
||||
/* Run-Test/Idle -> Shift-DR */
|
||||
uint8_t read[CPLD_XC2C64A_BYTES_IN_ROW];
|
||||
memset(read, 0xff, sizeof(read));
|
||||
cpld_xc2c64a_jtag_sram_read_row(jtag, &read[0], next_address);
|
||||
|
||||
bool matched = true;
|
||||
if( (expected != NULL) && (mask != NULL) ) {
|
||||
for(size_t i=0; i<CPLD_XC2C64A_BYTES_IN_ROW; i++) {
|
||||
const uint8_t significant_differences = (read[i] ^ expected[i]) & mask[i];
|
||||
matched &= (significant_differences == 0);
|
||||
}
|
||||
}
|
||||
|
||||
return matched;
|
||||
}
|
||||
|
||||
void cpld_xc2c64a_jtag_sram_write(
|
||||
const jtag_t* const jtag,
|
||||
const cpld_xc2c64a_program_t* const program
|
||||
) {
|
||||
cpld_xc2c_jtag_reset_and_idle(jtag);
|
||||
cpld_xc2c_jtag_enable(jtag);
|
||||
|
||||
cpld_xc2c_jtag_sram_write(jtag);
|
||||
|
||||
for(size_t row=0; row<CPLD_XC2C64A_ROWS; row++) {
|
||||
const uint8_t address = cpld_hackrf_row_addresses.address[row];
|
||||
cpld_xc2c64a_jtag_sram_write_row(jtag, address, &program->row[row].data[0]);
|
||||
}
|
||||
|
||||
cpld_xc2c_jtag_disable(jtag);
|
||||
cpld_xc2c_jtag_bypass(jtag, false);
|
||||
cpld_xc2c_jtag_reset(jtag);
|
||||
}
|
||||
|
||||
bool cpld_xc2c64a_jtag_sram_verify(
|
||||
const jtag_t* const jtag,
|
||||
const cpld_xc2c64a_program_t* const program,
|
||||
const cpld_xc2c64a_verify_t* const verify
|
||||
) {
|
||||
cpld_xc2c_jtag_reset_and_idle(jtag);
|
||||
cpld_xc2c_jtag_enable(jtag);
|
||||
|
||||
cpld_xc2c_jtag_sram_read(jtag);
|
||||
|
||||
/* Tricky loop to read dummy row first, then first address, then loop back to get
|
||||
* the first row's data.
|
||||
*/
|
||||
bool matched = true;
|
||||
for(size_t address_row=0; address_row<=CPLD_XC2C64A_ROWS; address_row++) {
|
||||
const int data_row = (int)address_row - 1;
|
||||
const size_t mask_index = (data_row >= 0) ? verify->mask_index[data_row] : 0;
|
||||
const uint8_t* const expected = (data_row >= 0) ? &program->row[data_row].data[0] : NULL;
|
||||
const uint8_t* const mask = (data_row >= 0) ? &verify->mask[mask_index].value[0] : NULL;
|
||||
const uint8_t next_address = (address_row < CPLD_XC2C64A_ROWS) ? cpld_hackrf_row_addresses.address[address_row] : 0;
|
||||
matched &= cpld_xc2c64a_jtag_sram_compare_row(jtag, expected, mask, next_address);
|
||||
}
|
||||
|
||||
cpld_xc2c_jtag_disable(jtag);
|
||||
cpld_xc2c_jtag_bypass(jtag, false);
|
||||
cpld_xc2c_jtag_reset(jtag);
|
||||
|
||||
return matched;
|
||||
}
|
||||
@ -0,0 +1,75 @@
|
||||
/*
|
||||
* Copyright 2019 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __CPLD_XC2C_H__
|
||||
#define __CPLD_XC2C_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "cpld_jtag.h"
|
||||
|
||||
/* Xilinx CoolRunner II XC2C64A bitstream attributes */
|
||||
#define CPLD_XC2C64A_ROWS (98)
|
||||
#define CPLD_XC2C64A_BITS_IN_ROW (274)
|
||||
#define CPLD_XC2C64A_BYTES_IN_ROW ((CPLD_XC2C64A_BITS_IN_ROW + 7) / 8)
|
||||
|
||||
typedef struct {
|
||||
uint8_t data[CPLD_XC2C64A_BYTES_IN_ROW];
|
||||
} cpld_xc2c64a_row_data_t;
|
||||
|
||||
typedef struct {
|
||||
cpld_xc2c64a_row_data_t row[CPLD_XC2C64A_ROWS];
|
||||
} cpld_xc2c64a_program_t;
|
||||
|
||||
typedef struct {
|
||||
uint8_t value[CPLD_XC2C64A_BYTES_IN_ROW];
|
||||
} cpld_xc2c64a_row_mask_t;
|
||||
|
||||
typedef struct {
|
||||
cpld_xc2c64a_row_mask_t mask[6];
|
||||
uint8_t mask_index[CPLD_XC2C64A_ROWS];
|
||||
} cpld_xc2c64a_verify_t;
|
||||
|
||||
typedef struct {
|
||||
uint8_t address[CPLD_XC2C64A_ROWS];
|
||||
} cpld_xc2c64a_row_addresses_t;
|
||||
|
||||
bool cpld_xc2c64a_jtag_checksum(
|
||||
const jtag_t* const jtag,
|
||||
const cpld_xc2c64a_verify_t* const verify,
|
||||
uint32_t* const crc_value
|
||||
);
|
||||
void cpld_xc2c64a_jtag_sram_write(
|
||||
const jtag_t* const jtag,
|
||||
const cpld_xc2c64a_program_t* const program
|
||||
);
|
||||
bool cpld_xc2c64a_jtag_sram_verify(
|
||||
const jtag_t* const jtag,
|
||||
const cpld_xc2c64a_program_t* const program,
|
||||
const cpld_xc2c64a_verify_t* const verify
|
||||
);
|
||||
|
||||
extern const cpld_xc2c64a_program_t cpld_hackrf_program_sram;
|
||||
extern const cpld_xc2c64a_verify_t cpld_hackrf_verify;
|
||||
extern const cpld_xc2c64a_row_addresses_t cpld_hackrf_row_addresses;
|
||||
|
||||
#endif/*__CPLD_XC2C_H__*/
|
||||
@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Copyright 2019 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include "crc.h"
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
void crc32_init(crc32_t* const crc) {
|
||||
crc->remainder = 0xffffffff;
|
||||
crc->reversed_polynomial = 0xedb88320;
|
||||
crc->final_xor = 0xffffffff;
|
||||
}
|
||||
|
||||
void crc32_update(crc32_t* const crc, const uint8_t* const data, const size_t byte_count) {
|
||||
uint32_t remainder = crc->remainder;
|
||||
const size_t bit_count = byte_count * 8;
|
||||
for(size_t bit_n=0; bit_n<bit_count; bit_n++) {
|
||||
const bool bit_in = data[bit_n >> 3] & (1 << (bit_n & 7));
|
||||
remainder ^= (bit_in ? 1 : 0);
|
||||
const bool bit_out = (remainder & 1);
|
||||
remainder >>= 1;
|
||||
if( bit_out ) {
|
||||
remainder ^= crc->reversed_polynomial;
|
||||
}
|
||||
}
|
||||
crc->remainder = remainder;
|
||||
}
|
||||
|
||||
uint32_t crc32_digest(const crc32_t* const crc) {
|
||||
return crc->remainder ^ crc->final_xor;
|
||||
}
|
||||
@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright 2019 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __CRC_H__
|
||||
#define __CRC_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
typedef struct {
|
||||
uint32_t remainder;
|
||||
uint32_t reversed_polynomial;
|
||||
uint32_t final_xor;
|
||||
} crc32_t;
|
||||
|
||||
void crc32_init(crc32_t* const crc);
|
||||
void crc32_update(crc32_t* const crc, const uint8_t* const data, const size_t byte_count);
|
||||
uint32_t crc32_digest(const crc32_t* const crc);
|
||||
|
||||
#endif//__CRC_H__
|
||||
@ -0,0 +1,86 @@
|
||||
/*
|
||||
* Copyright 2012 Jared Boone <jared@sharebrained.com>
|
||||
* Copyright 2013 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "fault_handler.h"
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t r0;
|
||||
uint32_t r1;
|
||||
uint32_t r2;
|
||||
uint32_t r3;
|
||||
uint32_t r12;
|
||||
uint32_t lr; /* Link Register. */
|
||||
uint32_t pc; /* Program Counter. */
|
||||
uint32_t psr;/* Program Status Register. */
|
||||
} hard_fault_stack_t;
|
||||
|
||||
__attribute__((naked))
|
||||
void hard_fault_handler(void) {
|
||||
__asm__("TST LR, #4");
|
||||
__asm__("ITE EQ");
|
||||
__asm__("MRSEQ R0, MSP");
|
||||
__asm__("MRSNE R0, PSP");
|
||||
__asm__("B hard_fault_handler_c");
|
||||
}
|
||||
|
||||
volatile hard_fault_stack_t* hard_fault_stack_pt;
|
||||
|
||||
__attribute__((used)) void hard_fault_handler_c(uint32_t* args)
|
||||
{
|
||||
/* hard_fault_stack_pt contains registers saved before the hard fault */
|
||||
hard_fault_stack_pt = (hard_fault_stack_t*)args;
|
||||
|
||||
// args[0-7]: r0, r1, r2, r3, r12, lr, pc, psr
|
||||
// Other interesting registers to examine:
|
||||
// CFSR: Configurable Fault Status Register
|
||||
// HFSR: Hard Fault Status Register
|
||||
// DFSR: Debug Fault Status Register
|
||||
// AFSR: Auxiliary Fault Status Register
|
||||
// MMAR: MemManage Fault Address Register
|
||||
// BFAR: Bus Fault Address Register
|
||||
|
||||
/*
|
||||
if( SCB->HFSR & SCB_HFSR_FORCED ) {
|
||||
if( SCB->CFSR & SCB_CFSR_BFSR_BFARVALID ) {
|
||||
SCB->BFAR;
|
||||
if( SCB->CFSR & CSCB_CFSR_BFSR_PRECISERR ) {
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
while(1);
|
||||
}
|
||||
|
||||
void mem_manage_handler() {
|
||||
while(1);
|
||||
}
|
||||
|
||||
void bus_fault_handler() {
|
||||
while(1);
|
||||
}
|
||||
|
||||
void usage_fault_handler() {
|
||||
while(1);
|
||||
}
|
||||
@ -0,0 +1,73 @@
|
||||
/*
|
||||
* Copyright 2012 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __FAULT_HANDLER__
|
||||
#define __FAULT_HANDLER__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <libopencm3/cm3/memorymap.h>
|
||||
|
||||
// TODO: Move all this to a Cortex-M(?) include file, since these
|
||||
// structures are supposedly the same between processors (to an
|
||||
// undetermined extent).
|
||||
typedef struct armv7m_scb_t armv7m_scb_t;
|
||||
struct armv7m_scb_t {
|
||||
volatile const uint32_t CPUID;
|
||||
volatile uint32_t ICSR;
|
||||
volatile uint32_t VTOR;
|
||||
volatile uint32_t AIRCR;
|
||||
volatile uint32_t SCR;
|
||||
volatile uint32_t CCR;
|
||||
volatile uint32_t SHPR1;
|
||||
volatile uint32_t SHPR2;
|
||||
volatile uint32_t SHPR3;
|
||||
volatile uint32_t SHCSR;
|
||||
volatile uint32_t CFSR;
|
||||
volatile uint32_t HFSR;
|
||||
volatile uint32_t DFSR;
|
||||
volatile uint32_t MMFAR;
|
||||
volatile uint32_t BFAR;
|
||||
volatile uint32_t AFSR;
|
||||
volatile const uint32_t ID_PFR0;
|
||||
volatile const uint32_t ID_PFR1;
|
||||
volatile const uint32_t ID_DFR0;
|
||||
volatile const uint32_t ID_AFR0;
|
||||
volatile const uint32_t ID_MMFR0;
|
||||
volatile const uint32_t ID_MMFR1;
|
||||
volatile const uint32_t ID_MMFR2;
|
||||
volatile const uint32_t ID_MMFR3;
|
||||
volatile const uint32_t ID_ISAR0;
|
||||
volatile const uint32_t ID_ISAR1;
|
||||
volatile const uint32_t ID_ISAR2;
|
||||
volatile const uint32_t ID_ISAR3;
|
||||
volatile const uint32_t ID_ISAR4;
|
||||
volatile const uint32_t __reserved_0x74_0x87[5];
|
||||
volatile uint32_t CPACR;
|
||||
} __attribute__((packed));
|
||||
|
||||
static armv7m_scb_t* const SCB = (armv7m_scb_t*)SCB_BASE;
|
||||
|
||||
#define SCB_HFSR_DEBUGEVT (1 << 31)
|
||||
#define SCB_HFSR_FORCED (1 << 30)
|
||||
#define SCB_HFSR_VECTTBL (1 << 1)
|
||||
|
||||
#endif//__FAULT_HANDLER__
|
||||
@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright 2013 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <gpdma.h>
|
||||
|
||||
#include <libopencm3/lpc43xx/gpdma.h>
|
||||
|
||||
void gpdma_controller_enable() {
|
||||
GPDMA_CONFIG |= GPDMA_CONFIG_E(1);
|
||||
while( (GPDMA_CONFIG & GPDMA_CONFIG_E_MASK) == 0 );
|
||||
}
|
||||
|
||||
void gpdma_channel_enable(const uint_fast8_t channel) {
|
||||
GPDMA_CCONFIG(channel) |= GPDMA_CCONFIG_E(1);
|
||||
}
|
||||
|
||||
void gpdma_channel_disable(const uint_fast8_t channel) {
|
||||
GPDMA_CCONFIG(channel) &= ~GPDMA_CCONFIG_E_MASK;
|
||||
while( (GPDMA_ENBLDCHNS & GPDMA_ENBLDCHNS_ENABLEDCHANNELS(1 << channel)) );
|
||||
}
|
||||
|
||||
void gpdma_channel_interrupt_tc_clear(const uint_fast8_t channel) {
|
||||
GPDMA_INTTCCLEAR = GPDMA_INTTCCLEAR_INTTCCLEAR(1 << channel);
|
||||
}
|
||||
|
||||
void gpdma_channel_interrupt_error_clear(const uint_fast8_t channel) {
|
||||
GPDMA_INTERRCLR = GPDMA_INTERRCLR_INTERRCLR(1 << channel);
|
||||
}
|
||||
|
||||
void gpdma_lli_enable_interrupt(gpdma_lli_t* const lli) {
|
||||
lli->ccontrol |= GPDMA_CCONTROL_I(1);
|
||||
}
|
||||
|
||||
void gpdma_lli_create_loop(gpdma_lli_t* const lli, const size_t lli_count) {
|
||||
for(size_t i=0; i<lli_count; i++) {
|
||||
gpdma_lli_t* const next_lli = &lli[(i + 1) % lli_count];
|
||||
lli[i].clli = (lli[i].clli & ~GPDMA_CLLI_LLI_MASK) | GPDMA_CLLI_LLI((uint32_t)next_lli >> 2);
|
||||
}
|
||||
}
|
||||
|
||||
void gpdma_lli_create_oneshot(gpdma_lli_t* const lli, const size_t lli_count) {
|
||||
gpdma_lli_create_loop(lli, lli_count);
|
||||
lli[lli_count - 1].clli &= ~GPDMA_CLLI_LLI_MASK;
|
||||
}
|
||||
@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Copyright 2013 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __GPDMA_H__
|
||||
#define __GPDMA_H__
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <libopencm3/lpc43xx/gpdma.h>
|
||||
|
||||
void gpdma_controller_enable();
|
||||
|
||||
void gpdma_channel_enable(const uint_fast8_t channel);
|
||||
void gpdma_channel_disable(const uint_fast8_t channel);
|
||||
|
||||
void gpdma_channel_interrupt_tc_clear(const uint_fast8_t channel);
|
||||
void gpdma_channel_interrupt_error_clear(const uint_fast8_t channel);
|
||||
|
||||
void gpdma_lli_enable_interrupt(gpdma_lli_t* const lli);
|
||||
|
||||
void gpdma_lli_create_loop(gpdma_lli_t* const lli, const size_t lli_count);
|
||||
void gpdma_lli_create_oneshot(gpdma_lli_t* const lli, const size_t lli_count);
|
||||
|
||||
#endif/*__GPDMA_H__*/
|
||||
@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __GPIO_H__
|
||||
#define __GPIO_H__
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
typedef const struct gpio_t* gpio_t;
|
||||
|
||||
void gpio_init();
|
||||
void gpio_set(gpio_t gpio);
|
||||
void gpio_clear(gpio_t gpio);
|
||||
void gpio_toggle(gpio_t gpio);
|
||||
void gpio_output(gpio_t gpio);
|
||||
void gpio_input(gpio_t gpio);
|
||||
void gpio_write(gpio_t gpio, const bool value);
|
||||
bool gpio_read(gpio_t gpio);
|
||||
|
||||
#endif/*__GPIO_H__*/
|
||||
@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include "gpio_lpc.h"
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
void gpio_init() {
|
||||
for(size_t i=0; i<8; i++) {
|
||||
GPIO_LPC_PORT(i)->dir = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_set(gpio_t gpio) {
|
||||
gpio->port->set = gpio->mask;
|
||||
}
|
||||
|
||||
void gpio_clear(gpio_t gpio) {
|
||||
gpio->port->clr = gpio->mask;
|
||||
}
|
||||
|
||||
void gpio_toggle(gpio_t gpio) {
|
||||
gpio->port->not = gpio->mask;
|
||||
}
|
||||
|
||||
void gpio_output(gpio_t gpio) {
|
||||
gpio->port->dir |= gpio->mask;
|
||||
}
|
||||
|
||||
void gpio_input(gpio_t gpio) {
|
||||
gpio->port->dir &= ~gpio->mask;
|
||||
}
|
||||
|
||||
void gpio_write(gpio_t gpio, const bool value) {
|
||||
*gpio->gpio_w = value;
|
||||
}
|
||||
|
||||
bool gpio_read(gpio_t gpio) {
|
||||
return *gpio->gpio_w;
|
||||
}
|
||||
@ -0,0 +1,70 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __GPIO_LPC_H__
|
||||
#define __GPIO_LPC_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "gpio.h"
|
||||
|
||||
/* NOTE: libopencm3 constants and functions not used here due to naming
|
||||
* conflicts. I'd recommend changes to libopencm3 design to separate
|
||||
* register #defines and API declarations into separate header files.
|
||||
*/
|
||||
|
||||
typedef struct gpio_port_t {
|
||||
volatile uint32_t dir; /* +0x000 */
|
||||
uint32_t _reserved0[31];
|
||||
volatile uint32_t mask; /* +0x080 */
|
||||
uint32_t _reserved1[31];
|
||||
volatile uint32_t pin; /* +0x100 */
|
||||
uint32_t _reserved2[31];
|
||||
volatile uint32_t mpin; /* +0x180 */
|
||||
uint32_t _reserved3[31];
|
||||
volatile uint32_t set; /* +0x200 */
|
||||
uint32_t _reserved4[31];
|
||||
volatile uint32_t clr; /* +0x280 */
|
||||
uint32_t _reserved5[31];
|
||||
volatile uint32_t not; /* +0x300 */
|
||||
} gpio_port_t;
|
||||
|
||||
struct gpio_t {
|
||||
const uint32_t mask;
|
||||
gpio_port_t* const port;
|
||||
volatile uint32_t* const gpio_w;
|
||||
};
|
||||
|
||||
#define GPIO_LPC_BASE (0x400f4000)
|
||||
#define GPIO_LPC_B_OFFSET (0x0)
|
||||
#define GPIO_LPC_W_OFFSET (0x1000)
|
||||
#define GPIO_LPC_PORT_OFFSET (0x2000)
|
||||
|
||||
#define GPIO_LPC_PORT(_n) ((gpio_port_t*)((GPIO_LPC_BASE + GPIO_LPC_PORT_OFFSET) + (_n) * 4))
|
||||
#define GPIO_LPC_W(_port_num, _pin_num) (volatile uint32_t*)((GPIO_LPC_BASE + GPIO_LPC_W_OFFSET) + ((_port_num) * 0x80) + ((_pin_num) * 4))
|
||||
|
||||
#define GPIO(_port_num, _pin_num) { \
|
||||
.mask = (1UL << (_pin_num)), \
|
||||
.port = GPIO_LPC_PORT(_port_num), \
|
||||
.gpio_w = GPIO_LPC_W(_port_num, _pin_num), \
|
||||
}
|
||||
|
||||
#endif/*__GPIO_LPC_H__*/
|
||||
@ -0,0 +1,919 @@
|
||||
/*
|
||||
* Copyright 2012 Michael Ossmann <mike@ossmann.com>
|
||||
* Copyright 2012 Jared Boone <jared@sharebrained.com>
|
||||
* Copyright 2013 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include "hackrf_core.h"
|
||||
#include "hackrf_ui.h"
|
||||
#include "si5351c.h"
|
||||
#include "spi_ssp.h"
|
||||
#include "max2837.h"
|
||||
#include "max2837_target.h"
|
||||
#include "max5864.h"
|
||||
#include "max5864_target.h"
|
||||
#include "w25q80bv.h"
|
||||
#include "w25q80bv_target.h"
|
||||
#include "i2c_bus.h"
|
||||
#include "i2c_lpc.h"
|
||||
#include "cpld_jtag.h"
|
||||
#include <libopencm3/lpc43xx/cgu.h>
|
||||
#include <libopencm3/lpc43xx/ccu.h>
|
||||
#include <libopencm3/lpc43xx/scu.h>
|
||||
#include <libopencm3/lpc43xx/ssp.h>
|
||||
|
||||
#ifdef HACKRF_ONE
|
||||
#include "portapack.h"
|
||||
#endif
|
||||
|
||||
#include "gpio_lpc.h"
|
||||
|
||||
#define WAIT_CPU_CLOCK_INIT_DELAY (10000)
|
||||
/* GPIO Output PinMux */
|
||||
static struct gpio_t gpio_led[] = {
|
||||
GPIO(2, 1),
|
||||
GPIO(2, 2),
|
||||
GPIO(2, 8),
|
||||
#ifdef RAD1O
|
||||
GPIO(5, 26),
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct gpio_t gpio_1v8_enable = GPIO(3, 6);
|
||||
|
||||
/* MAX2837 GPIO (XCVR_CTL) PinMux */
|
||||
static struct gpio_t gpio_max2837_select = GPIO(0, 15);
|
||||
static struct gpio_t gpio_max2837_enable = GPIO(2, 6);
|
||||
static struct gpio_t gpio_max2837_rx_enable = GPIO(2, 5);
|
||||
static struct gpio_t gpio_max2837_tx_enable = GPIO(2, 4);
|
||||
|
||||
/* MAX5864 SPI chip select (AD_CS) GPIO PinMux */
|
||||
static struct gpio_t gpio_max5864_select = GPIO(2, 7);
|
||||
|
||||
/* RFFC5071 GPIO serial interface PinMux */
|
||||
// #ifdef RAD1O
|
||||
// static struct gpio_t gpio_rffc5072_select = GPIO(2, 13);
|
||||
// static struct gpio_t gpio_rffc5072_clock = GPIO(5, 6);
|
||||
// static struct gpio_t gpio_rffc5072_data = GPIO(3, 3);
|
||||
// static struct gpio_t gpio_rffc5072_reset = GPIO(2, 14);
|
||||
// #endif
|
||||
|
||||
/* RF supply (VAA) control */
|
||||
#ifdef HACKRF_ONE
|
||||
static struct gpio_t gpio_vaa_disable = GPIO(2, 9);
|
||||
#endif
|
||||
#ifdef RAD1O
|
||||
static struct gpio_t gpio_vaa_enable = GPIO(2, 9);
|
||||
#endif
|
||||
|
||||
static struct gpio_t gpio_w25q80bv_hold = GPIO(1, 14);
|
||||
static struct gpio_t gpio_w25q80bv_wp = GPIO(1, 15);
|
||||
static struct gpio_t gpio_w25q80bv_select = GPIO(5, 11);
|
||||
|
||||
/* RF switch control */
|
||||
#ifdef HACKRF_ONE
|
||||
static struct gpio_t gpio_hp = GPIO(2, 0);
|
||||
static struct gpio_t gpio_lp = GPIO(2, 10);
|
||||
static struct gpio_t gpio_tx_mix_bp = GPIO(2, 11);
|
||||
static struct gpio_t gpio_no_mix_bypass = GPIO(1, 0);
|
||||
static struct gpio_t gpio_rx_mix_bp = GPIO(2, 12);
|
||||
static struct gpio_t gpio_tx_amp = GPIO(2, 15);
|
||||
static struct gpio_t gpio_tx = GPIO(5, 15);
|
||||
static struct gpio_t gpio_mix_bypass = GPIO(5, 16);
|
||||
static struct gpio_t gpio_rx = GPIO(5, 5);
|
||||
static struct gpio_t gpio_no_tx_amp_pwr = GPIO(3, 5);
|
||||
static struct gpio_t gpio_amp_bypass = GPIO(0, 14);
|
||||
static struct gpio_t gpio_rx_amp = GPIO(1, 11);
|
||||
static struct gpio_t gpio_no_rx_amp_pwr = GPIO(1, 12);
|
||||
#endif
|
||||
#ifdef RAD1O
|
||||
static struct gpio_t gpio_tx_rx_n = GPIO(1, 11);
|
||||
static struct gpio_t gpio_tx_rx = GPIO(0, 14);
|
||||
static struct gpio_t gpio_by_mix = GPIO(1, 12);
|
||||
static struct gpio_t gpio_by_mix_n = GPIO(2, 10);
|
||||
static struct gpio_t gpio_by_amp = GPIO(1, 0);
|
||||
static struct gpio_t gpio_by_amp_n = GPIO(5, 5);
|
||||
static struct gpio_t gpio_mixer_en = GPIO(5, 16);
|
||||
static struct gpio_t gpio_low_high_filt = GPIO(2, 11);
|
||||
static struct gpio_t gpio_low_high_filt_n = GPIO(2, 12);
|
||||
static struct gpio_t gpio_tx_amp = GPIO(2, 15);
|
||||
static struct gpio_t gpio_rx_lna = GPIO(5, 15);
|
||||
#endif
|
||||
|
||||
/* CPLD JTAG interface GPIO pins */
|
||||
static struct gpio_t gpio_cpld_tdo = GPIO(5, 18);
|
||||
static struct gpio_t gpio_cpld_tck = GPIO(3, 0);
|
||||
#if (defined HACKRF_ONE || defined RAD1O)
|
||||
static struct gpio_t gpio_cpld_tms = GPIO(3, 4);
|
||||
static struct gpio_t gpio_cpld_tdi = GPIO(3, 1);
|
||||
#else
|
||||
static struct gpio_t gpio_cpld_tms = GPIO(3, 1);
|
||||
static struct gpio_t gpio_cpld_tdi = GPIO(3, 4);
|
||||
#endif
|
||||
|
||||
#ifdef HACKRF_ONE
|
||||
static struct gpio_t gpio_cpld_pp_tms = GPIO(1, 1);
|
||||
static struct gpio_t gpio_cpld_pp_tdo = GPIO(1, 8);
|
||||
#endif
|
||||
|
||||
static struct gpio_t gpio_hw_sync_enable = GPIO(5,12);
|
||||
static struct gpio_t gpio_rx_q_invert = GPIO(0, 13);
|
||||
|
||||
i2c_bus_t i2c0 = {
|
||||
.obj = (void*)I2C0_BASE,
|
||||
.start = i2c_lpc_start,
|
||||
.stop = i2c_lpc_stop,
|
||||
.transfer = i2c_lpc_transfer,
|
||||
};
|
||||
|
||||
i2c_bus_t i2c1 = {
|
||||
.obj = (void*)I2C1_BASE,
|
||||
.start = i2c_lpc_start,
|
||||
.stop = i2c_lpc_stop,
|
||||
.transfer = i2c_lpc_transfer,
|
||||
};
|
||||
|
||||
// const i2c_lpc_config_t i2c_config_si5351c_slow_clock = {
|
||||
// .duty_cycle_count = 15,
|
||||
// };
|
||||
|
||||
const i2c_lpc_config_t i2c_config_si5351c_fast_clock = {
|
||||
.duty_cycle_count = 255,
|
||||
};
|
||||
|
||||
si5351c_driver_t clock_gen = {
|
||||
.bus = &i2c0,
|
||||
.i2c_address = 0x60,
|
||||
};
|
||||
|
||||
const ssp_config_t ssp_config_max2837 = {
|
||||
/* FIXME speed up once everything is working reliably */
|
||||
/*
|
||||
// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
|
||||
const uint8_t serial_clock_rate = 32;
|
||||
const uint8_t clock_prescale_rate = 128;
|
||||
*/
|
||||
// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
|
||||
.data_bits = SSP_DATA_16BITS,
|
||||
.serial_clock_rate = 21,
|
||||
.clock_prescale_rate = 2,
|
||||
.gpio_select = &gpio_max2837_select,
|
||||
};
|
||||
|
||||
const ssp_config_t ssp_config_max5864 = {
|
||||
/* FIXME speed up once everything is working reliably */
|
||||
/*
|
||||
// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
|
||||
const uint8_t serial_clock_rate = 32;
|
||||
const uint8_t clock_prescale_rate = 128;
|
||||
*/
|
||||
// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
|
||||
.data_bits = SSP_DATA_8BITS,
|
||||
.serial_clock_rate = 21,
|
||||
.clock_prescale_rate = 2,
|
||||
.gpio_select = &gpio_max5864_select,
|
||||
};
|
||||
|
||||
spi_bus_t spi_bus_ssp1 = {
|
||||
.obj = (void*)SSP1_BASE,
|
||||
.config = &ssp_config_max2837,
|
||||
.start = spi_ssp_start,
|
||||
.stop = spi_ssp_stop,
|
||||
.transfer = spi_ssp_transfer,
|
||||
.transfer_gather = spi_ssp_transfer_gather,
|
||||
};
|
||||
|
||||
max2837_driver_t max2837 = {
|
||||
.bus = &spi_bus_ssp1,
|
||||
.gpio_enable = &gpio_max2837_enable,
|
||||
.gpio_rx_enable = &gpio_max2837_rx_enable,
|
||||
.gpio_tx_enable = &gpio_max2837_tx_enable,
|
||||
.target_init = max2837_target_init,
|
||||
.set_mode = max2837_target_set_mode,
|
||||
};
|
||||
|
||||
max5864_driver_t max5864 = {
|
||||
.bus = &spi_bus_ssp1,
|
||||
.target_init = max5864_target_init,
|
||||
};
|
||||
|
||||
const ssp_config_t ssp_config_w25q80bv = {
|
||||
.data_bits = SSP_DATA_8BITS,
|
||||
.serial_clock_rate = 2,
|
||||
.clock_prescale_rate = 2,
|
||||
.gpio_select = &gpio_w25q80bv_select,
|
||||
};
|
||||
|
||||
spi_bus_t spi_bus_ssp0 = {
|
||||
.obj = (void*)SSP0_BASE,
|
||||
.config = &ssp_config_w25q80bv,
|
||||
.start = spi_ssp_start,
|
||||
.stop = spi_ssp_stop,
|
||||
.transfer = spi_ssp_transfer,
|
||||
.transfer_gather = spi_ssp_transfer_gather,
|
||||
};
|
||||
|
||||
w25q80bv_driver_t spi_flash = {
|
||||
.bus = &spi_bus_ssp0,
|
||||
.gpio_hold = &gpio_w25q80bv_hold,
|
||||
.gpio_wp = &gpio_w25q80bv_wp,
|
||||
.target_init = w25q80bv_target_init,
|
||||
};
|
||||
|
||||
sgpio_config_t sgpio_config = {
|
||||
.gpio_rx_q_invert = &gpio_rx_q_invert,
|
||||
.gpio_hw_sync_enable = &gpio_hw_sync_enable,
|
||||
.slice_mode_multislice = true,
|
||||
};
|
||||
|
||||
rf_path_t rf_path = {
|
||||
.switchctrl = 0,
|
||||
#ifdef HACKRF_ONE
|
||||
.gpio_hp = &gpio_hp,
|
||||
.gpio_lp = &gpio_lp,
|
||||
.gpio_tx_mix_bp = &gpio_tx_mix_bp,
|
||||
.gpio_no_mix_bypass = &gpio_no_mix_bypass,
|
||||
.gpio_rx_mix_bp = &gpio_rx_mix_bp,
|
||||
.gpio_tx_amp = &gpio_tx_amp,
|
||||
.gpio_tx = &gpio_tx,
|
||||
.gpio_mix_bypass = &gpio_mix_bypass,
|
||||
.gpio_rx = &gpio_rx,
|
||||
.gpio_no_tx_amp_pwr = &gpio_no_tx_amp_pwr,
|
||||
.gpio_amp_bypass = &gpio_amp_bypass,
|
||||
.gpio_rx_amp = &gpio_rx_amp,
|
||||
.gpio_no_rx_amp_pwr = &gpio_no_rx_amp_pwr,
|
||||
#endif
|
||||
#ifdef RAD1O
|
||||
.gpio_tx_rx_n = &gpio_tx_rx_n,
|
||||
.gpio_tx_rx = &gpio_tx_rx,
|
||||
.gpio_by_mix = &gpio_by_mix,
|
||||
.gpio_by_mix_n = &gpio_by_mix_n,
|
||||
.gpio_by_amp = &gpio_by_amp,
|
||||
.gpio_by_amp_n = &gpio_by_amp_n,
|
||||
.gpio_mixer_en = &gpio_mixer_en,
|
||||
.gpio_low_high_filt = &gpio_low_high_filt,
|
||||
.gpio_low_high_filt_n = &gpio_low_high_filt_n,
|
||||
.gpio_tx_amp = &gpio_tx_amp,
|
||||
.gpio_rx_lna = &gpio_rx_lna,
|
||||
#endif
|
||||
};
|
||||
|
||||
jtag_gpio_t jtag_gpio_cpld = {
|
||||
.gpio_tms = &gpio_cpld_tms,
|
||||
.gpio_tck = &gpio_cpld_tck,
|
||||
.gpio_tdi = &gpio_cpld_tdi,
|
||||
.gpio_tdo = &gpio_cpld_tdo,
|
||||
#ifdef HACKRF_ONE
|
||||
.gpio_pp_tms = &gpio_cpld_pp_tms,
|
||||
.gpio_pp_tdo = &gpio_cpld_pp_tdo,
|
||||
#endif
|
||||
};
|
||||
|
||||
jtag_t jtag_cpld = {
|
||||
.gpio = &jtag_gpio_cpld,
|
||||
};
|
||||
|
||||
void delay(uint32_t duration)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < duration; i++)
|
||||
__asm__("nop");
|
||||
}
|
||||
|
||||
/* GCD algo from wikipedia */
|
||||
/* http://en.wikipedia.org/wiki/Greatest_common_divisor */
|
||||
static uint32_t
|
||||
gcd(uint32_t u, uint32_t v)
|
||||
{
|
||||
int s;
|
||||
|
||||
if (!u || !v)
|
||||
return u | v;
|
||||
|
||||
for (s=0; !((u|v)&1); s++) {
|
||||
u >>= 1;
|
||||
v >>= 1;
|
||||
}
|
||||
|
||||
while (!(u&1))
|
||||
u >>= 1;
|
||||
|
||||
do {
|
||||
while (!(v&1))
|
||||
v >>= 1;
|
||||
|
||||
if (u>v) {
|
||||
uint32_t t;
|
||||
t = v;
|
||||
v = u;
|
||||
u = t;
|
||||
}
|
||||
|
||||
v = v - u;
|
||||
}
|
||||
while (v);
|
||||
|
||||
return u << s;
|
||||
}
|
||||
|
||||
bool sample_rate_frac_set(uint32_t rate_num, uint32_t rate_denom)
|
||||
{
|
||||
const uint64_t VCO_FREQ = 800 * 1000 * 1000; /* 800 MHz */
|
||||
uint32_t MSx_P1,MSx_P2,MSx_P3;
|
||||
uint32_t a, b, c;
|
||||
uint32_t rem;
|
||||
|
||||
hackrf_ui()->set_sample_rate(rate_num/2);
|
||||
|
||||
/* Find best config */
|
||||
a = (VCO_FREQ * rate_denom) / rate_num;
|
||||
|
||||
rem = (VCO_FREQ * rate_denom) - (a * rate_num);
|
||||
|
||||
if (!rem) {
|
||||
/* Integer mode */
|
||||
b = 0;
|
||||
c = 1;
|
||||
} else {
|
||||
/* Fractional */
|
||||
uint32_t g = gcd(rem, rate_num);
|
||||
rem /= g;
|
||||
rate_num /= g;
|
||||
|
||||
if (rate_num < (1<<20)) {
|
||||
/* Perfect match */
|
||||
b = rem;
|
||||
c = rate_num;
|
||||
} else {
|
||||
/* Approximate */
|
||||
c = (1<<20) - 1;
|
||||
b = ((uint64_t)c * (uint64_t)rem) / rate_num;
|
||||
|
||||
g = gcd(b, c);
|
||||
b /= g;
|
||||
c /= g;
|
||||
}
|
||||
}
|
||||
|
||||
/* Can we enable integer mode ? */
|
||||
if (a & 0x1 || b)
|
||||
si5351c_set_int_mode(&clock_gen, 0, 0);
|
||||
else
|
||||
si5351c_set_int_mode(&clock_gen, 0, 1);
|
||||
|
||||
/* Final MS values */
|
||||
MSx_P1 = 128*a + (128 * b/c) - 512;
|
||||
MSx_P2 = (128*b) % c;
|
||||
MSx_P3 = c;
|
||||
|
||||
/* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */
|
||||
si5351c_configure_multisynth(&clock_gen, 0, MSx_P1, MSx_P2, MSx_P3, 1);
|
||||
|
||||
/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
|
||||
si5351c_configure_multisynth(&clock_gen, 1, 0, 0, 0, 0);//p1 doesn't matter
|
||||
|
||||
/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
|
||||
si5351c_configure_multisynth(&clock_gen, 2, 0, 0, 0, 0);//p1 doesn't matter
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool sample_rate_set(const uint32_t sample_rate_hz) {
|
||||
uint32_t p1 = 4608;
|
||||
uint32_t p2 = 0;
|
||||
uint32_t p3 = 0;
|
||||
|
||||
switch(sample_rate_hz) {
|
||||
case 8000000:
|
||||
p1 = SI_INTDIV(50); // 800MHz / 50 = 16 MHz (SGPIO), 8 MHz (codec)
|
||||
break;
|
||||
|
||||
case 9216000:
|
||||
// 43.40277777777778: a = 43; b = 29; c = 72
|
||||
p1 = 5043;
|
||||
p2 = 40;
|
||||
p3 = 72;
|
||||
break;
|
||||
|
||||
case 10000000:
|
||||
p1 = SI_INTDIV(40); // 800MHz / 40 = 20 MHz (SGPIO), 10 MHz (codec)
|
||||
break;
|
||||
|
||||
case 12288000:
|
||||
// 32.552083333333336: a = 32; b = 159; c = 288
|
||||
p1 = 3654;
|
||||
p2 = 192;
|
||||
p3 = 288;
|
||||
break;
|
||||
|
||||
case 12500000:
|
||||
p1 = SI_INTDIV(32); // 800MHz / 32 = 25 MHz (SGPIO), 12.5 MHz (codec)
|
||||
break;
|
||||
|
||||
case 16000000:
|
||||
p1 = SI_INTDIV(25); // 800MHz / 25 = 32 MHz (SGPIO), 16 MHz (codec)
|
||||
break;
|
||||
|
||||
case 18432000:
|
||||
// 21.70138888889: a = 21; b = 101; c = 144
|
||||
p1 = 2265;
|
||||
p2 = 112;
|
||||
p3 = 144;
|
||||
break;
|
||||
|
||||
case 20000000:
|
||||
p1 = SI_INTDIV(20); // 800MHz / 20 = 40 MHz (SGPIO), 20 MHz (codec)
|
||||
break;
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
||||
/* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */
|
||||
si5351c_configure_multisynth(&clock_gen, 0, p1, p2, p3, 1);
|
||||
|
||||
/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
|
||||
si5351c_configure_multisynth(&clock_gen, 1, p1, 0, 1, 0);//p1 doesn't matter
|
||||
|
||||
/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
|
||||
si5351c_configure_multisynth(&clock_gen, 2, p1, 0, 1, 0);//p1 doesn't matter
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz) {
|
||||
uint32_t bandwidth_hz_real = max2837_set_lpf_bandwidth(&max2837, bandwidth_hz);
|
||||
|
||||
if(bandwidth_hz_real) hackrf_ui()->set_filter_bw(bandwidth_hz_real);
|
||||
|
||||
return bandwidth_hz_real != 0;
|
||||
}
|
||||
|
||||
/*
|
||||
Configure PLL1 (Main MCU Clock) to max speed (204MHz).
|
||||
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1.
|
||||
This function shall be called after cpu_clock_init().
|
||||
*/
|
||||
static void cpu_clock_pll1_max_speed(void)
|
||||
{
|
||||
uint32_t pll_reg;
|
||||
|
||||
/* Configure PLL1 to Intermediate Clock (between 90 MHz and 110 MHz) */
|
||||
/* Integer mode:
|
||||
FCLKOUT = M*(FCLKIN/N)
|
||||
FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N)
|
||||
*/
|
||||
pll_reg = CGU_PLL1_CTRL;
|
||||
/* Clear PLL1 bits */
|
||||
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */
|
||||
CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
|
||||
CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
|
||||
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
|
||||
/* Set PLL1 up to 12MHz * 8 = 96MHz. */
|
||||
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
|
||||
| CGU_PLL1_CTRL_PSEL(0)
|
||||
| CGU_PLL1_CTRL_NSEL(0)
|
||||
| CGU_PLL1_CTRL_MSEL(7)
|
||||
| CGU_PLL1_CTRL_FBSEL(1);
|
||||
CGU_PLL1_CTRL = pll_reg;
|
||||
/* wait until stable */
|
||||
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
|
||||
|
||||
/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
|
||||
CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
|
||||
|
||||
/* Wait before to switch to max speed */
|
||||
delay(WAIT_CPU_CLOCK_INIT_DELAY);
|
||||
|
||||
/* Configure PLL1 Max Speed */
|
||||
/* Direct mode: FCLKOUT = FCCO = M*(FCLKIN/N) */
|
||||
pll_reg = CGU_PLL1_CTRL;
|
||||
/* Clear PLL1 bits */
|
||||
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */
|
||||
CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
|
||||
CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
|
||||
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
|
||||
/* Set PLL1 up to 12MHz * 17 = 204MHz. */
|
||||
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
|
||||
| CGU_PLL1_CTRL_PSEL(0)
|
||||
| CGU_PLL1_CTRL_NSEL(0)
|
||||
| CGU_PLL1_CTRL_MSEL(16)
|
||||
| CGU_PLL1_CTRL_FBSEL(1)
|
||||
| CGU_PLL1_CTRL_DIRECT(1);
|
||||
CGU_PLL1_CTRL = pll_reg;
|
||||
/* wait until stable */
|
||||
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
|
||||
|
||||
}
|
||||
|
||||
/* clock startup for LPC4320 configure PLL1 to max speed (204MHz).
|
||||
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */
|
||||
void cpu_clock_init(void)
|
||||
{
|
||||
/* use IRC as clock source for APB1 (including I2C0) */
|
||||
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);
|
||||
|
||||
/* use IRC as clock source for APB3 */
|
||||
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC);
|
||||
|
||||
i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_fast_clock);
|
||||
|
||||
si5351c_disable_all_outputs(&clock_gen);
|
||||
si5351c_disable_oeb_pin_control(&clock_gen);
|
||||
si5351c_power_down_all_clocks(&clock_gen);
|
||||
si5351c_set_crystal_configuration(&clock_gen);
|
||||
si5351c_enable_xo_and_ms_fanout(&clock_gen);
|
||||
si5351c_configure_pll_sources(&clock_gen);
|
||||
si5351c_configure_pll_multisynth(&clock_gen);
|
||||
|
||||
/*
|
||||
* Clocks:
|
||||
* CLK0 -> MAX5864/CPLD
|
||||
* CLK1 -> CPLD
|
||||
* CLK2 -> SGPIO
|
||||
* CLK3 -> External Clock Output (power down at boot)
|
||||
* CLK4 -> RFFC5072 (MAX2837 on rad1o)
|
||||
* CLK5 -> MAX2837 (MAX2871 on rad1o)
|
||||
* CLK6 -> none
|
||||
* CLK7 -> LPC43xx (uses a 12MHz crystal by default)
|
||||
*/
|
||||
|
||||
/* MS4/CLK4 is the source for the RFFC5071 mixer (MAX2837 on rad1o). */
|
||||
si5351c_configure_multisynth(&clock_gen, 4, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
|
||||
/* MS5/CLK5 is the source for the MAX2837 clock input (MAX2871 on rad1o). */
|
||||
si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
|
||||
|
||||
/* MS6/CLK6 is unused. */
|
||||
/* MS7/CLK7 is unused. */
|
||||
|
||||
/* Set to 10 MHz, the common rate between Jawbreaker and HackRF One. */
|
||||
sample_rate_set(10000000);
|
||||
|
||||
si5351c_set_clock_source(&clock_gen, PLL_SOURCE_XTAL);
|
||||
// soft reset
|
||||
si5351c_reset_pll(&clock_gen);
|
||||
si5351c_enable_clock_outputs(&clock_gen);
|
||||
|
||||
//FIXME disable I2C
|
||||
/* Kick I2C0 down to 400kHz when we switch over to APB1 clock = 204MHz */
|
||||
i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_fast_clock);
|
||||
|
||||
/*
|
||||
* 12MHz clock is entering LPC XTAL1/OSC input now.
|
||||
* On HackRF One and Jawbreaker, there is a 12 MHz crystal at the LPC.
|
||||
* Set up PLL1 to run from XTAL1 input.
|
||||
*/
|
||||
|
||||
//FIXME a lot of the details here should be in a CGU driver
|
||||
|
||||
/* set xtal oscillator to low frequency mode */
|
||||
CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF_MASK;
|
||||
|
||||
/* power on the oscillator and wait until stable */
|
||||
CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE_MASK;
|
||||
|
||||
/* Wait about 100us after Crystal Power ON */
|
||||
delay(WAIT_CPU_CLOCK_INIT_DELAY);
|
||||
|
||||
/* use XTAL_OSC as clock source for BASE_M4_CLK (CPU) */
|
||||
CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
|
||||
|
||||
/* use XTAL_OSC as clock source for APB1 */
|
||||
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
|
||||
| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
|
||||
|
||||
/* use XTAL_OSC as clock source for APB3 */
|
||||
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
|
||||
| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);
|
||||
|
||||
cpu_clock_pll1_max_speed();
|
||||
|
||||
/* use XTAL_OSC as clock source for PLL0USB */
|
||||
CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1)
|
||||
| CGU_PLL0USB_CTRL_AUTOBLOCK(1)
|
||||
| CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL);
|
||||
while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK);
|
||||
|
||||
/* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */
|
||||
/* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */
|
||||
CGU_PLL0USB_MDIV = 0x06167FFA;
|
||||
CGU_PLL0USB_NP_DIV = 0x00302062;
|
||||
CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD(1)
|
||||
| CGU_PLL0USB_CTRL_DIRECTI(1)
|
||||
| CGU_PLL0USB_CTRL_DIRECTO(1)
|
||||
| CGU_PLL0USB_CTRL_CLKEN(1));
|
||||
|
||||
/* power on PLL0USB and wait until stable */
|
||||
CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD_MASK;
|
||||
while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK));
|
||||
|
||||
/* use PLL0USB as clock source for USB0 */
|
||||
CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK(1)
|
||||
| CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);
|
||||
|
||||
/* Switch peripheral clock over to use PLL1 (204MHz) */
|
||||
CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK(1)
|
||||
| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
|
||||
|
||||
/* Switch APB1 clock over to use PLL1 (204MHz) */
|
||||
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
|
||||
| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
|
||||
|
||||
/* Switch APB3 clock over to use PLL1 (204MHz) */
|
||||
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
|
||||
| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1);
|
||||
|
||||
CGU_BASE_SSP0_CLK = CGU_BASE_SSP0_CLK_AUTOBLOCK(1)
|
||||
| CGU_BASE_SSP0_CLK_CLK_SEL(CGU_SRC_PLL1);
|
||||
|
||||
CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_AUTOBLOCK(1)
|
||||
| CGU_BASE_SSP1_CLK_CLK_SEL(CGU_SRC_PLL1);
|
||||
|
||||
#if (defined JAWBREAKER || defined HACKRF_ONE)
|
||||
/* Disable unused clocks */
|
||||
/* Start with PLLs */
|
||||
CGU_PLL0AUDIO_CTRL = CGU_PLL0AUDIO_CTRL_PD(1);
|
||||
|
||||
/* Dividers */
|
||||
CGU_IDIVA_CTRL = CGU_IDIVA_CTRL_PD(1);
|
||||
CGU_IDIVB_CTRL = CGU_IDIVB_CTRL_PD(1);
|
||||
CGU_IDIVC_CTRL = CGU_IDIVC_CTRL_PD(1);
|
||||
CGU_IDIVD_CTRL = CGU_IDIVD_CTRL_PD(1);
|
||||
CGU_IDIVE_CTRL = CGU_IDIVE_CTRL_PD(1);
|
||||
|
||||
/* Base clocks */
|
||||
CGU_BASE_SPIFI_CLK = CGU_BASE_SPIFI_CLK_PD(1); /* SPIFI is only used at boot */
|
||||
CGU_BASE_USB1_CLK = CGU_BASE_USB1_CLK_PD(1); /* USB1 is not exposed on HackRF */
|
||||
CGU_BASE_PHY_RX_CLK = CGU_BASE_PHY_RX_CLK_PD(1);
|
||||
CGU_BASE_PHY_TX_CLK = CGU_BASE_PHY_TX_CLK_PD(1);
|
||||
CGU_BASE_LCD_CLK = CGU_BASE_LCD_CLK_PD(1);
|
||||
CGU_BASE_VADC_CLK = CGU_BASE_VADC_CLK_PD(1);
|
||||
CGU_BASE_SDIO_CLK = CGU_BASE_SDIO_CLK_PD(1);
|
||||
CGU_BASE_UART0_CLK = CGU_BASE_UART0_CLK_PD(1);
|
||||
CGU_BASE_UART1_CLK = CGU_BASE_UART1_CLK_PD(1);
|
||||
CGU_BASE_UART2_CLK = CGU_BASE_UART2_CLK_PD(1);
|
||||
CGU_BASE_UART3_CLK = CGU_BASE_UART3_CLK_PD(1);
|
||||
CGU_BASE_OUT_CLK = CGU_BASE_OUT_CLK_PD(1);
|
||||
CGU_BASE_AUDIO_CLK = CGU_BASE_AUDIO_CLK_PD(1);
|
||||
CGU_BASE_CGU_OUT0_CLK = CGU_BASE_CGU_OUT0_CLK_PD(1);
|
||||
CGU_BASE_CGU_OUT1_CLK = CGU_BASE_CGU_OUT1_CLK_PD(1);
|
||||
|
||||
/* Disable unused peripheral clocks */
|
||||
CCU1_CLK_APB1_CAN1_CFG = 0;
|
||||
CCU1_CLK_APB1_I2S_CFG = 0;
|
||||
CCU1_CLK_APB1_MOTOCONPWM_CFG = 0;
|
||||
CCU1_CLK_APB3_ADC0_CFG = 0;
|
||||
CCU1_CLK_APB3_ADC1_CFG = 0;
|
||||
CCU1_CLK_APB3_CAN0_CFG = 0;
|
||||
CCU1_CLK_APB3_DAC_CFG = 0;
|
||||
CCU1_CLK_M4_DMA_CFG = 0;
|
||||
CCU1_CLK_M4_EMC_CFG = 0;
|
||||
CCU1_CLK_M4_EMCDIV_CFG = 0;
|
||||
CCU1_CLK_M4_ETHERNET_CFG = 0;
|
||||
CCU1_CLK_M4_LCD_CFG = 0;
|
||||
CCU1_CLK_M4_QEI_CFG = 0;
|
||||
CCU1_CLK_M4_RITIMER_CFG = 0;
|
||||
CCU1_CLK_M4_SCT_CFG = 0;
|
||||
CCU1_CLK_M4_SDIO_CFG = 0;
|
||||
CCU1_CLK_M4_SPIFI_CFG = 0;
|
||||
CCU1_CLK_M4_TIMER0_CFG = 0;
|
||||
CCU1_CLK_M4_TIMER1_CFG = 0;
|
||||
CCU1_CLK_M4_TIMER2_CFG = 0;
|
||||
CCU1_CLK_M4_TIMER3_CFG = 0;
|
||||
CCU1_CLK_M4_UART1_CFG = 0;
|
||||
CCU1_CLK_M4_USART0_CFG = 0;
|
||||
CCU1_CLK_M4_USART2_CFG = 0;
|
||||
CCU1_CLK_M4_USART3_CFG = 0;
|
||||
CCU1_CLK_M4_USB1_CFG = 0;
|
||||
CCU1_CLK_M4_VADC_CFG = 0;
|
||||
// CCU1_CLK_SPIFI_CFG = 0;
|
||||
// CCU1_CLK_USB1_CFG = 0;
|
||||
// CCU1_CLK_VADC_CFG = 0;
|
||||
// CCU2_CLK_APB0_UART1_CFG = 0;
|
||||
// CCU2_CLK_APB0_USART0_CFG = 0;
|
||||
// CCU2_CLK_APB2_USART2_CFG = 0;
|
||||
// CCU2_CLK_APB2_USART3_CFG = 0;
|
||||
// CCU2_CLK_APLL_CFG = 0;
|
||||
// CCU2_CLK_SDIO_CFG = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
clock_source_t activate_best_clock_source(void)
|
||||
{
|
||||
#ifdef HACKRF_ONE
|
||||
/* Ensure PortaPack reference oscillator is off while checking for external clock input. */
|
||||
if( portapack_reference_oscillator && portapack()) {
|
||||
portapack_reference_oscillator(false);
|
||||
}
|
||||
#endif
|
||||
|
||||
clock_source_t source = CLOCK_SOURCE_HACKRF;
|
||||
|
||||
/* Check for external clock input. */
|
||||
if (si5351c_clkin_signal_valid(&clock_gen)) {
|
||||
source = CLOCK_SOURCE_EXTERNAL;
|
||||
} else {
|
||||
#ifdef HACKRF_ONE
|
||||
/* Enable PortaPack reference oscillator (if present), and check for valid clock. */
|
||||
if( portapack_reference_oscillator && portapack() ) {
|
||||
portapack_reference_oscillator(true);
|
||||
delay(510000); /* loop iterations @ 204MHz for >10ms for oscillator to enable. */
|
||||
if (si5351c_clkin_signal_valid(&clock_gen)) {
|
||||
source = CLOCK_SOURCE_PORTAPACK;
|
||||
} else {
|
||||
portapack_reference_oscillator(false);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
/* No external or PortaPack clock was found. Use HackRF Si5351C crystal. */
|
||||
}
|
||||
|
||||
si5351c_set_clock_source(&clock_gen, (source == CLOCK_SOURCE_HACKRF) ? PLL_SOURCE_XTAL : PLL_SOURCE_CLKIN);
|
||||
hackrf_ui()->set_clock_source(source);
|
||||
return source;
|
||||
}
|
||||
|
||||
void ssp1_set_mode_max2837(void)
|
||||
{
|
||||
spi_bus_start(max2837.bus, &ssp_config_max2837);
|
||||
}
|
||||
|
||||
void ssp1_set_mode_max5864(void)
|
||||
{
|
||||
spi_bus_start(max5864.bus, &ssp_config_max5864);
|
||||
}
|
||||
|
||||
void pin_setup(void) {
|
||||
/* Configure all GPIO as Input (safe state) */
|
||||
gpio_init();
|
||||
|
||||
/* TDI and TMS pull-ups are required in all JTAG-compliant devices.
|
||||
*
|
||||
* The HackRF CPLD is always present, so let the CPLD pull up its TDI and TMS.
|
||||
*
|
||||
* The PortaPack may not be present, so pull up the PortaPack TMS pin from the
|
||||
* microcontroller.
|
||||
*
|
||||
* TCK is recommended to be held low, so use microcontroller pull-down.
|
||||
*
|
||||
* TDO is undriven except when in Shift-IR or Shift-DR phases.
|
||||
* Use the microcontroller to pull down to keep from floating.
|
||||
*
|
||||
* LPC43xx pull-up and pull-down resistors are approximately 53K.
|
||||
*/
|
||||
#ifdef HACKRF_ONE
|
||||
scu_pinmux(SCU_PINMUX_PP_TMS, SCU_GPIO_PUP | SCU_CONF_FUNCTION0);
|
||||
scu_pinmux(SCU_PINMUX_PP_TDO, SCU_GPIO_PDN | SCU_CONF_FUNCTION0);
|
||||
#endif
|
||||
scu_pinmux(SCU_PINMUX_CPLD_TMS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
|
||||
scu_pinmux(SCU_PINMUX_CPLD_TDI, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
|
||||
scu_pinmux(SCU_PINMUX_CPLD_TDO, SCU_GPIO_PDN | SCU_CONF_FUNCTION4);
|
||||
scu_pinmux(SCU_PINMUX_CPLD_TCK, SCU_GPIO_PDN | SCU_CONF_FUNCTION0);
|
||||
|
||||
/* Configure SCU Pin Mux as GPIO */
|
||||
scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_NOPULL);
|
||||
scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_NOPULL);
|
||||
scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_NOPULL);
|
||||
#ifdef RAD1O
|
||||
scu_pinmux(SCU_PINMUX_LED4, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION4);
|
||||
#endif
|
||||
|
||||
/* Configure USB indicators */
|
||||
#ifdef JAWBREAKER
|
||||
scu_pinmux(SCU_PINMUX_USB_LED0, SCU_CONF_FUNCTION3);
|
||||
scu_pinmux(SCU_PINMUX_USB_LED1, SCU_CONF_FUNCTION3);
|
||||
#endif
|
||||
|
||||
gpio_output(&gpio_led[0]);
|
||||
gpio_output(&gpio_led[1]);
|
||||
gpio_output(&gpio_led[2]);
|
||||
#ifdef RAD1O
|
||||
gpio_output(&gpio_led[3]);
|
||||
#endif
|
||||
|
||||
disable_1v8_power();
|
||||
gpio_output(&gpio_1v8_enable);
|
||||
scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
|
||||
|
||||
#ifdef HACKRF_ONE
|
||||
/* Safe state: start with VAA turned off: */
|
||||
disable_rf_power();
|
||||
|
||||
/* Configure RF power supply (VAA) switch control signal as output */
|
||||
gpio_output(&gpio_vaa_disable);
|
||||
#endif
|
||||
|
||||
#ifdef RAD1O
|
||||
/* Safe state: start with VAA turned off: */
|
||||
disable_rf_power();
|
||||
|
||||
/* Configure RF power supply (VAA) switch control signal as output */
|
||||
gpio_output(&gpio_vaa_enable);
|
||||
|
||||
/* Disable unused clock outputs. They generate noise. */
|
||||
scu_pinmux(CLK0, SCU_CLK_IN | SCU_CONF_FUNCTION7);
|
||||
scu_pinmux(CLK2, SCU_CLK_IN | SCU_CONF_FUNCTION7);
|
||||
|
||||
scu_pinmux(SCU_PINMUX_GPIO3_10, SCU_GPIO_PDN | SCU_CONF_FUNCTION0);
|
||||
scu_pinmux(SCU_PINMUX_GPIO3_11, SCU_GPIO_PDN | SCU_CONF_FUNCTION0);
|
||||
|
||||
#endif
|
||||
|
||||
/* enable input on SCL and SDA pins */
|
||||
SCU_SFSI2C0 = SCU_I2C0_NOMINAL;
|
||||
|
||||
spi_bus_start(&spi_bus_ssp1, &ssp_config_max2837);
|
||||
|
||||
mixer_bus_setup(&mixer);
|
||||
|
||||
rf_path_pin_setup(&rf_path);
|
||||
|
||||
/* Configure external clock in */
|
||||
scu_pinmux(SCU_PINMUX_GP_CLKIN, SCU_CLK_IN | SCU_CONF_FUNCTION1);
|
||||
|
||||
sgpio_configure_pin_functions(&sgpio_config);
|
||||
}
|
||||
|
||||
void enable_1v8_power(void) {
|
||||
gpio_set(&gpio_1v8_enable);
|
||||
}
|
||||
|
||||
void disable_1v8_power(void) {
|
||||
gpio_clear(&gpio_1v8_enable);
|
||||
}
|
||||
|
||||
#ifdef HACKRF_ONE
|
||||
void enable_rf_power(void) {
|
||||
uint32_t i;
|
||||
|
||||
/* many short pulses to avoid one big voltage glitch */
|
||||
for (i = 0; i < 1000; i++) {
|
||||
gpio_clear(&gpio_vaa_disable);
|
||||
gpio_set(&gpio_vaa_disable);
|
||||
}
|
||||
gpio_clear(&gpio_vaa_disable);
|
||||
}
|
||||
|
||||
void disable_rf_power(void) {
|
||||
gpio_set(&gpio_vaa_disable);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef RAD1O
|
||||
void enable_rf_power(void) {
|
||||
gpio_set(&gpio_vaa_enable);
|
||||
}
|
||||
|
||||
void disable_rf_power(void) {
|
||||
gpio_clear(&gpio_vaa_enable);
|
||||
}
|
||||
#endif
|
||||
|
||||
void led_on(const led_t led) {
|
||||
gpio_set(&gpio_led[led]);
|
||||
}
|
||||
|
||||
void led_off(const led_t led) {
|
||||
gpio_clear(&gpio_led[led]);
|
||||
}
|
||||
|
||||
void led_toggle(const led_t led) {
|
||||
gpio_toggle(&gpio_led[led]);
|
||||
}
|
||||
|
||||
void hw_sync_enable(const hw_sync_mode_t hw_sync_mode){
|
||||
gpio_write(&gpio_hw_sync_enable, hw_sync_mode==1);
|
||||
}
|
||||
|
||||
void halt_and_flash(const uint32_t duration) {
|
||||
/* blink LED1, LED2, and LED3 */
|
||||
while (1)
|
||||
{
|
||||
led_on(LED1);
|
||||
led_on(LED2);
|
||||
led_on(LED3);
|
||||
delay(duration);
|
||||
led_off(LED1);
|
||||
led_off(LED2);
|
||||
led_off(LED3);
|
||||
delay(duration);
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,330 @@
|
||||
/*
|
||||
* Copyright 2012 Michael Ossmann <mike@ossmann.com>
|
||||
* Copyright 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||
* Copyright 2012 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __HACKRF_CORE_H
|
||||
#define __HACKRF_CORE_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "si5351c.h"
|
||||
#include "spi_ssp.h"
|
||||
|
||||
#include "max2837.h"
|
||||
#include "max5864.h"
|
||||
#include "mixer.h"
|
||||
#include "w25q80bv.h"
|
||||
#include "sgpio.h"
|
||||
#include "rf_path.h"
|
||||
#include "cpld_jtag.h"
|
||||
|
||||
/* hardware identification number */
|
||||
#define BOARD_ID_JAWBREAKER 1
|
||||
#define BOARD_ID_HACKRF_ONE 2
|
||||
#define BOARD_ID_RAD1O 3
|
||||
|
||||
#ifdef JAWBREAKER
|
||||
#define BOARD_ID BOARD_ID_JAWBREAKER
|
||||
#endif
|
||||
|
||||
#ifdef HACKRF_ONE
|
||||
#define BOARD_ID BOARD_ID_HACKRF_ONE
|
||||
#endif
|
||||
|
||||
#ifdef RAD1O
|
||||
#define BOARD_ID BOARD_ID_RAD1O
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SCU PinMux
|
||||
*/
|
||||
|
||||
/* GPIO Output PinMux */
|
||||
#define SCU_PINMUX_LED1 (P4_1) /* GPIO2[1] on P4_1 */
|
||||
#define SCU_PINMUX_LED2 (P4_2) /* GPIO2[2] on P4_2 */
|
||||
#define SCU_PINMUX_LED3 (P6_12) /* GPIO2[8] on P6_12 */
|
||||
#ifdef RAD1O
|
||||
#define SCU_PINMUX_LED4 (PB_6) /* GPIO5[26] on PB_6 */
|
||||
#endif
|
||||
|
||||
#define SCU_PINMUX_EN1V8 (P6_10) /* GPIO3[6] on P6_10 */
|
||||
|
||||
/* GPIO Input PinMux */
|
||||
#define SCU_PINMUX_BOOT0 (P1_1) /* GPIO0[8] on P1_1 */
|
||||
#define SCU_PINMUX_BOOT1 (P1_2) /* GPIO0[9] on P1_2 */
|
||||
#ifndef HACKRF_ONE
|
||||
#define SCU_PINMUX_BOOT2 (P2_8) /* GPIO5[7] on P2_8 */
|
||||
#define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */
|
||||
#endif
|
||||
#define SCU_PINMUX_PP_LCD_TE (P2_3) /* GPIO5[3] on P2_3 */
|
||||
#define SCU_PINMUX_PP_LCD_RDX (P2_4) /* GPIO5[4] on P2_4 */
|
||||
#define SCU_PINMUX_PP_UNUSED (P2_8) /* GPIO5[7] on P2_8 */
|
||||
#define SCU_PINMUX_PP_LCD_WRX (P2_9) /* GPIO1[10] on P2_9 */
|
||||
#define SCU_PINMUX_PP_DIR (P2_13) /* GPIO1[13] on P2_13 */
|
||||
|
||||
/* USB peripheral */
|
||||
#ifdef JAWBREAKER
|
||||
#define SCU_PINMUX_USB_LED0 (P6_8)
|
||||
#define SCU_PINMUX_USB_LED1 (P6_7)
|
||||
#endif
|
||||
|
||||
/* SSP1 Peripheral PinMux */
|
||||
#define SCU_SSP1_CIPO (P1_3) /* P1_3 */
|
||||
#define SCU_SSP1_COPI (P1_4) /* P1_4 */
|
||||
#define SCU_SSP1_SCK (P1_19) /* P1_19 */
|
||||
#define SCU_SSP1_CS (P1_20) /* P1_20 */
|
||||
|
||||
/* CPLD JTAG interface */
|
||||
#define SCU_PINMUX_CPLD_TDO (P9_5) /* GPIO5[18] */
|
||||
#define SCU_PINMUX_CPLD_TCK (P6_1) /* GPIO3[ 0] */
|
||||
#if (defined HACKRF_ONE || defined RAD1O)
|
||||
#define SCU_PINMUX_CPLD_TMS (P6_5) /* GPIO3[ 4] */
|
||||
#define SCU_PINMUX_CPLD_TDI (P6_2) /* GPIO3[ 1] */
|
||||
#else
|
||||
#define SCU_PINMUX_CPLD_TMS (P6_2) /* GPIO3[ 1] */
|
||||
#define SCU_PINMUX_CPLD_TDI (P6_5) /* GPIO3[ 4] */
|
||||
#endif
|
||||
|
||||
/* CPLD SGPIO interface */
|
||||
#define SCU_PINMUX_SGPIO0 (P0_0)
|
||||
#define SCU_PINMUX_SGPIO1 (P0_1)
|
||||
#define SCU_PINMUX_SGPIO2 (P1_15)
|
||||
#define SCU_PINMUX_SGPIO3 (P1_16)
|
||||
#define SCU_PINMUX_SGPIO4 (P6_3)
|
||||
#define SCU_PINMUX_SGPIO5 (P6_6)
|
||||
#define SCU_PINMUX_SGPIO6 (P2_2)
|
||||
#define SCU_PINMUX_SGPIO7 (P1_0)
|
||||
#if (defined JAWBREAKER || defined HACKRF_ONE || defined RAD1O)
|
||||
#define SCU_PINMUX_SGPIO8 (P9_6)
|
||||
#endif
|
||||
#define SCU_PINMUX_SGPIO9 (P4_3)
|
||||
#define SCU_PINMUX_SGPIO10 (P1_14)
|
||||
#define SCU_PINMUX_SGPIO11 (P1_17)
|
||||
#define SCU_PINMUX_SGPIO12 (P1_18)
|
||||
#define SCU_PINMUX_SGPIO13 (P4_8)
|
||||
#define SCU_PINMUX_SGPIO14 (P4_9)
|
||||
#define SCU_PINMUX_SGPIO15 (P4_10)
|
||||
|
||||
/* MAX2837 GPIO (XCVR_CTL) PinMux */
|
||||
#ifdef RAD1O
|
||||
#define SCU_XCVR_RXHP (P8_1) /* GPIO[] on P8_1 */
|
||||
#define SCU_XCVR_B6 (P8_2) /* GPIO[] on P8_2 */
|
||||
#define SCU_XCVR_B7 (P9_3) /* GPIO[] on P8_3 */
|
||||
#endif
|
||||
|
||||
#define SCU_XCVR_ENABLE (P4_6) /* GPIO2[6] on P4_6 */
|
||||
#define SCU_XCVR_RXENABLE (P4_5) /* GPIO2[5] on P4_5 */
|
||||
#define SCU_XCVR_TXENABLE (P4_4) /* GPIO2[4] on P4_4 */
|
||||
#define SCU_XCVR_CS (P1_20) /* GPIO0[15] on P1_20 */
|
||||
|
||||
/* MAX5864 SPI chip select (AD_CS) GPIO PinMux */
|
||||
#define SCU_AD_CS (P5_7) /* GPIO2[7] on P5_7 */
|
||||
|
||||
/* RFFC5071 GPIO serial interface PinMux */
|
||||
#if (defined JAWBREAKER || defined HACKRF_ONE)
|
||||
#define SCU_MIXER_ENX (P5_4) /* GPIO2[13] on P5_4 */
|
||||
#define SCU_MIXER_SCLK (P2_6) /* GPIO5[6] on P2_6 */
|
||||
#define SCU_MIXER_SDATA (P6_4) /* GPIO3[3] on P6_4 */
|
||||
#define SCU_MIXER_RESETX (P5_5) /* GPIO2[14] on P5_5 */
|
||||
#endif
|
||||
#ifdef RAD1O
|
||||
#define SCU_VCO_CE (P5_4) /* GPIO2[13] on P5_4 */
|
||||
#define SCU_VCO_SCLK (P2_6) /* GPIO5[6] on P2_6 */
|
||||
#define SCU_VCO_SDATA (P6_4) /* GPIO3[3] on P6_4 */
|
||||
#define SCU_VCO_LE (P5_5) /* GPIO2[14] on P5_5 */
|
||||
#define SCU_VCO_MUX (PB_5) /* GPIO5[25] on PB_5 */
|
||||
#define SCU_MIXER_EN (P6_8) /* GPIO5[16] on P6_8 */
|
||||
#define SCU_SYNT_RFOUT_EN (P6_9) /* GPIO3[5] on P6_9 */
|
||||
#endif
|
||||
|
||||
/* RF LDO control */
|
||||
#ifdef JAWBREAKER
|
||||
#define SCU_RF_LDO_ENABLE (P5_0) /* GPIO2[9] on P5_0 */
|
||||
#endif
|
||||
|
||||
/* RF supply (VAA) control */
|
||||
#ifdef HACKRF_ONE
|
||||
#define SCU_NO_VAA_ENABLE (P5_0) /* GPIO2[9] on P5_0 */
|
||||
#endif
|
||||
#ifdef RAD1O
|
||||
#define SCU_VAA_ENABLE (P5_0) /* GPIO2[9] on P5_0 */
|
||||
#endif
|
||||
|
||||
|
||||
/* SPI flash */
|
||||
#define SCU_SSP0_CIPO (P3_6)
|
||||
#define SCU_SSP0_COPI (P3_7)
|
||||
#define SCU_SSP0_SCK (P3_3)
|
||||
#define SCU_SSP0_CS (P3_8) /* GPIO5[11] on P3_8 */
|
||||
#define SCU_FLASH_HOLD (P3_4) /* GPIO1[14] on P3_4 */
|
||||
#define SCU_FLASH_WP (P3_5) /* GPIO1[15] on P3_5 */
|
||||
|
||||
/* RF switch control */
|
||||
#ifdef HACKRF_ONE
|
||||
#define SCU_HP (P4_0) /* GPIO2[0] on P4_0 */
|
||||
#define SCU_LP (P5_1) /* GPIO2[10] on P5_1 */
|
||||
#define SCU_TX_MIX_BP (P5_2) /* GPIO2[11] on P5_2 */
|
||||
#define SCU_NO_MIX_BYPASS (P1_7) /* GPIO1[0] on P1_7 */
|
||||
#define SCU_RX_MIX_BP (P5_3) /* GPIO2[12] on P5_3 */
|
||||
#define SCU_TX_AMP (P5_6) /* GPIO2[15] on P5_6 */
|
||||
#define SCU_TX (P6_7) /* GPIO5[15] on P6_7 */
|
||||
#define SCU_MIX_BYPASS (P6_8) /* GPIO5[16] on P6_8 */
|
||||
#define SCU_RX (P2_5) /* GPIO5[5] on P2_5 */
|
||||
#define SCU_NO_TX_AMP_PWR (P6_9) /* GPIO3[5] on P6_9 */
|
||||
#define SCU_AMP_BYPASS (P2_10) /* GPIO0[14] on P2_10 */
|
||||
#define SCU_RX_AMP (P2_11) /* GPIO1[11] on P2_11 */
|
||||
#define SCU_NO_RX_AMP_PWR (P2_12) /* GPIO1[12] on P2_12 */
|
||||
#endif
|
||||
#ifdef RAD1O
|
||||
#define SCU_BY_AMP (P1_7) /* GPIO1[0] on P1_7 */
|
||||
#define SCU_BY_AMP_N (P2_5) /* GPIO5[5] on P2_5 */
|
||||
#define SCU_TX_RX (P2_10) /* GPIO0[14] on P2_10 */
|
||||
#define SCU_TX_RX_N (P2_11) /* GPIO1[11] on P2_11 */
|
||||
#define SCU_BY_MIX (P2_12) /* GPIO1[12] on P2_12 */
|
||||
#define SCU_BY_MIX_N (P5_1) /* GPIO2[10] on P5_1 */
|
||||
#define SCU_LOW_HIGH_FILT (P5_2) /* GPIO2[11] on P5_2 */
|
||||
#define SCU_LOW_HIGH_FILT_N (P5_3) /* GPIO2[12] on P5_3 */
|
||||
#define SCU_TX_AMP (P5_6) /* GPIO2[15] on P5_6 */
|
||||
#define SCU_RX_LNA (P6_7) /* GPIO5[15] on P6_7 */
|
||||
#endif
|
||||
|
||||
#define SCU_PINMUX_PP_D0 (P7_0) /* GPIO3[8] */
|
||||
#define SCU_PINMUX_PP_D1 (P7_1) /* GPIO3[9] */
|
||||
#define SCU_PINMUX_PP_D2 (P7_2) /* GPIO3[10] */
|
||||
#define SCU_PINMUX_PP_D3 (P7_3) /* GPIO3[11] */
|
||||
#define SCU_PINMUX_PP_D4 (P7_4) /* GPIO3[12] */
|
||||
#define SCU_PINMUX_PP_D5 (P7_5) /* GPIO3[13] */
|
||||
#define SCU_PINMUX_PP_D6 (P7_6) /* GPIO3[14] */
|
||||
#define SCU_PINMUX_PP_D7 (P7_7) /* GPIO3[15] */
|
||||
/* TODO add other Pins */
|
||||
#define SCU_PINMUX_GPIO3_8 (P7_0) /* GPIO3[8] */
|
||||
#define SCU_PINMUX_GPIO3_9 (P7_1) /* GPIO3[9] */
|
||||
#define SCU_PINMUX_GPIO3_10 (P7_2) /* GPIO3[10] */
|
||||
#define SCU_PINMUX_GPIO3_11 (P7_3) /* GPIO3[11] */
|
||||
#define SCU_PINMUX_GPIO3_12 (P7_4) /* GPIO3[12] */
|
||||
#define SCU_PINMUX_GPIO3_13 (P7_5) /* GPIO3[13] */
|
||||
#define SCU_PINMUX_GPIO3_14 (P7_6) /* GPIO3[14] */
|
||||
#define SCU_PINMUX_GPIO3_15 (P7_7) /* GPIO3[15] */
|
||||
|
||||
#define SCU_PINMUX_PP_TDO (P1_5) /* GPIO1[8] */
|
||||
#define SCU_PINMUX_SD_POW (P1_5) /* GPIO1[8] */
|
||||
#define SCU_PINMUX_SD_CMD (P1_6) /* GPIO1[9] */
|
||||
#define SCU_PINMUX_PP_TMS (P1_8) /* GPIO1[1] */
|
||||
#define SCU_PINMUX_SD_VOLT0 (P1_8) /* GPIO1[1] */
|
||||
#define SCU_PINMUX_SD_DAT0 (P1_9) /* GPIO1[2] */
|
||||
#define SCU_PINMUX_SD_DAT1 (P1_10) /* GPIO1[3] */
|
||||
#define SCU_PINMUX_SD_DAT2 (P1_11) /* GPIO1[4] */
|
||||
#define SCU_PINMUX_SD_DAT3 (P1_12) /* GPIO1[5] */
|
||||
#define SCU_PINMUX_SD_CD (P1_13) /* GPIO1[6] */
|
||||
|
||||
#define SCU_PINMUX_PP_IO_STBX (P2_0) /* GPIO5[0] */
|
||||
#define SCU_PINMUX_PP_ADDR (P2_1) /* GPIO5[1] */
|
||||
#define SCU_PINMUX_U0_TXD (P2_0) /* GPIO5[0] */
|
||||
#define SCU_PINMUX_U0_RXD (P2_1) /* GPIO5[1] */
|
||||
|
||||
#define SCU_PINMUX_ISP (P2_7) /* GPIO0[7] */
|
||||
|
||||
#define SCU_PINMUX_GP_CLKIN (P4_7)
|
||||
|
||||
typedef enum {
|
||||
TRANSCEIVER_MODE_OFF = 0,
|
||||
TRANSCEIVER_MODE_RX = 1,
|
||||
TRANSCEIVER_MODE_TX = 2,
|
||||
TRANSCEIVER_MODE_SS = 3,
|
||||
TRANSCEIVER_MODE_CPLD_UPDATE = 4,
|
||||
TRANSCEIVER_MODE_RX_SWEEP = 5,
|
||||
} transceiver_mode_t;
|
||||
|
||||
typedef enum {
|
||||
HW_SYNC_MODE_OFF = 0,
|
||||
HW_SYNC_MODE_ON = 1,
|
||||
} hw_sync_mode_t;
|
||||
|
||||
typedef enum {
|
||||
CLOCK_SOURCE_HACKRF = 0,
|
||||
CLOCK_SOURCE_EXTERNAL = 1,
|
||||
CLOCK_SOURCE_PORTAPACK = 2,
|
||||
} clock_source_t;
|
||||
|
||||
void delay(uint32_t duration);
|
||||
|
||||
/* TODO: Hide these configurations */
|
||||
extern si5351c_driver_t clock_gen;
|
||||
extern const ssp_config_t ssp_config_w25q80bv;
|
||||
extern const ssp_config_t ssp_config_max2837;
|
||||
extern const ssp_config_t ssp_config_max5864;
|
||||
|
||||
extern max2837_driver_t max2837;
|
||||
extern max5864_driver_t max5864;
|
||||
extern mixer_driver_t mixer;
|
||||
extern w25q80bv_driver_t spi_flash;
|
||||
extern sgpio_config_t sgpio_config;
|
||||
extern rf_path_t rf_path;
|
||||
extern jtag_t jtag_cpld;
|
||||
extern i2c_bus_t i2c0;
|
||||
|
||||
void cpu_clock_init(void);
|
||||
void ssp1_set_mode_max2837(void);
|
||||
void ssp1_set_mode_max5864(void);
|
||||
|
||||
void pin_setup(void);
|
||||
|
||||
void enable_1v8_power(void);
|
||||
void disable_1v8_power(void);
|
||||
|
||||
bool sample_rate_frac_set(uint32_t rate_num, uint32_t rate_denom);
|
||||
bool sample_rate_set(const uint32_t sampling_rate_hz);
|
||||
bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz);
|
||||
|
||||
clock_source_t activate_best_clock_source(void);
|
||||
|
||||
#if (defined HACKRF_ONE || defined RAD1O)
|
||||
void enable_rf_power(void);
|
||||
void disable_rf_power(void);
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
LED1 = 0,
|
||||
LED2 = 1,
|
||||
LED3 = 2,
|
||||
LED4 = 3,
|
||||
} led_t;
|
||||
|
||||
void led_on(const led_t led);
|
||||
void led_off(const led_t led);
|
||||
void led_toggle(const led_t led);
|
||||
|
||||
void hw_sync_enable(const hw_sync_mode_t hw_sync_mode);
|
||||
|
||||
void halt_and_flash(const uint32_t duration);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HACKRF_CORE_H */
|
||||
@ -0,0 +1,102 @@
|
||||
/*
|
||||
* Copyright (C) 2019 Jared Boone, ShareBrained Technology, Inc.
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include "hackrf_ui.h"
|
||||
|
||||
#include "ui_portapack.h"
|
||||
#include "ui_rad1o.h"
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
#define UNUSED(x) (void)(x)
|
||||
|
||||
/* Stub functions for null UI function table */
|
||||
void hackrf_ui_init_null(void) { }
|
||||
void hackrf_ui_deinit_null(void) { }
|
||||
void hackrf_ui_set_frequency_null(uint64_t frequency) { UNUSED(frequency); }
|
||||
void hackrf_ui_set_sample_rate_null(uint32_t sample_rate) { UNUSED(sample_rate); }
|
||||
void hackrf_ui_set_direction_null(const rf_path_direction_t direction) { UNUSED(direction); }
|
||||
void hackrf_ui_set_filter_bw_null(uint32_t bandwidth) { UNUSED(bandwidth); }
|
||||
void hackrf_ui_set_lna_power_null(bool lna_on) { UNUSED(lna_on); }
|
||||
void hackrf_ui_set_bb_lna_gain_null(const uint32_t gain_db) { UNUSED(gain_db); }
|
||||
void hackrf_ui_set_bb_vga_gain_null(const uint32_t gain_db) { UNUSED(gain_db); }
|
||||
void hackrf_ui_set_bb_tx_vga_gain_null(const uint32_t gain_db) { UNUSED(gain_db); }
|
||||
void hackrf_ui_set_first_if_frequency_null(const uint64_t frequency) { UNUSED(frequency); }
|
||||
void hackrf_ui_set_filter_null(const rf_path_filter_t filter) { UNUSED(filter); }
|
||||
void hackrf_ui_set_antenna_bias_null(bool antenna_bias) { UNUSED(antenna_bias); }
|
||||
void hackrf_ui_set_clock_source_null(clock_source_t source) { UNUSED(source); }
|
||||
bool hackrf_ui_operacake_gpio_compatible_null(void) { return true; }
|
||||
|
||||
/* Null UI function table, used if there's no hardware UI detected. Eliminates the
|
||||
* need to check for null UI before calling a function in the table.
|
||||
*/
|
||||
static const hackrf_ui_t hackrf_ui_null = {
|
||||
&hackrf_ui_init_null,
|
||||
&hackrf_ui_deinit_null,
|
||||
&hackrf_ui_set_frequency_null,
|
||||
&hackrf_ui_set_sample_rate_null,
|
||||
&hackrf_ui_set_direction_null,
|
||||
&hackrf_ui_set_filter_bw_null,
|
||||
&hackrf_ui_set_lna_power_null,
|
||||
&hackrf_ui_set_bb_lna_gain_null,
|
||||
&hackrf_ui_set_bb_vga_gain_null,
|
||||
&hackrf_ui_set_bb_tx_vga_gain_null,
|
||||
&hackrf_ui_set_first_if_frequency_null,
|
||||
&hackrf_ui_set_filter_null,
|
||||
&hackrf_ui_set_antenna_bias_null,
|
||||
&hackrf_ui_set_clock_source_null,
|
||||
&hackrf_ui_operacake_gpio_compatible_null
|
||||
};
|
||||
|
||||
static const hackrf_ui_t* ui = NULL;
|
||||
static bool ui_enabled = true;
|
||||
|
||||
const hackrf_ui_t* hackrf_ui(void) {
|
||||
/* Detect on first use. If no UI hardware is detected, use a stub function table. */
|
||||
if( ui == NULL && ui_enabled ) {
|
||||
#ifdef HACKRF_ONE
|
||||
if( portapack_hackrf_ui_init ) {
|
||||
ui = portapack_hackrf_ui_init();
|
||||
}
|
||||
#endif
|
||||
#ifdef RAD1O
|
||||
if( rad1o_ui_setup ) {
|
||||
ui = rad1o_ui_setup();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
if( ui == NULL ) {
|
||||
ui = &hackrf_ui_null;
|
||||
}
|
||||
return ui;
|
||||
}
|
||||
|
||||
void hackrf_ui_set_enable(bool enabled) {
|
||||
if (ui_enabled != enabled) {
|
||||
ui_enabled = enabled;
|
||||
hackrf_ui()->deinit();
|
||||
ui = NULL;
|
||||
if (enabled) {
|
||||
hackrf_ui()->init();
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Jared Boone, ShareBrained Technology, Inc.
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef HACKRF_UI_H
|
||||
#define HACKRF_UI_H
|
||||
|
||||
#include <hackrf_core.h>
|
||||
#include <stdint.h>
|
||||
|
||||
typedef void (*hackrf_ui_init_fn)(void);
|
||||
typedef void (*hackrf_ui_deinit_fn)(void);
|
||||
typedef void (*hackrf_ui_set_frequency_fn)(uint64_t frequency);
|
||||
typedef void (*hackrf_ui_set_sample_rate_fn)(uint32_t sample_rate);
|
||||
typedef void (*hackrf_ui_set_direction_fn)(const rf_path_direction_t direction);
|
||||
typedef void (*hackrf_ui_set_filter_bw_fn)(uint32_t bandwidth);
|
||||
typedef void (*hackrf_ui_set_lna_power_fn)(bool lna_on);
|
||||
typedef void (*hackrf_ui_set_bb_lna_gain_fn)(const uint32_t gain_db);
|
||||
typedef void (*hackrf_ui_set_bb_vga_gain_fn)(const uint32_t gain_db);
|
||||
typedef void (*hackrf_ui_set_bb_tx_vga_gain_fn)(const uint32_t gain_db);
|
||||
typedef void (*hackrf_ui_set_first_if_frequency_fn)(const uint64_t frequency);
|
||||
typedef void (*hackrf_ui_set_filter_fn)(const rf_path_filter_t filter);
|
||||
typedef void (*hackrf_ui_set_antenna_bias_fn)(bool antenna_bias);
|
||||
typedef void (*hackrf_ui_set_clock_source_fn)(clock_source_t source);
|
||||
typedef bool (*hackrf_ui_operacake_gpio_compatible_fn)(void);
|
||||
|
||||
typedef struct {
|
||||
hackrf_ui_init_fn init;
|
||||
hackrf_ui_deinit_fn deinit;
|
||||
hackrf_ui_set_frequency_fn set_frequency;
|
||||
hackrf_ui_set_sample_rate_fn set_sample_rate;
|
||||
hackrf_ui_set_direction_fn set_direction;
|
||||
hackrf_ui_set_filter_bw_fn set_filter_bw;
|
||||
hackrf_ui_set_lna_power_fn set_lna_power;
|
||||
hackrf_ui_set_bb_lna_gain_fn set_bb_lna_gain;
|
||||
hackrf_ui_set_bb_vga_gain_fn set_bb_vga_gain;
|
||||
hackrf_ui_set_bb_tx_vga_gain_fn set_bb_tx_vga_gain;
|
||||
hackrf_ui_set_first_if_frequency_fn set_first_if_frequency;
|
||||
hackrf_ui_set_filter_fn set_filter;
|
||||
hackrf_ui_set_antenna_bias_fn set_antenna_bias;
|
||||
hackrf_ui_set_clock_source_fn set_clock_source;
|
||||
hackrf_ui_operacake_gpio_compatible_fn operacake_gpio_compatible;
|
||||
} hackrf_ui_t;
|
||||
|
||||
/* TODO: Lame hack to know that PortaPack was detected.
|
||||
* In the future, whatever UI was detected will be returned here,
|
||||
* or NULL if no UI was detected.
|
||||
*/
|
||||
const hackrf_ui_t* hackrf_ui(void);
|
||||
void hackrf_ui_set_enable(bool);
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include "i2c_bus.h"
|
||||
|
||||
void i2c_bus_start(i2c_bus_t* const bus, const void* const config) {
|
||||
bus->start(bus, config);
|
||||
}
|
||||
|
||||
void i2c_bus_stop(i2c_bus_t* const bus) {
|
||||
bus->stop(bus);
|
||||
}
|
||||
|
||||
void i2c_bus_transfer(
|
||||
i2c_bus_t* const bus,
|
||||
const uint_fast8_t peripheral_address,
|
||||
const uint8_t* const tx, const size_t tx_count,
|
||||
uint8_t* const rx, const size_t rx_count
|
||||
) {
|
||||
bus->transfer(bus, peripheral_address, tx, tx_count, rx, rx_count);
|
||||
}
|
||||
@ -0,0 +1,52 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __I2C_BUS_H__
|
||||
#define __I2C_BUS_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
struct i2c_bus_t;
|
||||
typedef struct i2c_bus_t i2c_bus_t;
|
||||
|
||||
struct i2c_bus_t {
|
||||
void* const obj;
|
||||
void (*start)(i2c_bus_t* const bus, const void* const config);
|
||||
void (*stop)(i2c_bus_t* const bus);
|
||||
void (*transfer)(
|
||||
i2c_bus_t* const bus,
|
||||
const uint_fast8_t peripheral_address,
|
||||
const uint8_t* const tx, const size_t tx_count,
|
||||
uint8_t* const rx, const size_t rx_count
|
||||
);
|
||||
};
|
||||
|
||||
void i2c_bus_start(i2c_bus_t* const bus, const void* const config);
|
||||
void i2c_bus_stop(i2c_bus_t* const bus);
|
||||
void i2c_bus_transfer(
|
||||
i2c_bus_t* const bus,
|
||||
const uint_fast8_t peripheral_address,
|
||||
const uint8_t* const tx, const size_t tx_count,
|
||||
uint8_t* const rx, const size_t rx_count
|
||||
);
|
||||
|
||||
#endif/*__I2C_BUS_H__*/
|
||||
@ -0,0 +1,79 @@
|
||||
/*
|
||||
* Copyright 2012 Michael Ossmann <mike@ossmann.com>
|
||||
* Copyright 2012 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include "i2c_lpc.h"
|
||||
|
||||
#include <libopencm3/lpc43xx/i2c.h>
|
||||
|
||||
/* FIXME return i2c0 status from each function */
|
||||
|
||||
void i2c_lpc_start(i2c_bus_t* const bus, const void* const _config) {
|
||||
const i2c_lpc_config_t* const config = _config;
|
||||
|
||||
const uint32_t port = (uint32_t)bus->obj;
|
||||
i2c_init(port, config->duty_cycle_count);
|
||||
}
|
||||
|
||||
void i2c_lpc_stop(i2c_bus_t* const bus) {
|
||||
const uint32_t port = (uint32_t)bus->obj;
|
||||
i2c_disable(port);
|
||||
}
|
||||
|
||||
void i2c_lpc_transfer(i2c_bus_t* const bus,
|
||||
const uint_fast8_t peripheral_address,
|
||||
const uint8_t* const data_tx, const size_t count_tx,
|
||||
uint8_t* const data_rx, const size_t count_rx
|
||||
) {
|
||||
const uint32_t port = (uint32_t)bus->obj;
|
||||
size_t i;
|
||||
bool ack = false;
|
||||
if (data_tx && (count_tx > 0)) {
|
||||
i2c_tx_start(port);
|
||||
i2c_tx_byte(port, (peripheral_address << 1) | I2C_WRITE);
|
||||
for(i=0; i<count_tx; i++) {
|
||||
i2c_tx_byte(port, data_tx[i]);
|
||||
}
|
||||
}
|
||||
|
||||
if (data_rx && (count_rx > 0)) {
|
||||
i2c_tx_start(port);
|
||||
i2c_tx_byte(port, (peripheral_address << 1) | I2C_READ);
|
||||
for(i=0; i<count_rx; i++) {
|
||||
/* ACK each byte except the last */
|
||||
ack = (i!=count_rx-1);
|
||||
data_rx[i] = i2c_rx_byte(port, ack);
|
||||
}
|
||||
}
|
||||
|
||||
i2c_stop(port);
|
||||
}
|
||||
|
||||
bool i2c_probe(i2c_bus_t* const bus, const uint_fast8_t device_address) {
|
||||
const uint32_t port = (uint32_t)bus->obj;
|
||||
|
||||
i2c_tx_start(port);
|
||||
i2c_tx_byte(port, (device_address << 1) | I2C_WRITE);
|
||||
const bool detected = (I2C_STAT(port) == 0x18);
|
||||
i2c_stop(port);
|
||||
|
||||
return detected;
|
||||
}
|
||||
@ -0,0 +1,44 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __I2C_LPC_H__
|
||||
#define __I2C_LPC_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "i2c_bus.h"
|
||||
|
||||
typedef struct i2c_lpc_config_t {
|
||||
const uint16_t duty_cycle_count;
|
||||
} i2c_lpc_config_t;
|
||||
|
||||
void i2c_lpc_start(i2c_bus_t* const bus, const void* const config);
|
||||
void i2c_lpc_stop(i2c_bus_t* const bus);
|
||||
void i2c_lpc_transfer(i2c_bus_t* const bus,
|
||||
const uint_fast8_t peripheral_address,
|
||||
const uint8_t* const data_tx, const size_t count_tx,
|
||||
uint8_t* const data_rx, const size_t count_rx
|
||||
);
|
||||
bool i2c_probe(i2c_bus_t* const bus, const uint_fast8_t device_address);
|
||||
|
||||
#endif/*__I2C_LPC_H__*/
|
||||
@ -0,0 +1,23 @@
|
||||
# Copyright 2013 Jared Boone <jared@sharebrained.com>
|
||||
#
|
||||
# This file is part of HackRF.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; see the file COPYING. If not, write to
|
||||
# the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
# Boston, MA 02110-1301, USA.
|
||||
|
||||
.data
|
||||
.section .m0_bin, "ax"
|
||||
|
||||
.incbin "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}_m0.bin"
|
||||
@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright 2013 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
int main() {
|
||||
while(1) {
|
||||
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,349 @@
|
||||
/*
|
||||
* Copyright 2012 Will Code? (TODO: Proper attribution)
|
||||
* Copyright 2014 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
/*
|
||||
* 'gcc -DTEST -DDEBUG -O2 -o test max2837.c' prints out what test
|
||||
* program would do if it had a real spi library
|
||||
*
|
||||
* 'gcc -DTEST -DBUS_PIRATE -O2 -o test max2837.c' prints out bus
|
||||
* pirate commands to do the same thing.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include "max2837.h"
|
||||
#include "max2837_regs.def" // private register def macros
|
||||
|
||||
/* Default register values. */
|
||||
static const uint16_t max2837_regs_default[MAX2837_NUM_REGS] = {
|
||||
0x150, /* 0 */
|
||||
0x002, /* 1 */
|
||||
0x1f4, /* 2 */
|
||||
0x1b9, /* 3 */
|
||||
0x00a, /* 4 */
|
||||
0x080, /* 5 */
|
||||
0x006, /* 6 */
|
||||
0x000, /* 7 */
|
||||
0x080, /* 8 */
|
||||
0x018, /* 9 */
|
||||
0x058, /* 10 */
|
||||
0x016, /* 11 */
|
||||
0x24f, /* 12 */
|
||||
0x150, /* 13 */
|
||||
0x1c5, /* 14 */
|
||||
0x081, /* 15 */
|
||||
0x01c, /* 16 */
|
||||
0x155, /* 17 */
|
||||
0x155, /* 18 */
|
||||
0x153, /* 19 */
|
||||
0x241, /* 20 */
|
||||
/*
|
||||
* Charge Pump Common Mode Enable bit (0) of register 21 must be set or TX
|
||||
* does not work. Page 1 of the SPI doc says not to set it (0x02c), but
|
||||
* page 21 says it should be set by default (0x02d).
|
||||
*/
|
||||
0x02d, /* 21 */
|
||||
0x1a9, /* 22 */
|
||||
0x24f, /* 23 */
|
||||
0x180, /* 24 */
|
||||
0x100, /* 25 */
|
||||
0x3ca, /* 26 */
|
||||
0x3e3, /* 27 */
|
||||
0x0c0, /* 28 */
|
||||
0x3f0, /* 29 */
|
||||
0x080, /* 30 */
|
||||
0x000 }; /* 31 */
|
||||
|
||||
/* Set up all registers according to defaults specified in docs. */
|
||||
static void max2837_init(max2837_driver_t* const drv)
|
||||
{
|
||||
drv->target_init(drv);
|
||||
max2837_set_mode(drv, MAX2837_MODE_SHUTDOWN);
|
||||
|
||||
memcpy(drv->regs, max2837_regs_default, sizeof(drv->regs));
|
||||
drv->regs_dirty = 0xffffffff;
|
||||
|
||||
/* Write default register values to chip. */
|
||||
max2837_regs_commit(drv);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up pins for GPIO and SPI control, configure SSP peripheral for SPI, and
|
||||
* set our own default register configuration.
|
||||
*/
|
||||
void max2837_setup(max2837_driver_t* const drv)
|
||||
{
|
||||
max2837_init(drv);
|
||||
|
||||
/* Use SPI control instead of B1-B7 pins for gain settings. */
|
||||
set_MAX2837_TXVGA_GAIN_SPI_EN(drv, 1);
|
||||
set_MAX2837_TXVGA_GAIN_MSB_SPI_EN(drv, 1);
|
||||
//set_MAX2837_TXVGA_GAIN(0x3f); /* maximum attenuation */
|
||||
set_MAX2837_TXVGA_GAIN(drv, 0x00); /* minimum attenuation */
|
||||
set_MAX2837_VGAMUX_enable(drv, 1);
|
||||
set_MAX2837_VGA_EN(drv, 1);
|
||||
set_MAX2837_HPC_RXGAIN_EN(drv, 0);
|
||||
set_MAX2837_HPC_STOP(drv, MAX2837_STOP_1K);
|
||||
set_MAX2837_LNAgain_SPI_EN(drv, 1);
|
||||
set_MAX2837_LNAgain(drv, MAX2837_LNAgain_MAX); /* maximum gain */
|
||||
set_MAX2837_VGAgain_SPI_EN(drv, 1);
|
||||
set_MAX2837_VGA(drv, 0x18); /* reasonable gain for noisy 2.4GHz environment */
|
||||
|
||||
/* maximum rx output common-mode voltage */
|
||||
set_MAX2837_BUFF_VCM(drv, MAX2837_BUFF_VCM_1_25);
|
||||
|
||||
/* configure baseband filter for 8 MHz TX */
|
||||
set_MAX2837_LPF_EN(drv, 1);
|
||||
set_MAX2837_ModeCtrl(drv, MAX2837_ModeCtrl_RxLPF);
|
||||
set_MAX2837_FT(drv, MAX2837_FT_5M);
|
||||
|
||||
max2837_regs_commit(drv);
|
||||
}
|
||||
|
||||
static uint16_t max2837_read(max2837_driver_t* const drv, uint8_t r) {
|
||||
uint16_t value = (1 << 15) | (r << 10);
|
||||
spi_bus_transfer(drv->bus, &value, 1);
|
||||
return value & 0x3ff;
|
||||
}
|
||||
|
||||
static void max2837_write(max2837_driver_t* const drv, uint8_t r, uint16_t v) {
|
||||
uint16_t value = (r << 10) | (v & 0x3ff);
|
||||
spi_bus_transfer(drv->bus, &value, 1);
|
||||
}
|
||||
|
||||
uint16_t max2837_reg_read(max2837_driver_t* const drv, uint8_t r)
|
||||
{
|
||||
if ((drv->regs_dirty >> r) & 0x1) {
|
||||
drv->regs[r] = max2837_read(drv, r);
|
||||
};
|
||||
return drv->regs[r];
|
||||
}
|
||||
|
||||
void max2837_reg_write(max2837_driver_t* const drv, uint8_t r, uint16_t v)
|
||||
{
|
||||
drv->regs[r] = v;
|
||||
max2837_write(drv, r, v);
|
||||
MAX2837_REG_SET_CLEAN(drv, r);
|
||||
}
|
||||
|
||||
static inline void max2837_reg_commit(max2837_driver_t* const drv, uint8_t r)
|
||||
{
|
||||
max2837_reg_write(drv, r, drv->regs[r]);
|
||||
}
|
||||
|
||||
void max2837_regs_commit(max2837_driver_t* const drv)
|
||||
{
|
||||
int r;
|
||||
for(r = 0; r < MAX2837_NUM_REGS; r++) {
|
||||
if ((drv->regs_dirty >> r) & 0x1) {
|
||||
max2837_reg_commit(drv, r);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void max2837_set_mode(max2837_driver_t* const drv, const max2837_mode_t new_mode) {
|
||||
drv->set_mode(drv, new_mode);
|
||||
}
|
||||
|
||||
max2837_mode_t max2837_mode(max2837_driver_t* const drv) {
|
||||
return drv->mode;
|
||||
}
|
||||
|
||||
void max2837_start(max2837_driver_t* const drv)
|
||||
{
|
||||
set_MAX2837_EN_SPI(drv, 1);
|
||||
max2837_regs_commit(drv);
|
||||
max2837_set_mode(drv, MAX2837_MODE_STANDBY);
|
||||
}
|
||||
|
||||
void max2837_tx(max2837_driver_t* const drv)
|
||||
{
|
||||
set_MAX2837_ModeCtrl(drv, MAX2837_ModeCtrl_TxLPF);
|
||||
max2837_regs_commit(drv);
|
||||
max2837_set_mode(drv, MAX2837_MODE_TX);
|
||||
}
|
||||
|
||||
void max2837_rx(max2837_driver_t* const drv)
|
||||
{
|
||||
set_MAX2837_ModeCtrl(drv, MAX2837_ModeCtrl_RxLPF);
|
||||
max2837_regs_commit(drv);
|
||||
max2837_set_mode(drv, MAX2837_MODE_RX);
|
||||
}
|
||||
|
||||
void max2837_stop(max2837_driver_t* const drv)
|
||||
{
|
||||
set_MAX2837_EN_SPI(drv, 0);
|
||||
max2837_regs_commit(drv);
|
||||
max2837_set_mode(drv, MAX2837_MODE_SHUTDOWN);
|
||||
}
|
||||
|
||||
void max2837_set_frequency(max2837_driver_t* const drv, uint32_t freq)
|
||||
{
|
||||
uint8_t band;
|
||||
uint8_t lna_band;
|
||||
uint32_t div_frac;
|
||||
uint32_t div_int;
|
||||
uint32_t div_rem;
|
||||
uint32_t div_cmp;
|
||||
int i;
|
||||
|
||||
/* Select band. Allow tuning outside specified bands. */
|
||||
if (freq < 2400000000U) {
|
||||
band = MAX2837_LOGEN_BSW_2_3;
|
||||
lna_band = MAX2837_LNAband_2_4;
|
||||
}
|
||||
else if (freq < 2500000000U) {
|
||||
band = MAX2837_LOGEN_BSW_2_4;
|
||||
lna_band = MAX2837_LNAband_2_4;
|
||||
}
|
||||
else if (freq < 2600000000U) {
|
||||
band = MAX2837_LOGEN_BSW_2_5;
|
||||
lna_band = MAX2837_LNAband_2_6;
|
||||
}
|
||||
else {
|
||||
band = MAX2837_LOGEN_BSW_2_6;
|
||||
lna_band = MAX2837_LNAband_2_6;
|
||||
}
|
||||
|
||||
/* ASSUME 40MHz PLL. Ratio = F*(4/3)/40,000,000 = F/30,000,000 */
|
||||
div_int = freq / 30000000;
|
||||
div_rem = freq % 30000000;
|
||||
div_frac = 0;
|
||||
div_cmp = 30000000;
|
||||
for( i = 0; i < 20; i++) {
|
||||
div_frac <<= 1;
|
||||
div_cmp >>= 1;
|
||||
if (div_rem > div_cmp) {
|
||||
div_frac |= 0x1;
|
||||
div_rem -= div_cmp;
|
||||
}
|
||||
}
|
||||
|
||||
/* Band settings */
|
||||
set_MAX2837_LOGEN_BSW(drv, band);
|
||||
set_MAX2837_LNAband(drv, lna_band);
|
||||
|
||||
/* Write order matters here, so commit INT and FRAC_HI before
|
||||
* committing FRAC_LO, which is the trigger for VCO
|
||||
* auto-select. TODO - it's cleaner this way, but it would be
|
||||
* faster to explicitly commit the registers explicitly so the
|
||||
* dirty bits aren't scanned twice. */
|
||||
set_MAX2837_SYN_INT(drv, div_int);
|
||||
set_MAX2837_SYN_FRAC_HI(drv, (div_frac >> 10) & 0x3ff);
|
||||
max2837_regs_commit(drv);
|
||||
set_MAX2837_SYN_FRAC_LO(drv, div_frac & 0x3ff);
|
||||
max2837_regs_commit(drv);
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
uint32_t bandwidth_hz;
|
||||
uint32_t ft;
|
||||
} max2837_ft_t;
|
||||
|
||||
static const max2837_ft_t max2837_ft[] = {
|
||||
{ 1750000, MAX2837_FT_1_75M },
|
||||
{ 2500000, MAX2837_FT_2_5M },
|
||||
{ 3500000, MAX2837_FT_3_5M },
|
||||
{ 5000000, MAX2837_FT_5M },
|
||||
{ 5500000, MAX2837_FT_5_5M },
|
||||
{ 6000000, MAX2837_FT_6M },
|
||||
{ 7000000, MAX2837_FT_7M },
|
||||
{ 8000000, MAX2837_FT_8M },
|
||||
{ 9000000, MAX2837_FT_9M },
|
||||
{ 10000000, MAX2837_FT_10M },
|
||||
{ 12000000, MAX2837_FT_12M },
|
||||
{ 14000000, MAX2837_FT_14M },
|
||||
{ 15000000, MAX2837_FT_15M },
|
||||
{ 20000000, MAX2837_FT_20M },
|
||||
{ 24000000, MAX2837_FT_24M },
|
||||
{ 28000000, MAX2837_FT_28M },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
uint32_t max2837_set_lpf_bandwidth(max2837_driver_t* const drv, const uint32_t bandwidth_hz) {
|
||||
const max2837_ft_t* p = max2837_ft;
|
||||
while( p->bandwidth_hz != 0 ) {
|
||||
if( p->bandwidth_hz >= bandwidth_hz ) {
|
||||
break;
|
||||
}
|
||||
p++;
|
||||
}
|
||||
|
||||
if( p->bandwidth_hz != 0 ) {
|
||||
set_MAX2837_FT(drv, p->ft);
|
||||
max2837_regs_commit(drv);
|
||||
}
|
||||
|
||||
return p->bandwidth_hz;
|
||||
}
|
||||
|
||||
bool max2837_set_lna_gain(max2837_driver_t* const drv, const uint32_t gain_db) {
|
||||
uint16_t val;
|
||||
switch(gain_db){
|
||||
case 40:
|
||||
val = MAX2837_LNAgain_MAX;
|
||||
break;
|
||||
case 32:
|
||||
val = MAX2837_LNAgain_M8;
|
||||
break;
|
||||
case 24:
|
||||
val = MAX2837_LNAgain_M16;
|
||||
break;
|
||||
case 16:
|
||||
val = MAX2837_LNAgain_M24;
|
||||
break;
|
||||
case 8:
|
||||
val = MAX2837_LNAgain_M32;
|
||||
break;
|
||||
case 0:
|
||||
val = MAX2837_LNAgain_M40;
|
||||
break;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
set_MAX2837_LNAgain(drv, val);
|
||||
max2837_reg_commit(drv, 1);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool max2837_set_vga_gain(max2837_driver_t* const drv, const uint32_t gain_db) {
|
||||
if( (gain_db & 0x1) || gain_db > 62)/* 0b11111*2 */
|
||||
return false;
|
||||
|
||||
set_MAX2837_VGA(drv, 31-(gain_db >> 1) );
|
||||
max2837_reg_commit(drv, 5);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool max2837_set_txvga_gain(max2837_driver_t* const drv, const uint32_t gain_db) {
|
||||
uint16_t val=0;
|
||||
if(gain_db <16){
|
||||
val = 31-gain_db;
|
||||
val |= (1 << 5); // bit6: 16db
|
||||
} else{
|
||||
val = 31-(gain_db-16);
|
||||
}
|
||||
|
||||
set_MAX2837_TXVGA_GAIN(drv, val);
|
||||
max2837_reg_commit(drv, 29);
|
||||
return true;
|
||||
}
|
||||
@ -0,0 +1,92 @@
|
||||
/*
|
||||
* Copyright 2012 Will Code? (TODO: Proper attribution)
|
||||
* Copyright 2014 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __MAX2837_H
|
||||
#define __MAX2837_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "gpio.h"
|
||||
#include "spi_bus.h"
|
||||
|
||||
/* 32 registers, each containing 10 bits of data. */
|
||||
#define MAX2837_NUM_REGS 32
|
||||
#define MAX2837_DATA_REGS_MAX_VALUE 1024
|
||||
|
||||
typedef enum {
|
||||
MAX2837_MODE_SHUTDOWN,
|
||||
MAX2837_MODE_STANDBY,
|
||||
MAX2837_MODE_TX,
|
||||
MAX2837_MODE_RX
|
||||
} max2837_mode_t;
|
||||
|
||||
struct max2837_driver_t;
|
||||
typedef struct max2837_driver_t max2837_driver_t;
|
||||
|
||||
struct max2837_driver_t {
|
||||
spi_bus_t* const bus;
|
||||
gpio_t gpio_enable;
|
||||
gpio_t gpio_rx_enable;
|
||||
gpio_t gpio_tx_enable;
|
||||
void (*target_init)(max2837_driver_t* const drv);
|
||||
void (*set_mode)(max2837_driver_t* const drv, const max2837_mode_t new_mode);
|
||||
max2837_mode_t mode;
|
||||
uint16_t regs[MAX2837_NUM_REGS];
|
||||
uint32_t regs_dirty;
|
||||
};
|
||||
|
||||
/* Initialize chip. */
|
||||
extern void max2837_setup(max2837_driver_t* const drv);
|
||||
|
||||
/* Read a register via SPI. Save a copy to memory and return
|
||||
* value. Mark clean. */
|
||||
extern uint16_t max2837_reg_read(max2837_driver_t* const drv, uint8_t r);
|
||||
|
||||
/* Write value to register via SPI and save a copy to memory. Mark
|
||||
* clean. */
|
||||
extern void max2837_reg_write(max2837_driver_t* const drv, uint8_t r, uint16_t v);
|
||||
|
||||
/* Write all dirty registers via SPI from memory. Mark all clean. Some
|
||||
* operations require registers to be written in a certain order. Use
|
||||
* provided routines for those operations. */
|
||||
extern void max2837_regs_commit(max2837_driver_t* const drv);
|
||||
|
||||
max2837_mode_t max2837_mode(max2837_driver_t* const drv);
|
||||
void max2837_set_mode(max2837_driver_t* const drv, const max2837_mode_t new_mode);
|
||||
|
||||
/* Turn on/off all chip functions. Does not control oscillator and CLKOUT */
|
||||
extern void max2837_start(max2837_driver_t* const drv);
|
||||
extern void max2837_stop(max2837_driver_t* const drv);
|
||||
|
||||
/* Set frequency in Hz. Frequency setting is a multi-step function
|
||||
* where order of register writes matters. */
|
||||
extern void max2837_set_frequency(max2837_driver_t* const drv, uint32_t freq);
|
||||
uint32_t max2837_set_lpf_bandwidth(max2837_driver_t* const drv, const uint32_t bandwidth_hz);
|
||||
bool max2837_set_lna_gain(max2837_driver_t* const drv, const uint32_t gain_db);
|
||||
bool max2837_set_vga_gain(max2837_driver_t* const drv, const uint32_t gain_db);
|
||||
bool max2837_set_txvga_gain(max2837_driver_t* const drv, const uint32_t gain_db);
|
||||
|
||||
extern void max2837_tx(max2837_driver_t* const drv);
|
||||
extern void max2837_rx(max2837_driver_t* const drv);
|
||||
|
||||
#endif // __MAX2837_H
|
||||
@ -0,0 +1,408 @@
|
||||
/* -*- mode: c -*- */
|
||||
|
||||
#ifndef __MAX2837_REGS_DEF
|
||||
#define __MAX2837_REGS_DEF
|
||||
|
||||
/* Generate static inline accessors that operate on the global
|
||||
* regs. Done this way to (1) allow defs to be scraped out and used
|
||||
* elsewhere, e.g. in scripts, (2) to avoid dealing with endian
|
||||
* (structs). This may be used in firmware, or on host predefined
|
||||
* register loads. */
|
||||
|
||||
#define MAX2837_REG_SET_CLEAN(_d, _r) (_d->regs_dirty &= ~(1UL<<_r))
|
||||
#define MAX2837_REG_SET_DIRTY(_d, _r) (_d->regs_dirty |= (1UL<<_r))
|
||||
|
||||
/* On set_, register is always set dirty, even if nothing
|
||||
* changed. This makes sure that write that have side effects,
|
||||
* e.g. frequency setting, are not skipped. */
|
||||
|
||||
/* n=name, r=regnum, o=offset (bits from LSB), l=length (bits) */
|
||||
#define __MREG__(n,r,o,l) \
|
||||
static inline uint16_t get_##n(max2837_driver_t* const _d) { \
|
||||
return (_d->regs[r] >> (o-l+1)) & ((1<<l)-1); \
|
||||
} \
|
||||
static inline void set_##n(max2837_driver_t* const _d, uint16_t v) { \
|
||||
_d->regs[r] &= ~(((1<<l)-1)<<(o-l+1)); \
|
||||
_d->regs[r] |= ((v&((1<<l)-1))<<(o-l+1)); \
|
||||
MAX2837_REG_SET_DIRTY(_d, r); \
|
||||
}
|
||||
|
||||
/* REG 0 */
|
||||
__MREG__(MAX2837_LNA_EN, 0,0,1)
|
||||
__MREG__(MAX2837_Mixer_EN, 0,1,1)
|
||||
__MREG__(MAX2837_RxLO_EN, 0,2,1)
|
||||
__MREG__(MAX2837_Lbias, 0,4,2)
|
||||
#define MAX2837_Lbias_LOWEST 0
|
||||
#define MAX2837_Lbias_NOMINAL 2
|
||||
#define MAX2837_Lbias_HIGHEST 3
|
||||
__MREG__(MAX2837_Mbias, 0,6,2)
|
||||
#define MAX2837_Mbias_LOWEST 0
|
||||
#define MAX2837_Mbias_NOMINAL 2
|
||||
#define MAX2837_Mbias_HIGHEST 3
|
||||
__MREG__(MAX2837_buf, 0,8,2)
|
||||
#define MAX2837_buf_LOWEST 0
|
||||
#define MAX2837_buf_NOMINAL 2
|
||||
#define MAX2837_buf_HIGHEST 3
|
||||
__MREG__(MAX2837_LNAband, 0,9,1)
|
||||
#define MAX2837_LNAband_2_4 0 // 2.3-2.5 GHz
|
||||
#define MAX2837_LNAband_2_6 1 // 2.5-2.7 GHz
|
||||
|
||||
/* REG 1 */
|
||||
__MREG__(MAX2837_LNAtune, 1,0,1)
|
||||
#define MAX2837_LNAtune_NOMINAL 0
|
||||
#define MAX2837_LNAtune_DOWN 1
|
||||
__MREG__(MAX2837_LNAde_Q,1,1,1)
|
||||
#define MAX2837_LNAde_Q_NOMINAL 0
|
||||
#define MAX2837_LNAde_Q_2DB 1
|
||||
__MREG__(MAX2837_LNAgain,1,4,3)
|
||||
#define MAX2837_LNAgain_MAX 0b000 // Pad in 8dB steps, bits reversed
|
||||
#define MAX2837_LNAgain_M8 0b100
|
||||
#define MAX2837_LNAgain_M16 0b010
|
||||
#define MAX2837_LNAgain_M24 0b110
|
||||
#define MAX2837_LNAgain_M32 0b011
|
||||
#define MAX2837_LNAgain_M40 0b111
|
||||
__MREG__(MAX2837_iqerr_trim,1,9,5)
|
||||
// 0b00000 = +4.0 degree phase error
|
||||
// 0b01111 = 0.0
|
||||
// 0b11111 = -4.0
|
||||
|
||||
/* REG 2 */
|
||||
__MREG__(MAX2837_LPF_EN,2,0,1)
|
||||
__MREG__(MAX2837_TxBB_EN,2,1,1)
|
||||
__MREG__(MAX2837_ModeCtrl,2,3,2)
|
||||
#define MAX2837_ModeCtrl_RxCalibration 0
|
||||
#define MAX2837_ModeCtrl_RxLPF 1
|
||||
#define MAX2837_ModeCtrl_TxLPF 2
|
||||
#define MAX2837_ModeCtrl_LPFTrim 3
|
||||
__MREG__(MAX2837_FT,2,7,4)
|
||||
#define MAX2837_FT_1_75M 0
|
||||
#define MAX2837_FT_2_5M 1
|
||||
#define MAX2837_FT_3_5M 2
|
||||
#define MAX2837_FT_5M 3
|
||||
#define MAX2837_FT_5_5M 4
|
||||
#define MAX2837_FT_6M 5
|
||||
#define MAX2837_FT_7M 6
|
||||
#define MAX2837_FT_8M 7
|
||||
#define MAX2837_FT_9M 8
|
||||
#define MAX2837_FT_10M 9
|
||||
#define MAX2837_FT_12M 10
|
||||
#define MAX2837_FT_14M 11
|
||||
#define MAX2837_FT_15M 12
|
||||
#define MAX2837_FT_20M 13
|
||||
#define MAX2837_FT_24M 14
|
||||
#define MAX2837_FT_28M 15
|
||||
__MREG__(MAX2837_dF,2,9,2)
|
||||
#define MAX2837_dF_M10 0b00 // -10%
|
||||
#define MAX2837_dF_NOMINAL 0b01
|
||||
#define MAX2837_dF_10 0b11 // +10%
|
||||
|
||||
/* REG 3 */
|
||||
__MREG__(MAX2837_PT_SPI,3,3,4) // slowest=1111 fastest=0000 nom=1001
|
||||
__MREG__(MAX2837_Bqd,3,6,3) // MSB doubles bias current, lower 2 25% each
|
||||
__MREG__(MAX2837_TxRPCM,3,9,3) // 000=1.00V, 0.05V steps, 111 not allowed
|
||||
|
||||
/* REG 4 */
|
||||
__MREG__(MAX2837_RP,4,1,2) // 20% steps, 00=lowest, 11=highest
|
||||
__MREG__(MAX2837_TxBuff,4,3,2) // 25% steps, 00=lowest, 11=highest
|
||||
__MREG__(MAX2837_VGA_EN,4,4,1)
|
||||
__MREG__(MAX2837_VGAMUX_enable,4,5,1)
|
||||
__MREG__(MAX2837_BUFF_Curr,4,7,2) // 250uA + 125uA steps
|
||||
__MREG__(MAX2837_BUFF_VCM,4,9,2) // VGA common mode
|
||||
#define MAX2837_BUFF_VCM_0_9 0 // 0.9V
|
||||
#define MAX2837_BUFF_VCM_1_0 1 // 1.0V
|
||||
#define MAX2837_BUFF_VCM_1_1 2 // 1.1V
|
||||
#define MAX2837_BUFF_VCM_1_25 3 // 1.25V
|
||||
|
||||
/* REG 5 */
|
||||
__MREG__(MAX2837_VGA,5,4,5) // max=00000, attenuation in 2dB steps
|
||||
__MREG__(MAX2837_sel_In1_In2,5,5,1)
|
||||
#define MAX2837_sel_In1_In2_RXVGA 0
|
||||
#define MAX2837_sel_In1_In2_TXAM 1
|
||||
__MREG__(MAX2837_turbo15n20,5,6,1)
|
||||
__MREG__(MAX2837_VGA_Curr,5,8,2) // 01=default, 00=-33%, 10=+33%, 11=+67%
|
||||
__MREG__(MAX2837_fuse_arm,5,9,1)
|
||||
|
||||
/* REG 6 */
|
||||
__MREG__(MAX2837_RSSI_EN,6,6,1) // enable RSSI
|
||||
__MREG__(MAX2837_RSSI_MUX,6,7,1)
|
||||
#define MAX2837_RSSI_MUX_RSSI 0
|
||||
#define MAX2837_RSSI_MUX_TEMP 1
|
||||
__MREG__(MAX2837_RSSI_MODE,6,8,1) // set to override RXHP pin
|
||||
__MREG__(MAX2837_LPF_MODE_SEL,6,9,1) // set to enable mode in reg 2 ModeCtrl
|
||||
|
||||
/* REG 7 is R/O */
|
||||
// D4:0 ts_adc (temp sensor)
|
||||
// D9:5 zeros or test outputs
|
||||
|
||||
/* REG 8 */
|
||||
__MREG__(MAX2837_LNAgain_SPI_EN,8,0,1) // set to override pin control of LNA
|
||||
__MREG__(MAX2837_VGAgain_SPI_EN,8,1,1) // set to override pin control of VGA
|
||||
__MREG__(MAX2837_EN_Bias_Trim,8,2,1) // route bias current to bondpad
|
||||
__MREG__(MAX2837_BIAS_TRIM_SPI,8,7,5) // down=00000, up=11111, nom=10000
|
||||
__MREG__(MAX2837_BIAS_TRIM_CNTRL,8,8,1) // enable BIAS_TRIM_SPI value
|
||||
__MREG__(MAX2837_RX_IQERR_SPI_EN,8,9,1) // ???
|
||||
|
||||
/* REG 9 */
|
||||
__MREG__(MAX2837_ts_adc_trigger,9,0,1) // temp sensor trigger (one shot)
|
||||
__MREG__(MAX2837_ts_en,9,1,1) // temp sensor enable (before trigger)
|
||||
__MREG__(MAX2837_LPFtrim_SPI_EN,9,2,1)
|
||||
__MREG__(MAX2837_DOUT_DRVH,9,3,1)
|
||||
#define MAX2837_DOUT_DRVH_1X 0
|
||||
#define MAX2837_DOUT_DRVH_4X 1
|
||||
__MREG__(MAX2837_DOUT_PU,9,4,1) // set to enable CMOS PU (default), else OD
|
||||
__MREG__(MAX2837_DOUT_SEL,9,7,3)
|
||||
#define MAX2837_DOUT_SEL_SPI 0 // default, SPI comm
|
||||
#define MAX2837_DOUT_SEL_PLL_LOCK_DETECT 1
|
||||
#define MAX2837_DOUT_SEL_VAS_TEST_OUT 2
|
||||
#define MAX2837_DOUT_SEL_HPFSM_TEST_OUT 3
|
||||
#define MAX2837_DOUT_SEL_LOGEN_TRIM_OUT 4
|
||||
#define MAX2837_DOUT_SEL_RX_FUSE_GASKET 5
|
||||
#define MAX2837_DOUT_SEL_TX_FUSE_GASKET 6
|
||||
#define MAX2837_DOUT_SEL_ZERO 7
|
||||
__MREG__(MAX2837_fuse_sh,9,8,1) // ???
|
||||
__MREG__(MAX2837_fuse_burn_gkt,9,9,1) // enable (don't)
|
||||
|
||||
/* REG 10 */
|
||||
__MREG__(MAX2837_TXCAL_GAIN,10,2,2) // 00=default, steps of +10dB
|
||||
__MREG__(MAX2837_TXCAL_V2I_FILT,10,5,3) // 000=+12%, 111=-16%, 011=default
|
||||
__MREG__(MAX2837_TX_BIAS_ADJ,10,7,2) // 00=-10%, 01=default, 10=+10%, 11=+20%
|
||||
|
||||
/* REG 11 */
|
||||
__MREG__(MAX2837_AMD_SPI_EN,11,0,1) // enable AM detector
|
||||
__MREG__(MAX2837_TXMXR_V2I_GAIN,11,4,4) // 0000=max, steps of -0.5dB
|
||||
|
||||
/* REG 12 */
|
||||
__MREG__(MAX2837_HPC_10M,12,1,2) // steps of 0.4uS (0.0-1.2)
|
||||
__MREG__(MAX2837_HPC_10M_GAIN,12,3,2) // steps of 0.4uS (0.0-1.2)
|
||||
__MREG__(MAX2837_HPC_600K,12,6,3) // steps of 0.8uS (0.0-4.8), 7=stay 1
|
||||
__MREG__(MAX2837_HPC_600K_GAIN,12,9,3) // steps of 0.8uS (0.0-4.8), 7=stay 1
|
||||
|
||||
/* REG 13 */
|
||||
__MREG__(MAX2837_HPC_100K,13,1,2) // steps of 3.2uS (0.0-9.6)
|
||||
__MREG__(MAX2837_HPC_100K_GAIN,13,3,2) // steps of 3.2uS (0.0-9.6)
|
||||
__MREG__(MAX2837_HPC_30K,13,5,2) // steps of 3.2uS (0.0-9.6)
|
||||
__MREG__(MAX2837_HPC_30K_GAIN,13,7,2) // steps of 3.2uS (0.0-9.6)
|
||||
__MREG__(MAX2837_HPC_1K,13,9,2) // steps of 3.2uS (0.0-9.6)
|
||||
|
||||
/* REG 14 */
|
||||
__MREG__(MAX2837_HPC_1K_GAIN,14,1,2) // steps of 3.2uS (0.0-9.6)
|
||||
__MREG__(MAX2837_HPC_DELAY,14,3,2) // steps of 0.2uS (0.0-0.6)
|
||||
__MREG__(MAX2837_HPC_STOP,14,5,2)
|
||||
#define MAX2837_STOP_100 0
|
||||
#define MAX2837_STOP_1K 1
|
||||
#define MAX2837_STOP_30K 2
|
||||
#define MAX2837_STOP_100K 3
|
||||
__MREG__(MAX2837_HPC_STOP_M2,14,7,2)
|
||||
#define MAX2837_STOP_M2_1K 0
|
||||
#define MAX2837_STOP_M2_30K 1
|
||||
#define MAX2837_STOP_M2_100K 2
|
||||
#define MAX2837_STOP_M2_600K 3
|
||||
__MREG__(MAX2837_HPC_RXGAIN_EN,14,8,1) // RXVGA HPFSM re-triggered by B7 & B6
|
||||
__MREG__(MAX2837_HPC_MODE,14,9,1) // use RXHP
|
||||
|
||||
/* REG 15 */
|
||||
__MREG__(MAX2837_HPC_DIVH,15,0,1)
|
||||
#define MAX2837_HPC_DIVH_20M 0
|
||||
#define MAX2837_HPC_DIVH_40M 1
|
||||
__MREG__(MAX2837_HPC_TST,15,5,5) // filter test modes ... see doc
|
||||
__MREG__(MAX2837_HPC_SEQ_BYP,15,6,1) // set to bypass programmed sequence
|
||||
__MREG__(MAX2837_DOUT_CSB_SEL,15,7,1) // set to tri state DOUT when CSB high
|
||||
|
||||
/* REG 16 */
|
||||
__MREG__(MAX2837_EN_SPI,16,0,1) // enable overall chip
|
||||
__MREG__(MAX2837_CAL_SPI,16,1,1) // enable calibration mode
|
||||
__MREG__(MAX2837_LOGEN_SPI_EN,16,2,1) // ???
|
||||
__MREG__(MAX2837_SYN_SPI_EN,16,3,1) // enable synthesizer
|
||||
__MREG__(MAX2837_VAS_SPI_EN,16,4,1) // enable VCO autoselect
|
||||
__MREG__(MAX2837_PADRV_SPI_EN,16,5,1) // enable power amp
|
||||
__MREG__(MAX2837_PADAC_SPI_EN,16,6,1) // enable power amp bias DAC always
|
||||
__MREG__(MAX2837_PADAC_TX_EN,16,7,1) // enable power amp bias only if TX pin
|
||||
__MREG__(MAX2837_TXMX_SPI_EN,16,8,1) // enable TX mixer
|
||||
__MREG__(MAX2837_TXLO_SPI_EN,16,9,1) // enable TX LO
|
||||
|
||||
/* REG 17 */
|
||||
__MREG__(MAX2837_SYN_FRAC_LO,17,9,10)
|
||||
|
||||
/* REG 18 */
|
||||
__MREG__(MAX2837_SYN_FRAC_HI,18,9,10)
|
||||
|
||||
/* REG 19 */
|
||||
__MREG__(MAX2837_SYN_INT,19,7,8)
|
||||
__MREG__(MAX2837_LOGEN_BSW,19,9,2)
|
||||
#define MAX2837_LOGEN_BSW_2_3 0 // 2300 - <2400 MHz
|
||||
#define MAX2837_LOGEN_BSW_2_4 1 // 2400 - <2500 MHz
|
||||
#define MAX2837_LOGEN_BSW_2_5 2 // 2500 - <2600 MHz
|
||||
#define MAX2837_LOGEN_BSW_2_6 3 // 2600 - <2700 MHz
|
||||
|
||||
/* REG 20 */
|
||||
__MREG__(MAX2837_SYN_MODE,20,0,1)
|
||||
#define MAX2837_SYN_MODE_INTEGER 0
|
||||
#define MAX2837_SYN_MODE_FRACTIONAL 1
|
||||
__MREG__(MAX2837_SYN_REF_DIV,20,2,2)
|
||||
#define MAX2837_SYN_REF_DIV_1 0
|
||||
#define MAX2837_SYN_REF_DIV_2 1
|
||||
#define MAX2837_SYN_REF_DIV_4 2
|
||||
#define MAX2837_SYN_REF_DIV_8 3
|
||||
__MREG__(MAX2837_SYN_CURRENT_,20,4,2)
|
||||
#define MAX2837_SYN_CURRENT_3_2_DIFF 0 // 3.2mA differential
|
||||
#define MAX2837_SYN_CURRENT_1_6_DIFF 1 // 1.6mA differential
|
||||
#define MAX2837_SYN_CURRENT_1_6_SINGLE 2 // 1.6mA single-ended
|
||||
#define MAX2837_SYN_CURRENT_0_8_SINGLE 3 // 0.8mA single-ended
|
||||
__MREG__(MAX2837_SYN_CLOCKOUT_DRIVE,20,5,1)
|
||||
#define MAX2837_SYN_CLOCKOUT_DRIVE_1X 0
|
||||
#define MAX2837_SYN_CLOCKOUT_DRIVE_4X 1
|
||||
__MREG__(MAX2837_SYN_TURBO_EN,20,6,1) // ???
|
||||
__MREG__(MAX2837_SYN_BIAS_SPI,20,7,1) // Use trim value below
|
||||
__MREG__(MAX2837_SYN_BIAS_TRIM,20,9,2) // 00=max 10=default 11=min
|
||||
|
||||
/* REG 21 */
|
||||
__MREG__(MAX2837_SYN_CP_COMMON_MODE_EN,21,0,1)
|
||||
__MREG__(MAX2837_SYN_PRESCALER_BIAS_BOOST,21,1,1) // 0=default 1=+20%
|
||||
__MREG__(MAX2837_SYN_CP_BETA_EN,21,2,1)
|
||||
__MREG__(MAX2837_SYN_SD_CLOCK_SEL,21,3,1)
|
||||
#define MAX2837_SYN_SD_CLOCK_PFD 0 // from PFD reset
|
||||
#define MAX2837_SYN_SD_CLOCK_PRE 1 // from prescaler
|
||||
__MREG__(MAX2837_SYN_CP_PULSE_WIDTH_ADJ,21,4,1) // 0=default 1=-20%
|
||||
__MREG__(MAX2837_SYN_CP_LIN_CUR,21,6,2) // +3% per step
|
||||
__MREG__(MAX2837_SYN_TEST_OUT,21,9,3) // high bit locks CP in test mode
|
||||
#define MAX2837_SYN_TEST_LOCK_DETECT 0b000
|
||||
#define MAX2837_SYN_TEST_SD 0b001
|
||||
#define MAX2837_SYN_TEST_REF_DIV 0b010
|
||||
#define MAX2837_SYN_TEST_MAIN_DIV 0b011
|
||||
#define MAX2837_SYN_TEST_CP_LO_Z_LOCK_DETECT 0b100
|
||||
#define MAX2837_SYN_TEST_CP_SOURCE_SD 0b101
|
||||
#define MAX2837_SYN_TEST_CP_SINK_REF_DIV 0b110
|
||||
#define MAX2837_SYN_TEST_CP_HI_Z_MAIN_DIV 0b111
|
||||
|
||||
/* REG 22 */
|
||||
__MREG__(MAX2837_VAS_EN,22,0,1) // select VCO subband by VAS, vs. reg
|
||||
__MREG__(MAX2837_VAS_RELOCK_SEL,22,1,1)
|
||||
#define MAX2837_VAS_RELOCK_SELECTED 0
|
||||
#define MAX2837_VAS_RELOCK_PRESENT 1
|
||||
__MREG__(MAX2837_VAS_DIV,22,4,3)
|
||||
#define MAX2837_VAS_CLK_DIV_8 0
|
||||
#define MAX2837_VAS_CLK_DIV_9 1
|
||||
#define MAX2837_VAS_CLK_DIV_10 2
|
||||
#define MAX2837_VAS_CLK_DIV_11 3
|
||||
#define MAX2837_VAS_CLK_DIV_12 4
|
||||
#define MAX2837_VAS_CLK_DIV_13 5
|
||||
#define MAX2837_VAS_CLK_DIV_14 6
|
||||
#define MAX2837_VAS_CLK_DIV_2 7
|
||||
__MREG__(MAX2837_VAS_DLY,22,6,2) // Delay = Txtal * VAS_DIV * VAS_DLY * 7
|
||||
#define MAX2837_VAS_DLY_16
|
||||
#define MAX2837_VAS_DLY_32
|
||||
#define MAX2837_VAS_DLY_64
|
||||
#define MAX2837_VAS_DLY_128
|
||||
__MREG__(MAX2837_VAS_TRIG_EN,22,7,1)
|
||||
__MREG__(MAX2837_VAS_ADE,22,8,1)
|
||||
__MREG__(MAX2837_VAS_ADL_SPI,22,9,1)
|
||||
|
||||
/* REG 23 */
|
||||
__MREG__(MAX2837_VAS_SPI,23,4,5) // subband selection default is center (15)
|
||||
__MREG__(MAX2837_XTAL_BIAS,23,6,2)
|
||||
#define MAX2837_XTAL_BIAS_240_20 0 // 240uA for 20MHz
|
||||
#define MAX2837_XTAL_BIAS_420_20 1
|
||||
#define MAX2837_XTAL_BIAS_600_40 2
|
||||
#define MAX2837_XTAL_BIAS_780_40 3
|
||||
__MREG__(MAX2837_XTAL_E2C_BIAS,23,7,1)
|
||||
#define MAX2837_XTAL_E2C_BIAS_360 0 // uA
|
||||
#define MAX2837_XTAL_E2C_BIAS_540 1
|
||||
__MREG__(MAX2837_VAS_SE,23,8,1)
|
||||
#define MAX2837_VAS_SE_DIFF 0
|
||||
#define MAX2837_VAS_SE_SINGLE 1
|
||||
__MREG__(MAX2837_VCO_SPI_EN,23,9,1) // set to override mode
|
||||
|
||||
/* REG 24 */
|
||||
__MREG__(MAX2837_XTAL_TUNE,24,6,7) // 0=max 127=min freq
|
||||
__MREG__(MAX2837_CLKOUT_PIN_EN,24,7,1)
|
||||
__MREG__(MAX2837_CLKOUT_DIV,24,8,1)
|
||||
#define MAX2837_CLKOUT_DIV_1 0
|
||||
#define MAX2837_CLKOUT_DIV_2 1
|
||||
__MREG__(MAX2837_XTAL_CORE_EN,24,9,1) // set to override mode
|
||||
|
||||
/* REG 25 */
|
||||
__MREG__(MAX2837_VCO_BIAS_SPI_EN,25,0,1) // enable override of vco bias trim
|
||||
__MREG__(MAX2837_VCO_BIAS,25,4,4) // 0b1000 nominal
|
||||
__MREG__(MAX2837_VCO_CMEN,25,5,1) // enable Miller capacitor
|
||||
__MREG__(MAX2837_VCO_PDET_TST,25,7,2) // peak detector test output select
|
||||
#define MAX2837_VCO_PDET_TST_NORMAL 0
|
||||
#define MAX2837_VCO_PDET_TST_PDOUT 1 // peak detector output
|
||||
#define MAX2837_VCO_PDET_TST_PDREF 2 // peak detector reference
|
||||
#define MAX2837_VCO_PDET_TST_TEMP 3 // VCO temperature sensor
|
||||
__MREG__(MAX2837_VCO_BUF_BIAS,25,9,2) // VCO buffer bias
|
||||
#define MAX2837_VCO_BUF_BIAS_800uA 0
|
||||
#define MAX2837_VCO_BUF_BIAS_1200uA 1 // default
|
||||
#define MAX2837_VCO_BUF_BIAS_1600uA 2
|
||||
#define MAX2837_VCO_BUF_BIAS_2000uA 3
|
||||
|
||||
/* REG 26 */
|
||||
__MREG__(MAX2837_LOGEN_BIAS1,26,1,2) // LOGEN emitter follower bias
|
||||
#define MAX2837_LOGEN_BIAS1_400u 0
|
||||
#define MAX2837_LOGEN_BIAS1_600u 1
|
||||
#define MAX2837_LOGEN_BIAS1_800u 2
|
||||
#define MAX2837_LOGEN_BIAS1_1000u 3
|
||||
__MREG__(MAX2837_LOGEN_BIAS2,26,2,1) // LOGEN RX/TX Gm bias
|
||||
#define MAX2837_LOGEN_BIAS2_DEFAULT 0 // default
|
||||
#define MAX2837_LOGEN_BIAS2_PLUS25 1 // +25%
|
||||
__MREG__(MAX2837_LOGEN_2GM,26,3,1) //
|
||||
__MREG__(MAX2837_LOGEN_TRIM1,26,4,1) // mixer tank trim enable
|
||||
__MREG__(MAX2837_LOGEN_TRIM2,26,5,1) // bandpass filter trim enable
|
||||
__MREG__(MAX2837_VAS_TST,26,9,4) // DOUT test signal select
|
||||
#define MAX2837_VAS_TST_VCO_BSW0 0 // VAS band select output (5 bits)
|
||||
#define MAX2837_VAS_TST_VCO_BSW1 1
|
||||
#define MAX2837_VAS_TST_VCO_BSW2 2
|
||||
#define MAX2837_VAS_TST_VCO_BSW3 3
|
||||
#define MAX2837_VAS_TST_VCO_BSW4 4
|
||||
#define MAX2837_VAS_TST_Vtune_ADC0 5 // VCO Vtune ADC output (3 bits)
|
||||
#define MAX2837_VAS_TST_Vtune_ADC1 6
|
||||
#define MAX2837_VAS_TST_Vtune_ADC2 7
|
||||
#define MAX2837_VAS_TST_VASA 8 // VAS accomplish (success)
|
||||
#define MAX2837_VAS_TST_VASE 9 // VAS end (success or gave up)
|
||||
#define MAX2837_VAS_TST_ZERO 15 // default
|
||||
|
||||
/* REG 27 */
|
||||
__MREG__(MAX2837_PADRV_BIAS,27,2,3) // PA driver bias (0-7), default 3
|
||||
__MREG__(MAX2837_PADRV_DOWN_SPI_EN,27,3,1) // PA drv down process select enable
|
||||
__MREG__(MAX2837_PADRV_DOWN,27,4,1) // PA driver down select
|
||||
#define MAX2837_PADRV_DOWN_DOWN 0
|
||||
#define MAX2837_PADRV_DOWN_UP 1 // default
|
||||
__MREG__(MAX2837_PADAC_IV,27,5,1) // PA DAC I/V output select
|
||||
#define MAX2837_PADAC_IV_VOLTAGE 0
|
||||
#define MAX2837_PADAC_IV_CURRENT 1 // default
|
||||
__MREG__(MAX2837_PADAC_VMODE,27,6,1) // set logic 0 or 1 for PADAC_IV out
|
||||
__MREG__(MAX2837_PADAC_DIV,27,7,1) // PA DAC clock divide ratio
|
||||
#define MAX2837_PADAC_DIV_20MHz 0
|
||||
#define MAX2837_PADAC_DIV_40MHz 1
|
||||
__MREG__(MAX2837_TXGATE_EN,27,8,1) // set to relock when TXOOL=1 or LD=0
|
||||
__MREG__(MAX2837_TXDCCORR_EN,27,9,1) // TX DC offset correction enable
|
||||
|
||||
/* REG 28 */
|
||||
__MREG__(MAX2837_PADAC_BIAS,28,5,6) // PADAC output current control, 5uA step
|
||||
__MREG__(MAX2837_PADAC_DLY,28,9,4) // PADAC turn-on delay control
|
||||
// 0,1 are both 0us
|
||||
// then 0.5us steps to 7.0us
|
||||
|
||||
/* REG 29 */
|
||||
__MREG__(MAX2837_TXVGA_GAIN_SPI_EN,29,0,1) // Enable SPI control of TXVGA gain
|
||||
__MREG__(MAX2837_TXVGA_GAIN_MSB_SPI_EN,29,1,1)
|
||||
__MREG__(MAX2837_TX_DCCORR_SPI_EN,29,2,1)
|
||||
__MREG__(MAX2837_FUSE_ARM,29,3,1) // Fuse burn enable
|
||||
__MREG__(MAX2837_TXVGA_GAIN,29,9,6) // 0 = min atten, 63 = max atten
|
||||
|
||||
/* REG 30 */
|
||||
__MREG__(MAX2837_TXLO_IQ,30,4,5)
|
||||
__MREG__(MAX2837_TXLO_IQ_SPI_EN,30,5,1)
|
||||
__MREG__(MAX2837_TXLO_BUFF_BIAS,30,7,2)
|
||||
#define MAX2837_TXLO_BUFF_BIAS_1_0mA 0
|
||||
#define MAX2837_TXLO_BUFF_BIAS_1_5mA 1
|
||||
#define MAX2837_TXLO_BUFF_BIAS_2_0mA 2 // default
|
||||
#define MAX2837_TXLO_BUFF_BIAS_2_5mA 3
|
||||
__MREG__(MAX2837_FUSE_GKT,30,8,1)
|
||||
__MREG__(MAX2837_FUSE_RTH,30,9,1)
|
||||
|
||||
/* REG 31 */
|
||||
// 0 -> 992/0uA correction, 15 -> 0/992uA correction ... if TX_DCCORR_SPI_EN
|
||||
__MREG__(MAX2837_TX_DCCORR_I,31,4,5)
|
||||
__MREG__(MAX2837_TX_DCCORR_Q,31,9,5)
|
||||
|
||||
#endif // __MAX2837_REGS_DEF
|
||||
@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Copyright 2012 Will Code? (TODO: Proper attribution)
|
||||
* Copyright 2014 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include "max2837_target.h"
|
||||
|
||||
#include <libopencm3/lpc43xx/scu.h>
|
||||
#include "hackrf_core.h"
|
||||
|
||||
void max2837_target_init(max2837_driver_t* const drv) {
|
||||
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
|
||||
scu_pinmux(SCU_SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
|
||||
scu_pinmux(SCU_SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
|
||||
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
|
||||
|
||||
scu_pinmux(SCU_XCVR_CS, SCU_GPIO_FAST);
|
||||
|
||||
/* Configure XCVR_CTL GPIO pins. */
|
||||
scu_pinmux(SCU_XCVR_ENABLE, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_XCVR_RXENABLE, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_XCVR_TXENABLE, SCU_GPIO_FAST);
|
||||
|
||||
/* Set GPIO pins as outputs. */
|
||||
gpio_output(drv->gpio_enable);
|
||||
gpio_output(drv->gpio_rx_enable);
|
||||
gpio_output(drv->gpio_tx_enable);
|
||||
}
|
||||
|
||||
void max2837_target_set_mode(max2837_driver_t* const drv, const max2837_mode_t new_mode) {
|
||||
/* MAX2837_MODE_SHUTDOWN:
|
||||
* All circuit blocks are powered down, except the 4-wire serial bus
|
||||
* and its internal programmable registers.
|
||||
*
|
||||
* MAX2837_MODE_STANDBY:
|
||||
* Used to enable the frequency synthesizer block while the rest of the
|
||||
* device is powered down. In this mode, PLL, VCO, and LO generator
|
||||
* are on, so that Tx or Rx modes can be quickly enabled from this mode.
|
||||
* These and other blocks can be selectively enabled in this mode.
|
||||
*
|
||||
* MAX2837_MODE_TX:
|
||||
* All Tx circuit blocks are powered on. The external PA is powered on
|
||||
* after a programmable delay using the on-chip PA bias DAC. The slow-
|
||||
* charging Rx circuits are in a precharged “idle-off” state for fast
|
||||
* Tx-to-Rx turnaround time.
|
||||
*
|
||||
* MAX2837_MODE_RX:
|
||||
* All Rx circuit blocks are powered on and active. Antenna signal is
|
||||
* applied; RF is downconverted, filtered, and buffered at Rx BB I and Q
|
||||
* outputs. The slow- charging Tx circuits are in a precharged “idle-off”
|
||||
* state for fast Rx-to-Tx turnaround time.
|
||||
*/
|
||||
gpio_write(drv->gpio_enable, new_mode != MAX2837_MODE_SHUTDOWN);
|
||||
gpio_write(drv->gpio_rx_enable, new_mode == MAX2837_MODE_RX);
|
||||
gpio_write(drv->gpio_tx_enable, new_mode == MAX2837_MODE_TX);
|
||||
drv->mode = new_mode;
|
||||
}
|
||||
@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright 2012 Will Code? (TODO: Proper attribution)
|
||||
* Copyright 2014 Jared Boone <jared@sharebrained.com>
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __MAX2837_TARGET_H
|
||||
#define __MAX2837_TARGET_H
|
||||
|
||||
#include "max2837.h"
|
||||
|
||||
void max2837_target_init(max2837_driver_t* const drv);
|
||||
void max2837_target_set_mode(max2837_driver_t* const drv, const max2837_mode_t new_mode);
|
||||
|
||||
#endif // __MAX2837_TARGET_H
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user