Updated HackRF firmware
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/*
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* Copyright 2016 Dominic Spill <dominicgs@gmail.com>
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "operacake.h"
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#include "hackrf_core.h"
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#include "gpio.h"
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#include "gpio_lpc.h"
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#include "i2c_bus.h"
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#include <libopencm3/lpc43xx/scu.h>
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/*
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* I2C Mode
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*/
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#define OPERACAKE_PIN_OE(x) (x<<7)
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#define OPERACAKE_PIN_U2CTRL1(x) (x<<6)
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#define OPERACAKE_PIN_U2CTRL0(x) (x<<5)
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#define OPERACAKE_PIN_U3CTRL1(x) (x<<4)
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#define OPERACAKE_PIN_U3CTRL0(x) (x<<3)
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#define OPERACAKE_PIN_U1CTRL(x) (x<<2)
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#define OPERACAKE_PIN_LEDEN2(x) (x<<1)
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#define OPERACAKE_PIN_LEDEN(x) (x<<0)
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#define OPERACAKE_PORT_A1 (OPERACAKE_PIN_U2CTRL0(0) | OPERACAKE_PIN_U2CTRL1(0))
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#define OPERACAKE_PORT_A2 (OPERACAKE_PIN_U2CTRL0(1) | OPERACAKE_PIN_U2CTRL1(0))
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#define OPERACAKE_PORT_A3 (OPERACAKE_PIN_U2CTRL0(0) | OPERACAKE_PIN_U2CTRL1(1))
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#define OPERACAKE_PORT_A4 (OPERACAKE_PIN_U2CTRL0(1) | OPERACAKE_PIN_U2CTRL1(1))
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#define OPERACAKE_PORT_B1 (OPERACAKE_PIN_U3CTRL0(0) | OPERACAKE_PIN_U3CTRL1(0))
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#define OPERACAKE_PORT_B2 (OPERACAKE_PIN_U3CTRL0(1) | OPERACAKE_PIN_U3CTRL1(0))
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#define OPERACAKE_PORT_B3 (OPERACAKE_PIN_U3CTRL0(0) | OPERACAKE_PIN_U3CTRL1(1))
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#define OPERACAKE_PORT_B4 (OPERACAKE_PIN_U3CTRL0(1) | OPERACAKE_PIN_U3CTRL1(1))
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#define OPERACAKE_SAMESIDE OPERACAKE_PIN_U1CTRL(1)
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#define OPERACAKE_CROSSOVER OPERACAKE_PIN_U1CTRL(0)
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#define OPERACAKE_EN_LEDS (OPERACAKE_PIN_LEDEN2(1) | OPERACAKE_PIN_LEDEN2(0))
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#define OPERACAKE_GPIO_ENABLE OPERACAKE_PIN_OE(0)
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#define OPERACAKE_GPIO_DISABLE OPERACAKE_PIN_OE(1)
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#define OPERACAKE_REG_INPUT 0x00
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#define OPERACAKE_REG_OUTPUT 0x01
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#define OPERACAKE_REG_POLARITY 0x02
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#define OPERACAKE_REG_CONFIG 0x03
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#define OPERACAKE_DEFAULT_OUTPUT (OPERACAKE_GPIO_DISABLE | OPERACAKE_SAMESIDE \
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| OPERACAKE_PORT_A1 | OPERACAKE_PORT_B1 \
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| OPERACAKE_EN_LEDS)
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#define OPERACAKE_CONFIG_ALL_OUTPUT (0x00)
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// Leave LED bits as outputs
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#define OPERACAKE_CONFIG_GPIO_INPUTS (0x7C)
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#define OPERACAKE_POLARITY_NORMAL (0x00)
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#define OPERACAKE_DEFAULT_ADDRESS 0x18
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i2c_bus_t* const oc_bus = &i2c0;
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uint8_t operacake_boards[8] = {0,0,0,0,0,0,0,0};
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bool allow_gpio_mode = true;
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/* read single register */
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uint8_t operacake_read_reg(i2c_bus_t* const bus, uint8_t address, uint8_t reg) {
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const uint8_t data_tx[] = { reg };
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uint8_t data_rx[] = { 0x00 };
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i2c_bus_transfer(bus, address, data_tx, 1, data_rx, 1);
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return data_rx[0];
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}
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/* Write to one of the PCA9557 registers */
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void operacake_write_reg(i2c_bus_t* const bus, uint8_t address, uint8_t reg, uint8_t value) {
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const uint8_t data[] = {reg, value};
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i2c_bus_transfer(bus, address, data, 2, NULL, 0);
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}
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uint8_t operacake_init(bool allow_gpio) {
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uint8_t reg, addr, i, j = 0;
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/* Find connected operacakes */
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for(i=0; i<8; i++) {
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addr = OPERACAKE_DEFAULT_ADDRESS | i;
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operacake_write_reg(oc_bus, addr, OPERACAKE_REG_OUTPUT,
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OPERACAKE_DEFAULT_OUTPUT);
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operacake_write_reg(oc_bus, addr, OPERACAKE_REG_CONFIG,
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OPERACAKE_CONFIG_ALL_OUTPUT);
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reg = operacake_read_reg(oc_bus, addr, OPERACAKE_REG_CONFIG);
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if(reg==OPERACAKE_CONFIG_ALL_OUTPUT)
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operacake_boards[j++] = addr;
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}
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allow_gpio_mode = allow_gpio;
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return 0;
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}
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uint8_t port_to_pins(uint8_t port) {
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switch(port) {
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case OPERACAKE_PA1:
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return OPERACAKE_PORT_A1;
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case OPERACAKE_PA2:
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return OPERACAKE_PORT_A2;
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case OPERACAKE_PA3:
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return OPERACAKE_PORT_A3;
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case OPERACAKE_PA4:
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return OPERACAKE_PORT_A4;
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case OPERACAKE_PB1:
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return OPERACAKE_PORT_B1;
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case OPERACAKE_PB2:
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return OPERACAKE_PORT_B2;
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case OPERACAKE_PB3:
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return OPERACAKE_PORT_B3;
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case OPERACAKE_PB4:
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return OPERACAKE_PORT_B4;
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}
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return 0xFF;
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}
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uint8_t operacake_set_ports(uint8_t address, uint8_t PA, uint8_t PB) {
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uint8_t side, pa, pb, reg;
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/* Start with some error checking,
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* which should have been done either
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* on the host or elsewhere in firmware
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*/
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if((PA > OPERACAKE_PB4) || (PB > OPERACAKE_PB4)) {
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return 1;
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}
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/* Check which side PA and PB are on */
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if(((PA <= OPERACAKE_PA4) && (PB <= OPERACAKE_PA4))
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|| ((PA > OPERACAKE_PA4) && (PB > OPERACAKE_PA4))) {
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return 1;
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}
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if(PA > OPERACAKE_PA4) {
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side = OPERACAKE_CROSSOVER;
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} else {
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side = OPERACAKE_SAMESIDE;
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}
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pa = port_to_pins(PA);
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pb = port_to_pins(PB);
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reg = (OPERACAKE_GPIO_DISABLE | side
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| pa | pb | OPERACAKE_EN_LEDS);
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operacake_write_reg(oc_bus, address, OPERACAKE_REG_OUTPUT, reg);
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return 0;
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}
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/*
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* Opera Glasses
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*/
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typedef struct {
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uint16_t freq_min;
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uint16_t freq_max;
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uint8_t portA;
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uint8_t portB;
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} operacake_range;
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static operacake_range ranges[MAX_OPERACAKE_RANGES * sizeof(operacake_range)];
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static uint8_t range_idx = 0;
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uint8_t operacake_add_range(uint16_t freq_min, uint16_t freq_max, uint8_t port) {
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if(range_idx >= MAX_OPERACAKE_RANGES) {
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return 1;
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}
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ranges[range_idx].freq_min = freq_min;
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ranges[range_idx].freq_max = freq_max;
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ranges[range_idx].portA = port;
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ranges[range_idx].portB = 7;
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if(port <= OPERACAKE_PA4) {
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ranges[range_idx].portB = range_idx+4;
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} else {
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ranges[range_idx].portB = OPERACAKE_PA1;
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}
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range_idx++;
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return 0;
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}
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#define FREQ_ONE_MHZ (1000000ull)
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static uint8_t current_range = 0xFF;
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uint8_t operacake_set_range(uint32_t freq_mhz) {
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if(range_idx == 0) {
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return 1;
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}
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int i;
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for(i=0; i<range_idx; i++) {
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if((freq_mhz >= ranges[i].freq_min)
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&& (freq_mhz <= ranges[i].freq_max)) {
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break;
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}
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}
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if(i == current_range) {
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return 1;
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}
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operacake_set_ports(operacake_boards[0], ranges[i].portA, ranges[i].portB);
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current_range = i;
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return 0;
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}
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/*
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* GPIO
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*/
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uint16_t gpio_test(uint8_t address)
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{
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uint8_t i, reg, bit_mask, gpio_mask = 0x1F;
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uint16_t result = 0;
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if(!allow_gpio_mode)
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return 0xFFFF;
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scu_pinmux(SCU_PINMUX_GPIO3_8, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
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scu_pinmux(SCU_PINMUX_GPIO3_12, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
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scu_pinmux(SCU_PINMUX_GPIO3_13, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
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scu_pinmux(SCU_PINMUX_GPIO3_14, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
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scu_pinmux(SCU_PINMUX_GPIO3_15, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
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static struct gpio_t gpio_pins[] = {
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GPIO(3, 8), // u1ctrl IO2
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GPIO(3, 14), // u3ctrl0 IO3
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GPIO(3, 15), // u3ctrl1 IO4
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GPIO(3, 12), // u2ctrl0 IO5
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GPIO(3, 13) // u2ctrl1 IO6
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};
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// Setup I2C to put it in GPIO mode
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reg = (OPERACAKE_GPIO_ENABLE | OPERACAKE_EN_LEDS);
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operacake_write_reg(oc_bus, address, OPERACAKE_REG_OUTPUT, reg);
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operacake_write_reg(oc_bus, address, OPERACAKE_REG_CONFIG,
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OPERACAKE_CONFIG_GPIO_INPUTS);
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operacake_write_reg(oc_bus, address, OPERACAKE_REG_POLARITY,
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OPERACAKE_POLARITY_NORMAL);
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// clear state
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for(i=0; i<5; i++) {
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gpio_output(&gpio_pins[i]);
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gpio_write(&gpio_pins[i], 0);
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}
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// Test each pin separately
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for(i=0; i<5; i++) {
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// Set pin high
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gpio_write(&gpio_pins[i], 1);
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// check input
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reg = operacake_read_reg(oc_bus, address, OPERACAKE_REG_INPUT);
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reg >>= 2;
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reg &= gpio_mask;
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bit_mask = 1 << i;
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result <<= 1;
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if(!(reg & bit_mask)) {
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// Is the correct bit set?
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result |= 1;
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}
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result <<= 1;
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if(reg & ~bit_mask) {
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// Are any other bits set?
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result |= 1;
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}
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result <<= 1;
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// set pin low
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gpio_write(&gpio_pins[i], 0);
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// check input
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reg = operacake_read_reg(oc_bus, address, OPERACAKE_REG_INPUT);
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reg >>= 2;
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reg &= gpio_mask;
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bit_mask = 1 << i;
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if(reg & bit_mask) {
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// Is the correct bit clear?
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result |= 1;
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}
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}
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// clean up
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for(i=0; i<5; i++) {
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gpio_input(&gpio_pins[i]);
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}
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// Put it back in to I2C mode and set default pins
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operacake_write_reg(oc_bus, address, OPERACAKE_REG_CONFIG,
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OPERACAKE_CONFIG_ALL_OUTPUT);
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operacake_write_reg(oc_bus, address, OPERACAKE_REG_OUTPUT,
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OPERACAKE_DEFAULT_OUTPUT);
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return result;
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}
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